commit_impl.hh revision 8834:21e8d54ecf07
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "config/the_isa.hh" 51#include "config/use_checker.hh" 52#include "cpu/o3/commit.hh" 53#include "cpu/o3/thread_state.hh" 54#include "cpu/base.hh" 55#include "cpu/exetrace.hh" 56#include "cpu/timebuf.hh" 57#include "debug/Activity.hh" 58#include "debug/Commit.hh" 59#include "debug/CommitRate.hh" 60#include "debug/ExecFaulting.hh" 61#include "debug/O3PipeView.hh" 62#include "params/DerivO3CPU.hh" 63#include "sim/faults.hh" 64#include "sim/full_system.hh" 65 66#if USE_CHECKER 67#include "cpu/checker/cpu.hh" 68#endif 69 70using namespace std; 71 72template <class Impl> 73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 74 ThreadID _tid) 75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 76{ 77} 78 79template <class Impl> 80void 81DefaultCommit<Impl>::TrapEvent::process() 82{ 83 // This will get reset by commit if it was switched out at the 84 // time of this event processing. 85 commit->trapSquash[tid] = true; 86} 87 88template <class Impl> 89const char * 90DefaultCommit<Impl>::TrapEvent::description() const 91{ 92 return "Trap"; 93} 94 95template <class Impl> 96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 97 : cpu(_cpu), 98 squashCounter(0), 99 iewToCommitDelay(params->iewToCommitDelay), 100 commitToIEWDelay(params->commitToIEWDelay), 101 renameToROBDelay(params->renameToROBDelay), 102 fetchToCommitDelay(params->commitToFetchDelay), 103 renameWidth(params->renameWidth), 104 commitWidth(params->commitWidth), 105 numThreads(params->numThreads), 106 drainPending(false), 107 switchedOut(false), 108 trapLatency(params->trapLatency), 109 canHandleInterrupts(true) 110{ 111 _status = Active; 112 _nextStatus = Inactive; 113 std::string policy = params->smtCommitPolicy; 114 115 //Convert string to lowercase 116 std::transform(policy.begin(), policy.end(), policy.begin(), 117 (int(*)(int)) tolower); 118 119 //Assign commit policy 120 if (policy == "aggressive"){ 121 commitPolicy = Aggressive; 122 123 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 124 } else if (policy == "roundrobin"){ 125 commitPolicy = RoundRobin; 126 127 //Set-Up Priority List 128 for (ThreadID tid = 0; tid < numThreads; tid++) { 129 priority_list.push_back(tid); 130 } 131 132 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 133 } else if (policy == "oldestready"){ 134 commitPolicy = OldestReady; 135 136 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 137 } else { 138 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 139 "RoundRobin,OldestReady}"); 140 } 141 142 for (ThreadID tid = 0; tid < numThreads; tid++) { 143 commitStatus[tid] = Idle; 144 changedROBNumEntries[tid] = false; 145 checkEmptyROB[tid] = false; 146 trapInFlight[tid] = false; 147 committedStores[tid] = false; 148 trapSquash[tid] = false; 149 tcSquash[tid] = false; 150 pc[tid].set(0); 151 lastCommitedSeqNum[tid] = 0; 152 } 153 interrupt = NoFault; 154} 155 156template <class Impl> 157std::string 158DefaultCommit<Impl>::name() const 159{ 160 return cpu->name() + ".commit"; 161} 162 163template <class Impl> 164void 165DefaultCommit<Impl>::regStats() 166{ 167 using namespace Stats; 168 commitCommittedInsts 169 .name(name() + ".commitCommittedInsts") 170 .desc("The number of committed instructions") 171 .prereq(commitCommittedInsts); 172 commitCommittedOps 173 .name(name() + ".commitCommittedOps") 174 .desc("The number of committed instructions") 175 .prereq(commitCommittedInsts); 176 commitSquashedInsts 177 .name(name() + ".commitSquashedInsts") 178 .desc("The number of squashed insts skipped by commit") 179 .prereq(commitSquashedInsts); 180 commitSquashEvents 181 .name(name() + ".commitSquashEvents") 182 .desc("The number of times commit is told to squash") 183 .prereq(commitSquashEvents); 184 commitNonSpecStalls 185 .name(name() + ".commitNonSpecStalls") 186 .desc("The number of times commit has been forced to stall to " 187 "communicate backwards") 188 .prereq(commitNonSpecStalls); 189 branchMispredicts 190 .name(name() + ".branchMispredicts") 191 .desc("The number of times a branch was mispredicted") 192 .prereq(branchMispredicts); 193 numCommittedDist 194 .init(0,commitWidth,1) 195 .name(name() + ".committed_per_cycle") 196 .desc("Number of insts commited each cycle") 197 .flags(Stats::pdf) 198 ; 199 200 instsCommitted 201 .init(cpu->numThreads) 202 .name(name() + ".committedInsts") 203 .desc("Number of instructions committed") 204 .flags(total) 205 ; 206 207 opsCommitted 208 .init(cpu->numThreads) 209 .name(name() + ".committedOps") 210 .desc("Number of ops (including micro ops) committed") 211 .flags(total) 212 ; 213 214 statComSwp 215 .init(cpu->numThreads) 216 .name(name() + ".swp_count") 217 .desc("Number of s/w prefetches committed") 218 .flags(total) 219 ; 220 221 statComRefs 222 .init(cpu->numThreads) 223 .name(name() + ".refs") 224 .desc("Number of memory references committed") 225 .flags(total) 226 ; 227 228 statComLoads 229 .init(cpu->numThreads) 230 .name(name() + ".loads") 231 .desc("Number of loads committed") 232 .flags(total) 233 ; 234 235 statComMembars 236 .init(cpu->numThreads) 237 .name(name() + ".membars") 238 .desc("Number of memory barriers committed") 239 .flags(total) 240 ; 241 242 statComBranches 243 .init(cpu->numThreads) 244 .name(name() + ".branches") 245 .desc("Number of branches committed") 246 .flags(total) 247 ; 248 249 statComFloating 250 .init(cpu->numThreads) 251 .name(name() + ".fp_insts") 252 .desc("Number of committed floating point instructions.") 253 .flags(total) 254 ; 255 256 statComInteger 257 .init(cpu->numThreads) 258 .name(name()+".int_insts") 259 .desc("Number of committed integer instructions.") 260 .flags(total) 261 ; 262 263 statComFunctionCalls 264 .init(cpu->numThreads) 265 .name(name()+".function_calls") 266 .desc("Number of function calls committed.") 267 .flags(total) 268 ; 269 270 commitEligible 271 .init(cpu->numThreads) 272 .name(name() + ".bw_limited") 273 .desc("number of insts not committed due to BW limits") 274 .flags(total) 275 ; 276 277 commitEligibleSamples 278 .name(name() + ".bw_lim_events") 279 .desc("number cycles where commit BW limit reached") 280 ; 281} 282 283template <class Impl> 284void 285DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 286{ 287 thread = threads; 288} 289 290template <class Impl> 291void 292DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 293{ 294 timeBuffer = tb_ptr; 295 296 // Setup wire to send information back to IEW. 297 toIEW = timeBuffer->getWire(0); 298 299 // Setup wire to read data from IEW (for the ROB). 300 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 301} 302 303template <class Impl> 304void 305DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 306{ 307 fetchQueue = fq_ptr; 308 309 // Setup wire to get instructions from rename (for the ROB). 310 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 311} 312 313template <class Impl> 314void 315DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 316{ 317 renameQueue = rq_ptr; 318 319 // Setup wire to get instructions from rename (for the ROB). 320 fromRename = renameQueue->getWire(-renameToROBDelay); 321} 322 323template <class Impl> 324void 325DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 326{ 327 iewQueue = iq_ptr; 328 329 // Setup wire to get instructions from IEW. 330 fromIEW = iewQueue->getWire(-iewToCommitDelay); 331} 332 333template <class Impl> 334void 335DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 336{ 337 iewStage = iew_stage; 338} 339 340template<class Impl> 341void 342DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 343{ 344 activeThreads = at_ptr; 345} 346 347template <class Impl> 348void 349DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 350{ 351 for (ThreadID tid = 0; tid < numThreads; tid++) 352 renameMap[tid] = &rm_ptr[tid]; 353} 354 355template <class Impl> 356void 357DefaultCommit<Impl>::setROB(ROB *rob_ptr) 358{ 359 rob = rob_ptr; 360} 361 362template <class Impl> 363void 364DefaultCommit<Impl>::initStage() 365{ 366 rob->setActiveThreads(activeThreads); 367 rob->resetEntries(); 368 369 // Broadcast the number of free entries. 370 for (ThreadID tid = 0; tid < numThreads; tid++) { 371 toIEW->commitInfo[tid].usedROB = true; 372 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 373 toIEW->commitInfo[tid].emptyROB = true; 374 } 375 376 // Commit must broadcast the number of free entries it has at the 377 // start of the simulation, so it starts as active. 378 cpu->activateStage(O3CPU::CommitIdx); 379 380 cpu->activityThisCycle(); 381 trapLatency = cpu->ticks(trapLatency); 382} 383 384template <class Impl> 385bool 386DefaultCommit<Impl>::drain() 387{ 388 drainPending = true; 389 390 return false; 391} 392 393template <class Impl> 394void 395DefaultCommit<Impl>::switchOut() 396{ 397 switchedOut = true; 398 drainPending = false; 399 rob->switchOut(); 400} 401 402template <class Impl> 403void 404DefaultCommit<Impl>::resume() 405{ 406 drainPending = false; 407} 408 409template <class Impl> 410void 411DefaultCommit<Impl>::takeOverFrom() 412{ 413 switchedOut = false; 414 _status = Active; 415 _nextStatus = Inactive; 416 for (ThreadID tid = 0; tid < numThreads; tid++) { 417 commitStatus[tid] = Idle; 418 changedROBNumEntries[tid] = false; 419 trapSquash[tid] = false; 420 tcSquash[tid] = false; 421 } 422 squashCounter = 0; 423 rob->takeOverFrom(); 424} 425 426template <class Impl> 427void 428DefaultCommit<Impl>::updateStatus() 429{ 430 // reset ROB changed variable 431 list<ThreadID>::iterator threads = activeThreads->begin(); 432 list<ThreadID>::iterator end = activeThreads->end(); 433 434 while (threads != end) { 435 ThreadID tid = *threads++; 436 437 changedROBNumEntries[tid] = false; 438 439 // Also check if any of the threads has a trap pending 440 if (commitStatus[tid] == TrapPending || 441 commitStatus[tid] == FetchTrapPending) { 442 _nextStatus = Active; 443 } 444 } 445 446 if (_nextStatus == Inactive && _status == Active) { 447 DPRINTF(Activity, "Deactivating stage.\n"); 448 cpu->deactivateStage(O3CPU::CommitIdx); 449 } else if (_nextStatus == Active && _status == Inactive) { 450 DPRINTF(Activity, "Activating stage.\n"); 451 cpu->activateStage(O3CPU::CommitIdx); 452 } 453 454 _status = _nextStatus; 455} 456 457template <class Impl> 458void 459DefaultCommit<Impl>::setNextStatus() 460{ 461 int squashes = 0; 462 463 list<ThreadID>::iterator threads = activeThreads->begin(); 464 list<ThreadID>::iterator end = activeThreads->end(); 465 466 while (threads != end) { 467 ThreadID tid = *threads++; 468 469 if (commitStatus[tid] == ROBSquashing) { 470 squashes++; 471 } 472 } 473 474 squashCounter = squashes; 475 476 // If commit is currently squashing, then it will have activity for the 477 // next cycle. Set its next status as active. 478 if (squashCounter) { 479 _nextStatus = Active; 480 } 481} 482 483template <class Impl> 484bool 485DefaultCommit<Impl>::changedROBEntries() 486{ 487 list<ThreadID>::iterator threads = activeThreads->begin(); 488 list<ThreadID>::iterator end = activeThreads->end(); 489 490 while (threads != end) { 491 ThreadID tid = *threads++; 492 493 if (changedROBNumEntries[tid]) { 494 return true; 495 } 496 } 497 498 return false; 499} 500 501template <class Impl> 502size_t 503DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 504{ 505 return rob->numFreeEntries(tid); 506} 507 508template <class Impl> 509void 510DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 511{ 512 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 513 514 TrapEvent *trap = new TrapEvent(this, tid); 515 516 cpu->schedule(trap, curTick() + trapLatency); 517 trapInFlight[tid] = true; 518 thread[tid]->trapPending = true; 519} 520 521template <class Impl> 522void 523DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 524{ 525 assert(!trapInFlight[tid]); 526 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 527 528 tcSquash[tid] = true; 529} 530 531template <class Impl> 532void 533DefaultCommit<Impl>::squashAll(ThreadID tid) 534{ 535 // If we want to include the squashing instruction in the squash, 536 // then use one older sequence number. 537 // Hopefully this doesn't mess things up. Basically I want to squash 538 // all instructions of this thread. 539 InstSeqNum squashed_inst = rob->isEmpty() ? 540 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 541 542 // All younger instructions will be squashed. Set the sequence 543 // number as the youngest instruction in the ROB (0 in this case. 544 // Hopefully nothing breaks.) 545 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 546 547 rob->squash(squashed_inst, tid); 548 changedROBNumEntries[tid] = true; 549 550 // Send back the sequence number of the squashed instruction. 551 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 552 553 // Send back the squash signal to tell stages that they should 554 // squash. 555 toIEW->commitInfo[tid].squash = true; 556 557 // Send back the rob squashing signal so other stages know that 558 // the ROB is in the process of squashing. 559 toIEW->commitInfo[tid].robSquashing = true; 560 561 toIEW->commitInfo[tid].mispredictInst = NULL; 562 toIEW->commitInfo[tid].squashInst = NULL; 563 564 toIEW->commitInfo[tid].pc = pc[tid]; 565} 566 567template <class Impl> 568void 569DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 570{ 571 squashAll(tid); 572 573 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 574 575 thread[tid]->trapPending = false; 576 thread[tid]->inSyscall = false; 577 trapInFlight[tid] = false; 578 579 trapSquash[tid] = false; 580 581 commitStatus[tid] = ROBSquashing; 582 cpu->activityThisCycle(); 583} 584 585template <class Impl> 586void 587DefaultCommit<Impl>::squashFromTC(ThreadID tid) 588{ 589 squashAll(tid); 590 591 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 592 593 thread[tid]->inSyscall = false; 594 assert(!thread[tid]->trapPending); 595 596 commitStatus[tid] = ROBSquashing; 597 cpu->activityThisCycle(); 598 599 tcSquash[tid] = false; 600} 601 602template <class Impl> 603void 604DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst, 605 uint64_t squash_after_seq_num) 606{ 607 youngestSeqNum[tid] = squash_after_seq_num; 608 609 rob->squash(squash_after_seq_num, tid); 610 changedROBNumEntries[tid] = true; 611 612 // Send back the sequence number of the squashed instruction. 613 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 614 615 toIEW->commitInfo[tid].squashInst = head_inst; 616 // Send back the squash signal to tell stages that they should squash. 617 toIEW->commitInfo[tid].squash = true; 618 619 // Send back the rob squashing signal so other stages know that 620 // the ROB is in the process of squashing. 621 toIEW->commitInfo[tid].robSquashing = true; 622 623 toIEW->commitInfo[tid].mispredictInst = NULL; 624 625 toIEW->commitInfo[tid].pc = pc[tid]; 626 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 627 tid, squash_after_seq_num); 628 commitStatus[tid] = ROBSquashing; 629} 630 631template <class Impl> 632void 633DefaultCommit<Impl>::tick() 634{ 635 wroteToTimeBuffer = false; 636 _nextStatus = Inactive; 637 638 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 639 cpu->signalDrained(); 640 drainPending = false; 641 return; 642 } 643 644 if (activeThreads->empty()) 645 return; 646 647 list<ThreadID>::iterator threads = activeThreads->begin(); 648 list<ThreadID>::iterator end = activeThreads->end(); 649 650 // Check if any of the threads are done squashing. Change the 651 // status if they are done. 652 while (threads != end) { 653 ThreadID tid = *threads++; 654 655 // Clear the bit saying if the thread has committed stores 656 // this cycle. 657 committedStores[tid] = false; 658 659 if (commitStatus[tid] == ROBSquashing) { 660 661 if (rob->isDoneSquashing(tid)) { 662 commitStatus[tid] = Running; 663 } else { 664 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 665 " insts this cycle.\n", tid); 666 rob->doSquash(tid); 667 toIEW->commitInfo[tid].robSquashing = true; 668 wroteToTimeBuffer = true; 669 } 670 } 671 } 672 673 commit(); 674 675 markCompletedInsts(); 676 677 threads = activeThreads->begin(); 678 679 while (threads != end) { 680 ThreadID tid = *threads++; 681 682 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 683 // The ROB has more instructions it can commit. Its next status 684 // will be active. 685 _nextStatus = Active; 686 687 DynInstPtr inst = rob->readHeadInst(tid); 688 689 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 690 " ROB and ready to commit\n", 691 tid, inst->seqNum, inst->pcState()); 692 693 } else if (!rob->isEmpty(tid)) { 694 DynInstPtr inst = rob->readHeadInst(tid); 695 696 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 697 "%s is head of ROB and not ready\n", 698 tid, inst->seqNum, inst->pcState()); 699 } 700 701 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 702 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 703 } 704 705 706 if (wroteToTimeBuffer) { 707 DPRINTF(Activity, "Activity This Cycle.\n"); 708 cpu->activityThisCycle(); 709 } 710 711 updateStatus(); 712} 713 714template <class Impl> 715void 716DefaultCommit<Impl>::handleInterrupt() 717{ 718 // Verify that we still have an interrupt to handle 719 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 720 DPRINTF(Commit, "Pending interrupt is cleared by master before " 721 "it got handled. Restart fetching from the orig path.\n"); 722 toIEW->commitInfo[0].clearInterrupt = true; 723 interrupt = NoFault; 724 return; 725 } 726 727 // Wait until all in flight instructions are finished before enterring 728 // the interrupt. 729 if (canHandleInterrupts && cpu->instList.empty()) { 730 // Squash or record that I need to squash this cycle if 731 // an interrupt needed to be handled. 732 DPRINTF(Commit, "Interrupt detected.\n"); 733 734 // Clear the interrupt now that it's going to be handled 735 toIEW->commitInfo[0].clearInterrupt = true; 736 737 assert(!thread[0]->inSyscall); 738 thread[0]->inSyscall = true; 739 740#if USE_CHECKER 741 if (cpu->checker) { 742 cpu->checker->handlePendingInt(); 743 } 744#endif 745 746 // CPU will handle interrupt. 747 cpu->processInterrupts(interrupt); 748 749 thread[0]->inSyscall = false; 750 751 commitStatus[0] = TrapPending; 752 753 // Generate trap squash event. 754 generateTrapEvent(0); 755 756 interrupt = NoFault; 757 } else { 758 DPRINTF(Commit, "Interrupt pending: instruction is %sin " 759 "flight, ROB is %sempty\n", 760 canHandleInterrupts ? "not " : "", 761 cpu->instList.empty() ? "" : "not " ); 762 } 763} 764 765template <class Impl> 766void 767DefaultCommit<Impl>::propagateInterrupt() 768{ 769 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 770 tcSquash[0]) 771 return; 772 773 // Process interrupts if interrupts are enabled, not in PAL 774 // mode, and no other traps or external squashes are currently 775 // pending. 776 // @todo: Allow other threads to handle interrupts. 777 778 // Get any interrupt that happened 779 interrupt = cpu->getInterrupts(); 780 781 // Tell fetch that there is an interrupt pending. This 782 // will make fetch wait until it sees a non PAL-mode PC, 783 // at which point it stops fetching instructions. 784 if (interrupt != NoFault) 785 toIEW->commitInfo[0].interruptPending = true; 786} 787 788template <class Impl> 789void 790DefaultCommit<Impl>::commit() 791{ 792 if (FullSystem) { 793 // Check if we have a interrupt and get read to handle it 794 if (cpu->checkInterrupts(cpu->tcBase(0))) 795 propagateInterrupt(); 796 } 797 798 //////////////////////////////////// 799 // Check for any possible squashes, handle them first 800 //////////////////////////////////// 801 list<ThreadID>::iterator threads = activeThreads->begin(); 802 list<ThreadID>::iterator end = activeThreads->end(); 803 804 while (threads != end) { 805 ThreadID tid = *threads++; 806 807 // Not sure which one takes priority. I think if we have 808 // both, that's a bad sign. 809 if (trapSquash[tid] == true) { 810 assert(!tcSquash[tid]); 811 squashFromTrap(tid); 812 } else if (tcSquash[tid] == true) { 813 assert(commitStatus[tid] != TrapPending); 814 squashFromTC(tid); 815 } 816 817 // Squashed sequence number must be older than youngest valid 818 // instruction in the ROB. This prevents squashes from younger 819 // instructions overriding squashes from older instructions. 820 if (fromIEW->squash[tid] && 821 commitStatus[tid] != TrapPending && 822 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 823 824 if (fromIEW->mispredictInst[tid]) { 825 DPRINTF(Commit, 826 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 827 tid, 828 fromIEW->mispredictInst[tid]->instAddr(), 829 fromIEW->squashedSeqNum[tid]); 830 } else { 831 DPRINTF(Commit, 832 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 833 tid, fromIEW->squashedSeqNum[tid]); 834 } 835 836 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 837 tid, 838 fromIEW->pc[tid].nextInstAddr()); 839 840 commitStatus[tid] = ROBSquashing; 841 842 // If we want to include the squashing instruction in the squash, 843 // then use one older sequence number. 844 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 845 846 if (fromIEW->includeSquashInst[tid] == true) { 847 squashed_inst--; 848 } 849 850 // All younger instructions will be squashed. Set the sequence 851 // number as the youngest instruction in the ROB. 852 youngestSeqNum[tid] = squashed_inst; 853 854 rob->squash(squashed_inst, tid); 855 changedROBNumEntries[tid] = true; 856 857 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 858 859 toIEW->commitInfo[tid].squash = true; 860 861 // Send back the rob squashing signal so other stages know that 862 // the ROB is in the process of squashing. 863 toIEW->commitInfo[tid].robSquashing = true; 864 865 toIEW->commitInfo[tid].mispredictInst = 866 fromIEW->mispredictInst[tid]; 867 toIEW->commitInfo[tid].branchTaken = 868 fromIEW->branchTaken[tid]; 869 toIEW->commitInfo[tid].squashInst = 870 rob->findInst(tid, squashed_inst); 871 872 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 873 874 if (toIEW->commitInfo[tid].mispredictInst) { 875 ++branchMispredicts; 876 } 877 } 878 879 } 880 881 setNextStatus(); 882 883 if (squashCounter != numThreads) { 884 // If we're not currently squashing, then get instructions. 885 getInsts(); 886 887 // Try to commit any instructions. 888 commitInsts(); 889 } 890 891 //Check for any activity 892 threads = activeThreads->begin(); 893 894 while (threads != end) { 895 ThreadID tid = *threads++; 896 897 if (changedROBNumEntries[tid]) { 898 toIEW->commitInfo[tid].usedROB = true; 899 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 900 901 wroteToTimeBuffer = true; 902 changedROBNumEntries[tid] = false; 903 if (rob->isEmpty(tid)) 904 checkEmptyROB[tid] = true; 905 } 906 907 // ROB is only considered "empty" for previous stages if: a) 908 // ROB is empty, b) there are no outstanding stores, c) IEW 909 // stage has received any information regarding stores that 910 // committed. 911 // c) is checked by making sure to not consider the ROB empty 912 // on the same cycle as when stores have been committed. 913 // @todo: Make this handle multi-cycle communication between 914 // commit and IEW. 915 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 916 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 917 checkEmptyROB[tid] = false; 918 toIEW->commitInfo[tid].usedROB = true; 919 toIEW->commitInfo[tid].emptyROB = true; 920 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 921 wroteToTimeBuffer = true; 922 } 923 924 } 925} 926 927template <class Impl> 928void 929DefaultCommit<Impl>::commitInsts() 930{ 931 //////////////////////////////////// 932 // Handle commit 933 // Note that commit will be handled prior to putting new 934 // instructions in the ROB so that the ROB only tries to commit 935 // instructions it has in this current cycle, and not instructions 936 // it is writing in during this cycle. Can't commit and squash 937 // things at the same time... 938 //////////////////////////////////// 939 940 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 941 942 unsigned num_committed = 0; 943 944 DynInstPtr head_inst; 945 946 // Commit as many instructions as possible until the commit bandwidth 947 // limit is reached, or it becomes impossible to commit any more. 948 while (num_committed < commitWidth) { 949 // Check for any interrupt that we've already squashed for 950 // and start processing it. 951 if (interrupt != NoFault) 952 handleInterrupt(); 953 954 int commit_thread = getCommittingThread(); 955 956 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 957 break; 958 959 head_inst = rob->readHeadInst(commit_thread); 960 961 ThreadID tid = head_inst->threadNumber; 962 963 assert(tid == commit_thread); 964 965 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 966 head_inst->seqNum, tid); 967 968 // If the head instruction is squashed, it is ready to retire 969 // (be removed from the ROB) at any time. 970 if (head_inst->isSquashed()) { 971 972 DPRINTF(Commit, "Retiring squashed instruction from " 973 "ROB.\n"); 974 975 rob->retireHead(commit_thread); 976 977 ++commitSquashedInsts; 978 979 // Record that the number of ROB entries has changed. 980 changedROBNumEntries[tid] = true; 981 } else { 982 pc[tid] = head_inst->pcState(); 983 984 // Increment the total number of non-speculative instructions 985 // executed. 986 // Hack for now: it really shouldn't happen until after the 987 // commit is deemed to be successful, but this count is needed 988 // for syscalls. 989 thread[tid]->funcExeInst++; 990 991 // Try to commit the head instruction. 992 bool commit_success = commitHead(head_inst, num_committed); 993 994 if (commit_success) { 995 ++num_committed; 996 997 changedROBNumEntries[tid] = true; 998 999 // Set the doneSeqNum to the youngest committed instruction. 1000 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 1001 1002 if (!head_inst->isMicroop() || head_inst->isLastMicroop()) 1003 ++commitCommittedInsts; 1004 ++commitCommittedOps; 1005 1006 // To match the old model, don't count nops and instruction 1007 // prefetches towards the total commit count. 1008 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 1009 cpu->instDone(tid, head_inst); 1010 } 1011 1012 if (tid == 0) { 1013 canHandleInterrupts = (!head_inst->isDelayedCommit()) && 1014 ((THE_ISA != ALPHA_ISA) || 1015 (!(pc[0].instAddr() & 0x3))); 1016 } 1017 1018 // Updates misc. registers. 1019 head_inst->updateMiscRegs(); 1020 1021 cpu->traceFunctions(pc[tid].instAddr()); 1022 1023 TheISA::advancePC(pc[tid], head_inst->staticInst); 1024 1025 // Keep track of the last sequence number commited 1026 lastCommitedSeqNum[tid] = head_inst->seqNum; 1027 1028 // If this is an instruction that doesn't play nicely with 1029 // others squash everything and restart fetch 1030 if (head_inst->isSquashAfter()) 1031 squashAfter(tid, head_inst, head_inst->seqNum); 1032 1033 int count = 0; 1034 Addr oldpc; 1035 // Debug statement. Checks to make sure we're not 1036 // currently updating state while handling PC events. 1037 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 1038 do { 1039 oldpc = pc[tid].instAddr(); 1040 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1041 count++; 1042 } while (oldpc != pc[tid].instAddr()); 1043 if (count > 1) { 1044 DPRINTF(Commit, 1045 "PC skip function event, stopping commit\n"); 1046 break; 1047 } 1048 } else { 1049 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1050 "[tid:%i] [sn:%i].\n", 1051 head_inst->pcState(), tid ,head_inst->seqNum); 1052 break; 1053 } 1054 } 1055 } 1056 1057 DPRINTF(CommitRate, "%i\n", num_committed); 1058 numCommittedDist.sample(num_committed); 1059 1060 if (num_committed == commitWidth) { 1061 commitEligibleSamples++; 1062 } 1063} 1064 1065template <class Impl> 1066bool 1067DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1068{ 1069 assert(head_inst); 1070 1071 ThreadID tid = head_inst->threadNumber; 1072 1073 // If the instruction is not executed yet, then it will need extra 1074 // handling. Signal backwards that it should be executed. 1075 if (!head_inst->isExecuted()) { 1076 // Keep this number correct. We have not yet actually executed 1077 // and committed this instruction. 1078 thread[tid]->funcExeInst--; 1079 1080 if (head_inst->isNonSpeculative() || 1081 head_inst->isStoreConditional() || 1082 head_inst->isMemBarrier() || 1083 head_inst->isWriteBarrier()) { 1084 1085 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1086 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1087 head_inst->seqNum, head_inst->pcState()); 1088 1089 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1090 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1091 return false; 1092 } 1093 1094 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1095 1096 // Change the instruction so it won't try to commit again until 1097 // it is executed. 1098 head_inst->clearCanCommit(); 1099 1100 ++commitNonSpecStalls; 1101 1102 return false; 1103 } else if (head_inst->isLoad()) { 1104 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1105 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1106 return false; 1107 } 1108 1109 assert(head_inst->uncacheable()); 1110 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1111 head_inst->seqNum, head_inst->pcState()); 1112 1113 // Send back the non-speculative instruction's sequence 1114 // number. Tell the lsq to re-execute the load. 1115 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1116 toIEW->commitInfo[tid].uncached = true; 1117 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1118 1119 head_inst->clearCanCommit(); 1120 1121 return false; 1122 } else { 1123 panic("Trying to commit un-executed instruction " 1124 "of unknown type!\n"); 1125 } 1126 } 1127 1128 if (head_inst->isThreadSync()) { 1129 // Not handled for now. 1130 panic("Thread sync instructions are not handled yet.\n"); 1131 } 1132 1133 // Check if the instruction caused a fault. If so, trap. 1134 Fault inst_fault = head_inst->getFault(); 1135 1136 // Stores mark themselves as completed. 1137 if (!head_inst->isStore() && inst_fault == NoFault) { 1138 head_inst->setCompleted(); 1139 } 1140 1141#if USE_CHECKER 1142 // Use checker prior to updating anything due to traps or PC 1143 // based events. 1144 if (cpu->checker) { 1145 cpu->checker->verify(head_inst); 1146 } 1147#endif 1148 1149 if (inst_fault != NoFault) { 1150 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1151 head_inst->seqNum, head_inst->pcState()); 1152 1153 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1154 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1155 return false; 1156 } 1157 1158 head_inst->setCompleted(); 1159 1160#if USE_CHECKER 1161 if (cpu->checker) { 1162 // Need to check the instruction before its fault is processed 1163 cpu->checker->verify(head_inst); 1164 } 1165#endif 1166 1167 assert(!thread[tid]->inSyscall); 1168 1169 // Mark that we're in state update mode so that the trap's 1170 // execution doesn't generate extra squashes. 1171 thread[tid]->inSyscall = true; 1172 1173 // Execute the trap. Although it's slightly unrealistic in 1174 // terms of timing (as it doesn't wait for the full timing of 1175 // the trap event to complete before updating state), it's 1176 // needed to update the state as soon as possible. This 1177 // prevents external agents from changing any specific state 1178 // that the trap need. 1179 cpu->trap(inst_fault, tid, head_inst->staticInst); 1180 1181 // Exit state update mode to avoid accidental updating. 1182 thread[tid]->inSyscall = false; 1183 1184 commitStatus[tid] = TrapPending; 1185 1186 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1187 head_inst->seqNum); 1188 if (head_inst->traceData) { 1189 if (DTRACE(ExecFaulting)) { 1190 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1191 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1192 head_inst->traceData->dump(); 1193 } 1194 delete head_inst->traceData; 1195 head_inst->traceData = NULL; 1196 } 1197 1198 // Generate trap squash event. 1199 generateTrapEvent(tid); 1200 return false; 1201 } 1202 1203 updateComInstStats(head_inst); 1204 1205 if (FullSystem) { 1206 if (thread[tid]->profile) { 1207 thread[tid]->profilePC = head_inst->instAddr(); 1208 ProfileNode *node = thread[tid]->profile->consume( 1209 thread[tid]->getTC(), head_inst->staticInst); 1210 1211 if (node) 1212 thread[tid]->profileNode = node; 1213 } 1214 if (CPA::available()) { 1215 if (head_inst->isControl()) { 1216 ThreadContext *tc = thread[tid]->getTC(); 1217 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1218 } 1219 } 1220 } 1221 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1222 head_inst->seqNum, head_inst->pcState()); 1223 if (head_inst->traceData) { 1224 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1225 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1226 head_inst->traceData->dump(); 1227 delete head_inst->traceData; 1228 head_inst->traceData = NULL; 1229 } 1230 1231 // Update the commit rename map 1232 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1233 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1234 head_inst->renamedDestRegIdx(i)); 1235 } 1236 1237 // Finally clear the head ROB entry. 1238 rob->retireHead(tid); 1239 1240#if TRACING_ON 1241 // Print info needed by the pipeline activity viewer. 1242 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 1243 head_inst->fetchTick, 1244 head_inst->instAddr(), 1245 head_inst->microPC(), 1246 head_inst->seqNum, 1247 head_inst->staticInst->disassemble(head_inst->instAddr())); 1248 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick); 1249 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick); 1250 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick); 1251 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick); 1252 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick); 1253 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick()); 1254#endif 1255 1256 // If this was a store, record it for this cycle. 1257 if (head_inst->isStore()) 1258 committedStores[tid] = true; 1259 1260 // Return true to indicate that we have committed an instruction. 1261 return true; 1262} 1263 1264template <class Impl> 1265void 1266DefaultCommit<Impl>::getInsts() 1267{ 1268 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1269 1270 // Read any renamed instructions and place them into the ROB. 1271 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1272 1273 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1274 DynInstPtr inst; 1275 1276 inst = fromRename->insts[inst_num]; 1277 ThreadID tid = inst->threadNumber; 1278 1279 if (!inst->isSquashed() && 1280 commitStatus[tid] != ROBSquashing && 1281 commitStatus[tid] != TrapPending) { 1282 changedROBNumEntries[tid] = true; 1283 1284 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1285 inst->pcState(), inst->seqNum, tid); 1286 1287 rob->insertInst(inst); 1288 1289 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1290 1291 youngestSeqNum[tid] = inst->seqNum; 1292 } else { 1293 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1294 "squashed, skipping.\n", 1295 inst->pcState(), inst->seqNum, tid); 1296 } 1297 } 1298} 1299 1300template <class Impl> 1301void 1302DefaultCommit<Impl>::skidInsert() 1303{ 1304 DPRINTF(Commit, "Attempting to any instructions from rename into " 1305 "skidBuffer.\n"); 1306 1307 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1308 DynInstPtr inst = fromRename->insts[inst_num]; 1309 1310 if (!inst->isSquashed()) { 1311 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1312 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1313 inst->threadNumber); 1314 skidBuffer.push(inst); 1315 } else { 1316 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1317 "squashed, skipping.\n", 1318 inst->pcState(), inst->seqNum, inst->threadNumber); 1319 } 1320 } 1321} 1322 1323template <class Impl> 1324void 1325DefaultCommit<Impl>::markCompletedInsts() 1326{ 1327 // Grab completed insts out of the IEW instruction queue, and mark 1328 // instructions completed within the ROB. 1329 for (int inst_num = 0; 1330 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1331 ++inst_num) 1332 { 1333 if (!fromIEW->insts[inst_num]->isSquashed()) { 1334 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1335 "within ROB.\n", 1336 fromIEW->insts[inst_num]->threadNumber, 1337 fromIEW->insts[inst_num]->pcState(), 1338 fromIEW->insts[inst_num]->seqNum); 1339 1340 // Mark the instruction as ready to commit. 1341 fromIEW->insts[inst_num]->setCanCommit(); 1342 } 1343 } 1344} 1345 1346template <class Impl> 1347bool 1348DefaultCommit<Impl>::robDoneSquashing() 1349{ 1350 list<ThreadID>::iterator threads = activeThreads->begin(); 1351 list<ThreadID>::iterator end = activeThreads->end(); 1352 1353 while (threads != end) { 1354 ThreadID tid = *threads++; 1355 1356 if (!rob->isDoneSquashing(tid)) 1357 return false; 1358 } 1359 1360 return true; 1361} 1362 1363template <class Impl> 1364void 1365DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1366{ 1367 ThreadID tid = inst->threadNumber; 1368 1369 // 1370 // Pick off the software prefetches 1371 // 1372#ifdef TARGET_ALPHA 1373 if (inst->isDataPrefetch()) { 1374 statComSwp[tid]++; 1375 } else { 1376 if (!inst->isMicroop() || inst->isLastMicroop()) 1377 instsCommitted[tid]++; 1378 opsCommitted[tid]++; 1379 } 1380#else 1381 if (!inst->isMicroop() || inst->isLastMicroop()) 1382 instsCommitted[tid]++; 1383 opsCommitted[tid]++; 1384#endif 1385 1386 // 1387 // Control Instructions 1388 // 1389 if (inst->isControl()) 1390 statComBranches[tid]++; 1391 1392 // 1393 // Memory references 1394 // 1395 if (inst->isMemRef()) { 1396 statComRefs[tid]++; 1397 1398 if (inst->isLoad()) { 1399 statComLoads[tid]++; 1400 } 1401 } 1402 1403 if (inst->isMemBarrier()) { 1404 statComMembars[tid]++; 1405 } 1406 1407 // Integer Instruction 1408 if (inst->isInteger()) 1409 statComInteger[tid]++; 1410 1411 // Floating Point Instruction 1412 if (inst->isFloating()) 1413 statComFloating[tid]++; 1414 1415 // Function Calls 1416 if (inst->isCall()) 1417 statComFunctionCalls[tid]++; 1418 1419} 1420 1421//////////////////////////////////////// 1422// // 1423// SMT COMMIT POLICY MAINTAINED HERE // 1424// // 1425//////////////////////////////////////// 1426template <class Impl> 1427ThreadID 1428DefaultCommit<Impl>::getCommittingThread() 1429{ 1430 if (numThreads > 1) { 1431 switch (commitPolicy) { 1432 1433 case Aggressive: 1434 //If Policy is Aggressive, commit will call 1435 //this function multiple times per 1436 //cycle 1437 return oldestReady(); 1438 1439 case RoundRobin: 1440 return roundRobin(); 1441 1442 case OldestReady: 1443 return oldestReady(); 1444 1445 default: 1446 return InvalidThreadID; 1447 } 1448 } else { 1449 assert(!activeThreads->empty()); 1450 ThreadID tid = activeThreads->front(); 1451 1452 if (commitStatus[tid] == Running || 1453 commitStatus[tid] == Idle || 1454 commitStatus[tid] == FetchTrapPending) { 1455 return tid; 1456 } else { 1457 return InvalidThreadID; 1458 } 1459 } 1460} 1461 1462template<class Impl> 1463ThreadID 1464DefaultCommit<Impl>::roundRobin() 1465{ 1466 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1467 list<ThreadID>::iterator end = priority_list.end(); 1468 1469 while (pri_iter != end) { 1470 ThreadID tid = *pri_iter; 1471 1472 if (commitStatus[tid] == Running || 1473 commitStatus[tid] == Idle || 1474 commitStatus[tid] == FetchTrapPending) { 1475 1476 if (rob->isHeadReady(tid)) { 1477 priority_list.erase(pri_iter); 1478 priority_list.push_back(tid); 1479 1480 return tid; 1481 } 1482 } 1483 1484 pri_iter++; 1485 } 1486 1487 return InvalidThreadID; 1488} 1489 1490template<class Impl> 1491ThreadID 1492DefaultCommit<Impl>::oldestReady() 1493{ 1494 unsigned oldest = 0; 1495 bool first = true; 1496 1497 list<ThreadID>::iterator threads = activeThreads->begin(); 1498 list<ThreadID>::iterator end = activeThreads->end(); 1499 1500 while (threads != end) { 1501 ThreadID tid = *threads++; 1502 1503 if (!rob->isEmpty(tid) && 1504 (commitStatus[tid] == Running || 1505 commitStatus[tid] == Idle || 1506 commitStatus[tid] == FetchTrapPending)) { 1507 1508 if (rob->isHeadReady(tid)) { 1509 1510 DynInstPtr head_inst = rob->readHeadInst(tid); 1511 1512 if (first) { 1513 oldest = tid; 1514 first = false; 1515 } else if (head_inst->seqNum < oldest) { 1516 oldest = tid; 1517 } 1518 } 1519 } 1520 } 1521 1522 if (!first) { 1523 return oldest; 1524 } else { 1525 return InvalidThreadID; 1526 } 1527} 1528