commit_impl.hh revision 8822:e7ae13867098 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/o3/commit.hh"
53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64#include "sim/full_system.hh"
65
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#endif
69
70using namespace std;
71
72template <class Impl>
73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
74                                          ThreadID _tid)
75    : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
76{
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83    // This will get reset by commit if it was switched out at the
84    // time of this event processing.
85    commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92    return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97    : cpu(_cpu),
98      squashCounter(0),
99      iewToCommitDelay(params->iewToCommitDelay),
100      commitToIEWDelay(params->commitToIEWDelay),
101      renameToROBDelay(params->renameToROBDelay),
102      fetchToCommitDelay(params->commitToFetchDelay),
103      renameWidth(params->renameWidth),
104      commitWidth(params->commitWidth),
105      numThreads(params->numThreads),
106      drainPending(false),
107      switchedOut(false),
108      trapLatency(params->trapLatency)
109{
110    _status = Active;
111    _nextStatus = Inactive;
112    std::string policy = params->smtCommitPolicy;
113
114    //Convert string to lowercase
115    std::transform(policy.begin(), policy.end(), policy.begin(),
116                   (int(*)(int)) tolower);
117
118    //Assign commit policy
119    if (policy == "aggressive"){
120        commitPolicy = Aggressive;
121
122        DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
123    } else if (policy == "roundrobin"){
124        commitPolicy = RoundRobin;
125
126        //Set-Up Priority List
127        for (ThreadID tid = 0; tid < numThreads; tid++) {
128            priority_list.push_back(tid);
129        }
130
131        DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
132    } else if (policy == "oldestready"){
133        commitPolicy = OldestReady;
134
135        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
136    } else {
137        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
138               "RoundRobin,OldestReady}");
139    }
140
141    for (ThreadID tid = 0; tid < numThreads; tid++) {
142        commitStatus[tid] = Idle;
143        changedROBNumEntries[tid] = false;
144        checkEmptyROB[tid] = false;
145        trapInFlight[tid] = false;
146        committedStores[tid] = false;
147        trapSquash[tid] = false;
148        tcSquash[tid] = false;
149        pc[tid].set(0);
150        lastCommitedSeqNum[tid] = 0;
151    }
152    interrupt = NoFault;
153}
154
155template <class Impl>
156std::string
157DefaultCommit<Impl>::name() const
158{
159    return cpu->name() + ".commit";
160}
161
162template <class Impl>
163void
164DefaultCommit<Impl>::regStats()
165{
166    using namespace Stats;
167    commitCommittedInsts
168        .name(name() + ".commitCommittedInsts")
169        .desc("The number of committed instructions")
170        .prereq(commitCommittedInsts);
171    commitSquashedInsts
172        .name(name() + ".commitSquashedInsts")
173        .desc("The number of squashed insts skipped by commit")
174        .prereq(commitSquashedInsts);
175    commitSquashEvents
176        .name(name() + ".commitSquashEvents")
177        .desc("The number of times commit is told to squash")
178        .prereq(commitSquashEvents);
179    commitNonSpecStalls
180        .name(name() + ".commitNonSpecStalls")
181        .desc("The number of times commit has been forced to stall to "
182              "communicate backwards")
183        .prereq(commitNonSpecStalls);
184    branchMispredicts
185        .name(name() + ".branchMispredicts")
186        .desc("The number of times a branch was mispredicted")
187        .prereq(branchMispredicts);
188    numCommittedDist
189        .init(0,commitWidth,1)
190        .name(name() + ".committed_per_cycle")
191        .desc("Number of insts commited each cycle")
192        .flags(Stats::pdf)
193        ;
194
195    statComInst
196        .init(cpu->numThreads)
197        .name(name() + ".count")
198        .desc("Number of instructions committed")
199        .flags(total)
200        ;
201
202    statComSwp
203        .init(cpu->numThreads)
204        .name(name() + ".swp_count")
205        .desc("Number of s/w prefetches committed")
206        .flags(total)
207        ;
208
209    statComRefs
210        .init(cpu->numThreads)
211        .name(name() +  ".refs")
212        .desc("Number of memory references committed")
213        .flags(total)
214        ;
215
216    statComLoads
217        .init(cpu->numThreads)
218        .name(name() +  ".loads")
219        .desc("Number of loads committed")
220        .flags(total)
221        ;
222
223    statComMembars
224        .init(cpu->numThreads)
225        .name(name() +  ".membars")
226        .desc("Number of memory barriers committed")
227        .flags(total)
228        ;
229
230    statComBranches
231        .init(cpu->numThreads)
232        .name(name() + ".branches")
233        .desc("Number of branches committed")
234        .flags(total)
235        ;
236
237    statComFloating
238        .init(cpu->numThreads)
239        .name(name() + ".fp_insts")
240        .desc("Number of committed floating point instructions.")
241        .flags(total)
242        ;
243
244    statComInteger
245        .init(cpu->numThreads)
246        .name(name()+".int_insts")
247        .desc("Number of committed integer instructions.")
248        .flags(total)
249        ;
250
251    statComFunctionCalls
252        .init(cpu->numThreads)
253        .name(name()+".function_calls")
254        .desc("Number of function calls committed.")
255        .flags(total)
256        ;
257
258    commitEligible
259        .init(cpu->numThreads)
260        .name(name() + ".bw_limited")
261        .desc("number of insts not committed due to BW limits")
262        .flags(total)
263        ;
264
265    commitEligibleSamples
266        .name(name() + ".bw_lim_events")
267        .desc("number cycles where commit BW limit reached")
268        ;
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
274{
275    thread = threads;
276}
277
278template <class Impl>
279void
280DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
281{
282    timeBuffer = tb_ptr;
283
284    // Setup wire to send information back to IEW.
285    toIEW = timeBuffer->getWire(0);
286
287    // Setup wire to read data from IEW (for the ROB).
288    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
289}
290
291template <class Impl>
292void
293DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
294{
295    fetchQueue = fq_ptr;
296
297    // Setup wire to get instructions from rename (for the ROB).
298    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
299}
300
301template <class Impl>
302void
303DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
304{
305    renameQueue = rq_ptr;
306
307    // Setup wire to get instructions from rename (for the ROB).
308    fromRename = renameQueue->getWire(-renameToROBDelay);
309}
310
311template <class Impl>
312void
313DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
314{
315    iewQueue = iq_ptr;
316
317    // Setup wire to get instructions from IEW.
318    fromIEW = iewQueue->getWire(-iewToCommitDelay);
319}
320
321template <class Impl>
322void
323DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
324{
325    iewStage = iew_stage;
326}
327
328template<class Impl>
329void
330DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
331{
332    activeThreads = at_ptr;
333}
334
335template <class Impl>
336void
337DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
338{
339    for (ThreadID tid = 0; tid < numThreads; tid++)
340        renameMap[tid] = &rm_ptr[tid];
341}
342
343template <class Impl>
344void
345DefaultCommit<Impl>::setROB(ROB *rob_ptr)
346{
347    rob = rob_ptr;
348}
349
350template <class Impl>
351void
352DefaultCommit<Impl>::initStage()
353{
354    rob->setActiveThreads(activeThreads);
355    rob->resetEntries();
356
357    // Broadcast the number of free entries.
358    for (ThreadID tid = 0; tid < numThreads; tid++) {
359        toIEW->commitInfo[tid].usedROB = true;
360        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
361        toIEW->commitInfo[tid].emptyROB = true;
362    }
363
364    // Commit must broadcast the number of free entries it has at the
365    // start of the simulation, so it starts as active.
366    cpu->activateStage(O3CPU::CommitIdx);
367
368    cpu->activityThisCycle();
369    trapLatency = cpu->ticks(trapLatency);
370}
371
372template <class Impl>
373bool
374DefaultCommit<Impl>::drain()
375{
376    drainPending = true;
377
378    return false;
379}
380
381template <class Impl>
382void
383DefaultCommit<Impl>::switchOut()
384{
385    switchedOut = true;
386    drainPending = false;
387    rob->switchOut();
388}
389
390template <class Impl>
391void
392DefaultCommit<Impl>::resume()
393{
394    drainPending = false;
395}
396
397template <class Impl>
398void
399DefaultCommit<Impl>::takeOverFrom()
400{
401    switchedOut = false;
402    _status = Active;
403    _nextStatus = Inactive;
404    for (ThreadID tid = 0; tid < numThreads; tid++) {
405        commitStatus[tid] = Idle;
406        changedROBNumEntries[tid] = false;
407        trapSquash[tid] = false;
408        tcSquash[tid] = false;
409    }
410    squashCounter = 0;
411    rob->takeOverFrom();
412}
413
414template <class Impl>
415void
416DefaultCommit<Impl>::updateStatus()
417{
418    // reset ROB changed variable
419    list<ThreadID>::iterator threads = activeThreads->begin();
420    list<ThreadID>::iterator end = activeThreads->end();
421
422    while (threads != end) {
423        ThreadID tid = *threads++;
424
425        changedROBNumEntries[tid] = false;
426
427        // Also check if any of the threads has a trap pending
428        if (commitStatus[tid] == TrapPending ||
429            commitStatus[tid] == FetchTrapPending) {
430            _nextStatus = Active;
431        }
432    }
433
434    if (_nextStatus == Inactive && _status == Active) {
435        DPRINTF(Activity, "Deactivating stage.\n");
436        cpu->deactivateStage(O3CPU::CommitIdx);
437    } else if (_nextStatus == Active && _status == Inactive) {
438        DPRINTF(Activity, "Activating stage.\n");
439        cpu->activateStage(O3CPU::CommitIdx);
440    }
441
442    _status = _nextStatus;
443}
444
445template <class Impl>
446void
447DefaultCommit<Impl>::setNextStatus()
448{
449    int squashes = 0;
450
451    list<ThreadID>::iterator threads = activeThreads->begin();
452    list<ThreadID>::iterator end = activeThreads->end();
453
454    while (threads != end) {
455        ThreadID tid = *threads++;
456
457        if (commitStatus[tid] == ROBSquashing) {
458            squashes++;
459        }
460    }
461
462    squashCounter = squashes;
463
464    // If commit is currently squashing, then it will have activity for the
465    // next cycle. Set its next status as active.
466    if (squashCounter) {
467        _nextStatus = Active;
468    }
469}
470
471template <class Impl>
472bool
473DefaultCommit<Impl>::changedROBEntries()
474{
475    list<ThreadID>::iterator threads = activeThreads->begin();
476    list<ThreadID>::iterator end = activeThreads->end();
477
478    while (threads != end) {
479        ThreadID tid = *threads++;
480
481        if (changedROBNumEntries[tid]) {
482            return true;
483        }
484    }
485
486    return false;
487}
488
489template <class Impl>
490size_t
491DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
492{
493    return rob->numFreeEntries(tid);
494}
495
496template <class Impl>
497void
498DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
499{
500    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
501
502    TrapEvent *trap = new TrapEvent(this, tid);
503
504    cpu->schedule(trap, curTick() + trapLatency);
505    trapInFlight[tid] = true;
506    thread[tid]->trapPending = true;
507}
508
509template <class Impl>
510void
511DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
512{
513    assert(!trapInFlight[tid]);
514    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
515
516    tcSquash[tid] = true;
517}
518
519template <class Impl>
520void
521DefaultCommit<Impl>::squashAll(ThreadID tid)
522{
523    // If we want to include the squashing instruction in the squash,
524    // then use one older sequence number.
525    // Hopefully this doesn't mess things up.  Basically I want to squash
526    // all instructions of this thread.
527    InstSeqNum squashed_inst = rob->isEmpty() ?
528        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
529
530    // All younger instructions will be squashed. Set the sequence
531    // number as the youngest instruction in the ROB (0 in this case.
532    // Hopefully nothing breaks.)
533    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
534
535    rob->squash(squashed_inst, tid);
536    changedROBNumEntries[tid] = true;
537
538    // Send back the sequence number of the squashed instruction.
539    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
540
541    // Send back the squash signal to tell stages that they should
542    // squash.
543    toIEW->commitInfo[tid].squash = true;
544
545    // Send back the rob squashing signal so other stages know that
546    // the ROB is in the process of squashing.
547    toIEW->commitInfo[tid].robSquashing = true;
548
549    toIEW->commitInfo[tid].mispredictInst = NULL;
550    toIEW->commitInfo[tid].squashInst = NULL;
551
552    toIEW->commitInfo[tid].pc = pc[tid];
553}
554
555template <class Impl>
556void
557DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
558{
559    squashAll(tid);
560
561    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
562
563    thread[tid]->trapPending = false;
564    thread[tid]->inSyscall = false;
565    trapInFlight[tid] = false;
566
567    trapSquash[tid] = false;
568
569    commitStatus[tid] = ROBSquashing;
570    cpu->activityThisCycle();
571}
572
573template <class Impl>
574void
575DefaultCommit<Impl>::squashFromTC(ThreadID tid)
576{
577    squashAll(tid);
578
579    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
580
581    thread[tid]->inSyscall = false;
582    assert(!thread[tid]->trapPending);
583
584    commitStatus[tid] = ROBSquashing;
585    cpu->activityThisCycle();
586
587    tcSquash[tid] = false;
588}
589
590template <class Impl>
591void
592DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
593        uint64_t squash_after_seq_num)
594{
595    youngestSeqNum[tid] = squash_after_seq_num;
596
597    rob->squash(squash_after_seq_num, tid);
598    changedROBNumEntries[tid] = true;
599
600    // Send back the sequence number of the squashed instruction.
601    toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
602
603    toIEW->commitInfo[tid].squashInst = head_inst;
604    // Send back the squash signal to tell stages that they should squash.
605    toIEW->commitInfo[tid].squash = true;
606
607    // Send back the rob squashing signal so other stages know that
608    // the ROB is in the process of squashing.
609    toIEW->commitInfo[tid].robSquashing = true;
610
611    toIEW->commitInfo[tid].mispredictInst = NULL;
612
613    toIEW->commitInfo[tid].pc = pc[tid];
614    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
615            tid, squash_after_seq_num);
616    commitStatus[tid] = ROBSquashing;
617}
618
619template <class Impl>
620void
621DefaultCommit<Impl>::tick()
622{
623    wroteToTimeBuffer = false;
624    _nextStatus = Inactive;
625
626    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
627        cpu->signalDrained();
628        drainPending = false;
629        return;
630    }
631
632    if (activeThreads->empty())
633        return;
634
635    list<ThreadID>::iterator threads = activeThreads->begin();
636    list<ThreadID>::iterator end = activeThreads->end();
637
638    // Check if any of the threads are done squashing.  Change the
639    // status if they are done.
640    while (threads != end) {
641        ThreadID tid = *threads++;
642
643        // Clear the bit saying if the thread has committed stores
644        // this cycle.
645        committedStores[tid] = false;
646
647        if (commitStatus[tid] == ROBSquashing) {
648
649            if (rob->isDoneSquashing(tid)) {
650                commitStatus[tid] = Running;
651            } else {
652                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
653                        " insts this cycle.\n", tid);
654                rob->doSquash(tid);
655                toIEW->commitInfo[tid].robSquashing = true;
656                wroteToTimeBuffer = true;
657            }
658        }
659    }
660
661    commit();
662
663    markCompletedInsts();
664
665    threads = activeThreads->begin();
666
667    while (threads != end) {
668        ThreadID tid = *threads++;
669
670        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
671            // The ROB has more instructions it can commit. Its next status
672            // will be active.
673            _nextStatus = Active;
674
675            DynInstPtr inst = rob->readHeadInst(tid);
676
677            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
678                    " ROB and ready to commit\n",
679                    tid, inst->seqNum, inst->pcState());
680
681        } else if (!rob->isEmpty(tid)) {
682            DynInstPtr inst = rob->readHeadInst(tid);
683
684            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
685                    "%s is head of ROB and not ready\n",
686                    tid, inst->seqNum, inst->pcState());
687        }
688
689        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
690                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
691    }
692
693
694    if (wroteToTimeBuffer) {
695        DPRINTF(Activity, "Activity This Cycle.\n");
696        cpu->activityThisCycle();
697    }
698
699    updateStatus();
700}
701
702template <class Impl>
703void
704DefaultCommit<Impl>::handleInterrupt()
705{
706    // Verify that we still have an interrupt to handle
707    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
708        DPRINTF(Commit, "Pending interrupt is cleared by master before "
709                "it got handled. Restart fetching from the orig path.\n");
710        toIEW->commitInfo[0].clearInterrupt = true;
711        interrupt = NoFault;
712        return;
713    }
714
715    // Wait until all in flight instructions are finished before enterring
716    // the interrupt.
717    if (cpu->instList.empty()) {
718        // Squash or record that I need to squash this cycle if
719        // an interrupt needed to be handled.
720        DPRINTF(Commit, "Interrupt detected.\n");
721
722        // Clear the interrupt now that it's going to be handled
723        toIEW->commitInfo[0].clearInterrupt = true;
724
725        assert(!thread[0]->inSyscall);
726        thread[0]->inSyscall = true;
727
728#if USE_CHECKER
729        if (cpu->checker) {
730            cpu->checker->handlePendingInt();
731        }
732#endif
733
734        // CPU will handle interrupt.
735        cpu->processInterrupts(interrupt);
736
737        thread[0]->inSyscall = false;
738
739        commitStatus[0] = TrapPending;
740
741        // Generate trap squash event.
742        generateTrapEvent(0);
743
744        interrupt = NoFault;
745    } else {
746        DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
747    }
748}
749
750template <class Impl>
751void
752DefaultCommit<Impl>::propagateInterrupt()
753{
754    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
755            tcSquash[0])
756        return;
757
758    // Process interrupts if interrupts are enabled, not in PAL
759    // mode, and no other traps or external squashes are currently
760    // pending.
761    // @todo: Allow other threads to handle interrupts.
762
763    // Get any interrupt that happened
764    interrupt = cpu->getInterrupts();
765
766    // Tell fetch that there is an interrupt pending.  This
767    // will make fetch wait until it sees a non PAL-mode PC,
768    // at which point it stops fetching instructions.
769    if (interrupt != NoFault)
770        toIEW->commitInfo[0].interruptPending = true;
771}
772
773template <class Impl>
774void
775DefaultCommit<Impl>::commit()
776{
777    if (FullSystem) {
778        // Check for any interrupt that we've already squashed for and
779        // start processing it.
780        if (interrupt != NoFault)
781            handleInterrupt();
782
783        // Check if we have a interrupt and get read to handle it
784        if (cpu->checkInterrupts(cpu->tcBase(0)))
785            propagateInterrupt();
786    }
787
788    ////////////////////////////////////
789    // Check for any possible squashes, handle them first
790    ////////////////////////////////////
791    list<ThreadID>::iterator threads = activeThreads->begin();
792    list<ThreadID>::iterator end = activeThreads->end();
793
794    while (threads != end) {
795        ThreadID tid = *threads++;
796
797        // Not sure which one takes priority.  I think if we have
798        // both, that's a bad sign.
799        if (trapSquash[tid] == true) {
800            assert(!tcSquash[tid]);
801            squashFromTrap(tid);
802        } else if (tcSquash[tid] == true) {
803            assert(commitStatus[tid] != TrapPending);
804            squashFromTC(tid);
805        }
806
807        // Squashed sequence number must be older than youngest valid
808        // instruction in the ROB. This prevents squashes from younger
809        // instructions overriding squashes from older instructions.
810        if (fromIEW->squash[tid] &&
811            commitStatus[tid] != TrapPending &&
812            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
813
814            if (fromIEW->mispredictInst[tid]) {
815                DPRINTF(Commit,
816                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
817                    tid,
818                    fromIEW->mispredictInst[tid]->instAddr(),
819                    fromIEW->squashedSeqNum[tid]);
820            } else {
821                DPRINTF(Commit,
822                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
823                    tid, fromIEW->squashedSeqNum[tid]);
824            }
825
826            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
827                    tid,
828                    fromIEW->pc[tid].nextInstAddr());
829
830            commitStatus[tid] = ROBSquashing;
831
832            // If we want to include the squashing instruction in the squash,
833            // then use one older sequence number.
834            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
835
836            if (fromIEW->includeSquashInst[tid] == true) {
837                squashed_inst--;
838            }
839
840            // All younger instructions will be squashed. Set the sequence
841            // number as the youngest instruction in the ROB.
842            youngestSeqNum[tid] = squashed_inst;
843
844            rob->squash(squashed_inst, tid);
845            changedROBNumEntries[tid] = true;
846
847            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
848
849            toIEW->commitInfo[tid].squash = true;
850
851            // Send back the rob squashing signal so other stages know that
852            // the ROB is in the process of squashing.
853            toIEW->commitInfo[tid].robSquashing = true;
854
855            toIEW->commitInfo[tid].mispredictInst =
856                fromIEW->mispredictInst[tid];
857            toIEW->commitInfo[tid].branchTaken =
858                fromIEW->branchTaken[tid];
859            toIEW->commitInfo[tid].squashInst =
860                                    rob->findInst(tid, squashed_inst);
861
862            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
863
864            if (toIEW->commitInfo[tid].mispredictInst) {
865                ++branchMispredicts;
866            }
867        }
868
869    }
870
871    setNextStatus();
872
873    if (squashCounter != numThreads) {
874        // If we're not currently squashing, then get instructions.
875        getInsts();
876
877        // Try to commit any instructions.
878        commitInsts();
879    }
880
881    //Check for any activity
882    threads = activeThreads->begin();
883
884    while (threads != end) {
885        ThreadID tid = *threads++;
886
887        if (changedROBNumEntries[tid]) {
888            toIEW->commitInfo[tid].usedROB = true;
889            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
890
891            wroteToTimeBuffer = true;
892            changedROBNumEntries[tid] = false;
893            if (rob->isEmpty(tid))
894                checkEmptyROB[tid] = true;
895        }
896
897        // ROB is only considered "empty" for previous stages if: a)
898        // ROB is empty, b) there are no outstanding stores, c) IEW
899        // stage has received any information regarding stores that
900        // committed.
901        // c) is checked by making sure to not consider the ROB empty
902        // on the same cycle as when stores have been committed.
903        // @todo: Make this handle multi-cycle communication between
904        // commit and IEW.
905        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
906            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
907            checkEmptyROB[tid] = false;
908            toIEW->commitInfo[tid].usedROB = true;
909            toIEW->commitInfo[tid].emptyROB = true;
910            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
911            wroteToTimeBuffer = true;
912        }
913
914    }
915}
916
917template <class Impl>
918void
919DefaultCommit<Impl>::commitInsts()
920{
921    ////////////////////////////////////
922    // Handle commit
923    // Note that commit will be handled prior to putting new
924    // instructions in the ROB so that the ROB only tries to commit
925    // instructions it has in this current cycle, and not instructions
926    // it is writing in during this cycle.  Can't commit and squash
927    // things at the same time...
928    ////////////////////////////////////
929
930    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
931
932    unsigned num_committed = 0;
933
934    DynInstPtr head_inst;
935
936    // Commit as many instructions as possible until the commit bandwidth
937    // limit is reached, or it becomes impossible to commit any more.
938    while (num_committed < commitWidth) {
939        int commit_thread = getCommittingThread();
940
941        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
942            break;
943
944        head_inst = rob->readHeadInst(commit_thread);
945
946        ThreadID tid = head_inst->threadNumber;
947
948        assert(tid == commit_thread);
949
950        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
951                head_inst->seqNum, tid);
952
953        // If the head instruction is squashed, it is ready to retire
954        // (be removed from the ROB) at any time.
955        if (head_inst->isSquashed()) {
956
957            DPRINTF(Commit, "Retiring squashed instruction from "
958                    "ROB.\n");
959
960            rob->retireHead(commit_thread);
961
962            ++commitSquashedInsts;
963
964            // Record that the number of ROB entries has changed.
965            changedROBNumEntries[tid] = true;
966        } else {
967            pc[tid] = head_inst->pcState();
968
969            // Increment the total number of non-speculative instructions
970            // executed.
971            // Hack for now: it really shouldn't happen until after the
972            // commit is deemed to be successful, but this count is needed
973            // for syscalls.
974            thread[tid]->funcExeInst++;
975
976            // Try to commit the head instruction.
977            bool commit_success = commitHead(head_inst, num_committed);
978
979            if (commit_success) {
980                ++num_committed;
981
982                changedROBNumEntries[tid] = true;
983
984                // Set the doneSeqNum to the youngest committed instruction.
985                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
986
987                ++commitCommittedInsts;
988
989                // To match the old model, don't count nops and instruction
990                // prefetches towards the total commit count.
991                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
992                    cpu->instDone(tid);
993                }
994
995                // Updates misc. registers.
996                head_inst->updateMiscRegs();
997
998                cpu->traceFunctions(pc[tid].instAddr());
999
1000                TheISA::advancePC(pc[tid], head_inst->staticInst);
1001
1002                // Keep track of the last sequence number commited
1003                lastCommitedSeqNum[tid] = head_inst->seqNum;
1004
1005                // If this is an instruction that doesn't play nicely with
1006                // others squash everything and restart fetch
1007                if (head_inst->isSquashAfter())
1008                    squashAfter(tid, head_inst, head_inst->seqNum);
1009
1010                int count = 0;
1011                Addr oldpc;
1012                // Debug statement.  Checks to make sure we're not
1013                // currently updating state while handling PC events.
1014                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1015                do {
1016                    oldpc = pc[tid].instAddr();
1017                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
1018                    count++;
1019                } while (oldpc != pc[tid].instAddr());
1020                if (count > 1) {
1021                    DPRINTF(Commit,
1022                            "PC skip function event, stopping commit\n");
1023                    break;
1024                }
1025            } else {
1026                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1027                        "[tid:%i] [sn:%i].\n",
1028                        head_inst->pcState(), tid ,head_inst->seqNum);
1029                break;
1030            }
1031        }
1032    }
1033
1034    DPRINTF(CommitRate, "%i\n", num_committed);
1035    numCommittedDist.sample(num_committed);
1036
1037    if (num_committed == commitWidth) {
1038        commitEligibleSamples++;
1039    }
1040}
1041
1042template <class Impl>
1043bool
1044DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1045{
1046    assert(head_inst);
1047
1048    ThreadID tid = head_inst->threadNumber;
1049
1050    // If the instruction is not executed yet, then it will need extra
1051    // handling.  Signal backwards that it should be executed.
1052    if (!head_inst->isExecuted()) {
1053        // Keep this number correct.  We have not yet actually executed
1054        // and committed this instruction.
1055        thread[tid]->funcExeInst--;
1056
1057        if (head_inst->isNonSpeculative() ||
1058            head_inst->isStoreConditional() ||
1059            head_inst->isMemBarrier() ||
1060            head_inst->isWriteBarrier()) {
1061
1062            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1063                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1064                    head_inst->seqNum, head_inst->pcState());
1065
1066            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1067                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1068                return false;
1069            }
1070
1071            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1072
1073            // Change the instruction so it won't try to commit again until
1074            // it is executed.
1075            head_inst->clearCanCommit();
1076
1077            ++commitNonSpecStalls;
1078
1079            return false;
1080        } else if (head_inst->isLoad()) {
1081            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1082                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1083                return false;
1084            }
1085
1086            assert(head_inst->uncacheable());
1087            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1088                    head_inst->seqNum, head_inst->pcState());
1089
1090            // Send back the non-speculative instruction's sequence
1091            // number.  Tell the lsq to re-execute the load.
1092            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1093            toIEW->commitInfo[tid].uncached = true;
1094            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1095
1096            head_inst->clearCanCommit();
1097
1098            return false;
1099        } else {
1100            panic("Trying to commit un-executed instruction "
1101                  "of unknown type!\n");
1102        }
1103    }
1104
1105    if (head_inst->isThreadSync()) {
1106        // Not handled for now.
1107        panic("Thread sync instructions are not handled yet.\n");
1108    }
1109
1110    // Check if the instruction caused a fault.  If so, trap.
1111    Fault inst_fault = head_inst->getFault();
1112
1113    // Stores mark themselves as completed.
1114    if (!head_inst->isStore() && inst_fault == NoFault) {
1115        head_inst->setCompleted();
1116    }
1117
1118#if USE_CHECKER
1119    // Use checker prior to updating anything due to traps or PC
1120    // based events.
1121    if (cpu->checker) {
1122        cpu->checker->verify(head_inst);
1123    }
1124#endif
1125
1126    if (inst_fault != NoFault) {
1127        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1128                head_inst->seqNum, head_inst->pcState());
1129
1130        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1131            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1132            return false;
1133        }
1134
1135        head_inst->setCompleted();
1136
1137#if USE_CHECKER
1138        if (cpu->checker) {
1139            // Need to check the instruction before its fault is processed
1140            cpu->checker->verify(head_inst);
1141        }
1142#endif
1143
1144        assert(!thread[tid]->inSyscall);
1145
1146        // Mark that we're in state update mode so that the trap's
1147        // execution doesn't generate extra squashes.
1148        thread[tid]->inSyscall = true;
1149
1150        // Execute the trap.  Although it's slightly unrealistic in
1151        // terms of timing (as it doesn't wait for the full timing of
1152        // the trap event to complete before updating state), it's
1153        // needed to update the state as soon as possible.  This
1154        // prevents external agents from changing any specific state
1155        // that the trap need.
1156        cpu->trap(inst_fault, tid, head_inst->staticInst);
1157
1158        // Exit state update mode to avoid accidental updating.
1159        thread[tid]->inSyscall = false;
1160
1161        commitStatus[tid] = TrapPending;
1162
1163        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1164            head_inst->seqNum);
1165        if (head_inst->traceData) {
1166            if (DTRACE(ExecFaulting)) {
1167                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1168                head_inst->traceData->setCPSeq(thread[tid]->numInst);
1169                head_inst->traceData->dump();
1170            }
1171            delete head_inst->traceData;
1172            head_inst->traceData = NULL;
1173        }
1174
1175        // Generate trap squash event.
1176        generateTrapEvent(tid);
1177        return false;
1178    }
1179
1180    updateComInstStats(head_inst);
1181
1182    if (FullSystem) {
1183        if (thread[tid]->profile) {
1184            thread[tid]->profilePC = head_inst->instAddr();
1185            ProfileNode *node = thread[tid]->profile->consume(
1186                    thread[tid]->getTC(), head_inst->staticInst);
1187
1188            if (node)
1189                thread[tid]->profileNode = node;
1190        }
1191        if (CPA::available()) {
1192            if (head_inst->isControl()) {
1193                ThreadContext *tc = thread[tid]->getTC();
1194                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1195            }
1196        }
1197    }
1198    DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1199            head_inst->seqNum, head_inst->pcState());
1200    if (head_inst->traceData) {
1201        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1202        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1203        head_inst->traceData->dump();
1204        delete head_inst->traceData;
1205        head_inst->traceData = NULL;
1206    }
1207
1208    // Update the commit rename map
1209    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1210        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1211                                 head_inst->renamedDestRegIdx(i));
1212    }
1213
1214    // Finally clear the head ROB entry.
1215    rob->retireHead(tid);
1216
1217#if TRACING_ON
1218    // Print info needed by the pipeline activity viewer.
1219    DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1220             head_inst->fetchTick,
1221             head_inst->instAddr(),
1222             head_inst->microPC(),
1223             head_inst->seqNum,
1224             head_inst->staticInst->disassemble(head_inst->instAddr()));
1225    DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1226    DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1227    DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1228    DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1229    DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1230    DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1231#endif
1232
1233    // If this was a store, record it for this cycle.
1234    if (head_inst->isStore())
1235        committedStores[tid] = true;
1236
1237    // Return true to indicate that we have committed an instruction.
1238    return true;
1239}
1240
1241template <class Impl>
1242void
1243DefaultCommit<Impl>::getInsts()
1244{
1245    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1246
1247    // Read any renamed instructions and place them into the ROB.
1248    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1249
1250    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1251        DynInstPtr inst;
1252
1253        inst = fromRename->insts[inst_num];
1254        ThreadID tid = inst->threadNumber;
1255
1256        if (!inst->isSquashed() &&
1257            commitStatus[tid] != ROBSquashing &&
1258            commitStatus[tid] != TrapPending) {
1259            changedROBNumEntries[tid] = true;
1260
1261            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1262                    inst->pcState(), inst->seqNum, tid);
1263
1264            rob->insertInst(inst);
1265
1266            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1267
1268            youngestSeqNum[tid] = inst->seqNum;
1269        } else {
1270            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1271                    "squashed, skipping.\n",
1272                    inst->pcState(), inst->seqNum, tid);
1273        }
1274    }
1275}
1276
1277template <class Impl>
1278void
1279DefaultCommit<Impl>::skidInsert()
1280{
1281    DPRINTF(Commit, "Attempting to any instructions from rename into "
1282            "skidBuffer.\n");
1283
1284    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1285        DynInstPtr inst = fromRename->insts[inst_num];
1286
1287        if (!inst->isSquashed()) {
1288            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1289                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
1290                    inst->threadNumber);
1291            skidBuffer.push(inst);
1292        } else {
1293            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1294                    "squashed, skipping.\n",
1295                    inst->pcState(), inst->seqNum, inst->threadNumber);
1296        }
1297    }
1298}
1299
1300template <class Impl>
1301void
1302DefaultCommit<Impl>::markCompletedInsts()
1303{
1304    // Grab completed insts out of the IEW instruction queue, and mark
1305    // instructions completed within the ROB.
1306    for (int inst_num = 0;
1307         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1308         ++inst_num)
1309    {
1310        if (!fromIEW->insts[inst_num]->isSquashed()) {
1311            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1312                    "within ROB.\n",
1313                    fromIEW->insts[inst_num]->threadNumber,
1314                    fromIEW->insts[inst_num]->pcState(),
1315                    fromIEW->insts[inst_num]->seqNum);
1316
1317            // Mark the instruction as ready to commit.
1318            fromIEW->insts[inst_num]->setCanCommit();
1319        }
1320    }
1321}
1322
1323template <class Impl>
1324bool
1325DefaultCommit<Impl>::robDoneSquashing()
1326{
1327    list<ThreadID>::iterator threads = activeThreads->begin();
1328    list<ThreadID>::iterator end = activeThreads->end();
1329
1330    while (threads != end) {
1331        ThreadID tid = *threads++;
1332
1333        if (!rob->isDoneSquashing(tid))
1334            return false;
1335    }
1336
1337    return true;
1338}
1339
1340template <class Impl>
1341void
1342DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1343{
1344    ThreadID tid = inst->threadNumber;
1345
1346    //
1347    //  Pick off the software prefetches
1348    //
1349#ifdef TARGET_ALPHA
1350    if (inst->isDataPrefetch()) {
1351        statComSwp[tid]++;
1352    } else {
1353        statComInst[tid]++;
1354    }
1355#else
1356    statComInst[tid]++;
1357#endif
1358
1359    //
1360    //  Control Instructions
1361    //
1362    if (inst->isControl())
1363        statComBranches[tid]++;
1364
1365    //
1366    //  Memory references
1367    //
1368    if (inst->isMemRef()) {
1369        statComRefs[tid]++;
1370
1371        if (inst->isLoad()) {
1372            statComLoads[tid]++;
1373        }
1374    }
1375
1376    if (inst->isMemBarrier()) {
1377        statComMembars[tid]++;
1378    }
1379
1380    // Integer Instruction
1381    if (inst->isInteger())
1382        statComInteger[tid]++;
1383
1384    // Floating Point Instruction
1385    if (inst->isFloating())
1386        statComFloating[tid]++;
1387
1388    // Function Calls
1389    if (inst->isCall())
1390        statComFunctionCalls[tid]++;
1391
1392}
1393
1394////////////////////////////////////////
1395//                                    //
1396//  SMT COMMIT POLICY MAINTAINED HERE //
1397//                                    //
1398////////////////////////////////////////
1399template <class Impl>
1400ThreadID
1401DefaultCommit<Impl>::getCommittingThread()
1402{
1403    if (numThreads > 1) {
1404        switch (commitPolicy) {
1405
1406          case Aggressive:
1407            //If Policy is Aggressive, commit will call
1408            //this function multiple times per
1409            //cycle
1410            return oldestReady();
1411
1412          case RoundRobin:
1413            return roundRobin();
1414
1415          case OldestReady:
1416            return oldestReady();
1417
1418          default:
1419            return InvalidThreadID;
1420        }
1421    } else {
1422        assert(!activeThreads->empty());
1423        ThreadID tid = activeThreads->front();
1424
1425        if (commitStatus[tid] == Running ||
1426            commitStatus[tid] == Idle ||
1427            commitStatus[tid] == FetchTrapPending) {
1428            return tid;
1429        } else {
1430            return InvalidThreadID;
1431        }
1432    }
1433}
1434
1435template<class Impl>
1436ThreadID
1437DefaultCommit<Impl>::roundRobin()
1438{
1439    list<ThreadID>::iterator pri_iter = priority_list.begin();
1440    list<ThreadID>::iterator end      = priority_list.end();
1441
1442    while (pri_iter != end) {
1443        ThreadID tid = *pri_iter;
1444
1445        if (commitStatus[tid] == Running ||
1446            commitStatus[tid] == Idle ||
1447            commitStatus[tid] == FetchTrapPending) {
1448
1449            if (rob->isHeadReady(tid)) {
1450                priority_list.erase(pri_iter);
1451                priority_list.push_back(tid);
1452
1453                return tid;
1454            }
1455        }
1456
1457        pri_iter++;
1458    }
1459
1460    return InvalidThreadID;
1461}
1462
1463template<class Impl>
1464ThreadID
1465DefaultCommit<Impl>::oldestReady()
1466{
1467    unsigned oldest = 0;
1468    bool first = true;
1469
1470    list<ThreadID>::iterator threads = activeThreads->begin();
1471    list<ThreadID>::iterator end = activeThreads->end();
1472
1473    while (threads != end) {
1474        ThreadID tid = *threads++;
1475
1476        if (!rob->isEmpty(tid) &&
1477            (commitStatus[tid] == Running ||
1478             commitStatus[tid] == Idle ||
1479             commitStatus[tid] == FetchTrapPending)) {
1480
1481            if (rob->isHeadReady(tid)) {
1482
1483                DynInstPtr head_inst = rob->readHeadInst(tid);
1484
1485                if (first) {
1486                    oldest = tid;
1487                    first = false;
1488                } else if (head_inst->seqNum < oldest) {
1489                    oldest = tid;
1490                }
1491            }
1492        }
1493    }
1494
1495    if (!first) {
1496        return oldest;
1497    } else {
1498        return InvalidThreadID;
1499    }
1500}
1501