commit_impl.hh revision 8793:5f25086326ac
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "config/the_isa.hh" 51#include "config/use_checker.hh" 52#include "cpu/o3/commit.hh" 53#include "cpu/o3/thread_state.hh" 54#include "cpu/exetrace.hh" 55#include "cpu/timebuf.hh" 56#include "debug/Activity.hh" 57#include "debug/Commit.hh" 58#include "debug/CommitRate.hh" 59#include "debug/ExecFaulting.hh" 60#include "debug/O3PipeView.hh" 61#include "params/DerivO3CPU.hh" 62#include "sim/faults.hh" 63#include "sim/full_system.hh" 64 65#if USE_CHECKER 66#include "cpu/checker/cpu.hh" 67#endif 68 69using namespace std; 70 71template <class Impl> 72DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 73 ThreadID _tid) 74 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 75{ 76} 77 78template <class Impl> 79void 80DefaultCommit<Impl>::TrapEvent::process() 81{ 82 // This will get reset by commit if it was switched out at the 83 // time of this event processing. 84 commit->trapSquash[tid] = true; 85} 86 87template <class Impl> 88const char * 89DefaultCommit<Impl>::TrapEvent::description() const 90{ 91 return "Trap"; 92} 93 94template <class Impl> 95DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 96 : cpu(_cpu), 97 squashCounter(0), 98 iewToCommitDelay(params->iewToCommitDelay), 99 commitToIEWDelay(params->commitToIEWDelay), 100 renameToROBDelay(params->renameToROBDelay), 101 fetchToCommitDelay(params->commitToFetchDelay), 102 renameWidth(params->renameWidth), 103 commitWidth(params->commitWidth), 104 numThreads(params->numThreads), 105 drainPending(false), 106 switchedOut(false), 107 trapLatency(params->trapLatency) 108{ 109 _status = Active; 110 _nextStatus = Inactive; 111 std::string policy = params->smtCommitPolicy; 112 113 //Convert string to lowercase 114 std::transform(policy.begin(), policy.end(), policy.begin(), 115 (int(*)(int)) tolower); 116 117 //Assign commit policy 118 if (policy == "aggressive"){ 119 commitPolicy = Aggressive; 120 121 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 122 } else if (policy == "roundrobin"){ 123 commitPolicy = RoundRobin; 124 125 //Set-Up Priority List 126 for (ThreadID tid = 0; tid < numThreads; tid++) { 127 priority_list.push_back(tid); 128 } 129 130 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 131 } else if (policy == "oldestready"){ 132 commitPolicy = OldestReady; 133 134 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 135 } else { 136 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 137 "RoundRobin,OldestReady}"); 138 } 139 140 for (ThreadID tid = 0; tid < numThreads; tid++) { 141 commitStatus[tid] = Idle; 142 changedROBNumEntries[tid] = false; 143 checkEmptyROB[tid] = false; 144 trapInFlight[tid] = false; 145 committedStores[tid] = false; 146 trapSquash[tid] = false; 147 tcSquash[tid] = false; 148 pc[tid].set(0); 149 lastCommitedSeqNum[tid] = 0; 150 } 151 interrupt = NoFault; 152} 153 154template <class Impl> 155std::string 156DefaultCommit<Impl>::name() const 157{ 158 return cpu->name() + ".commit"; 159} 160 161template <class Impl> 162void 163DefaultCommit<Impl>::regStats() 164{ 165 using namespace Stats; 166 commitCommittedInsts 167 .name(name() + ".commitCommittedInsts") 168 .desc("The number of committed instructions") 169 .prereq(commitCommittedInsts); 170 commitSquashedInsts 171 .name(name() + ".commitSquashedInsts") 172 .desc("The number of squashed insts skipped by commit") 173 .prereq(commitSquashedInsts); 174 commitSquashEvents 175 .name(name() + ".commitSquashEvents") 176 .desc("The number of times commit is told to squash") 177 .prereq(commitSquashEvents); 178 commitNonSpecStalls 179 .name(name() + ".commitNonSpecStalls") 180 .desc("The number of times commit has been forced to stall to " 181 "communicate backwards") 182 .prereq(commitNonSpecStalls); 183 branchMispredicts 184 .name(name() + ".branchMispredicts") 185 .desc("The number of times a branch was mispredicted") 186 .prereq(branchMispredicts); 187 numCommittedDist 188 .init(0,commitWidth,1) 189 .name(name() + ".committed_per_cycle") 190 .desc("Number of insts commited each cycle") 191 .flags(Stats::pdf) 192 ; 193 194 statComInst 195 .init(cpu->numThreads) 196 .name(name() + ".count") 197 .desc("Number of instructions committed") 198 .flags(total) 199 ; 200 201 statComSwp 202 .init(cpu->numThreads) 203 .name(name() + ".swp_count") 204 .desc("Number of s/w prefetches committed") 205 .flags(total) 206 ; 207 208 statComRefs 209 .init(cpu->numThreads) 210 .name(name() + ".refs") 211 .desc("Number of memory references committed") 212 .flags(total) 213 ; 214 215 statComLoads 216 .init(cpu->numThreads) 217 .name(name() + ".loads") 218 .desc("Number of loads committed") 219 .flags(total) 220 ; 221 222 statComMembars 223 .init(cpu->numThreads) 224 .name(name() + ".membars") 225 .desc("Number of memory barriers committed") 226 .flags(total) 227 ; 228 229 statComBranches 230 .init(cpu->numThreads) 231 .name(name() + ".branches") 232 .desc("Number of branches committed") 233 .flags(total) 234 ; 235 236 statComFloating 237 .init(cpu->numThreads) 238 .name(name() + ".fp_insts") 239 .desc("Number of committed floating point instructions.") 240 .flags(total) 241 ; 242 243 statComInteger 244 .init(cpu->numThreads) 245 .name(name()+".int_insts") 246 .desc("Number of committed integer instructions.") 247 .flags(total) 248 ; 249 250 statComFunctionCalls 251 .init(cpu->numThreads) 252 .name(name()+".function_calls") 253 .desc("Number of function calls committed.") 254 .flags(total) 255 ; 256 257 commitEligible 258 .init(cpu->numThreads) 259 .name(name() + ".bw_limited") 260 .desc("number of insts not committed due to BW limits") 261 .flags(total) 262 ; 263 264 commitEligibleSamples 265 .name(name() + ".bw_lim_events") 266 .desc("number cycles where commit BW limit reached") 267 ; 268} 269 270template <class Impl> 271void 272DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 273{ 274 thread = threads; 275} 276 277template <class Impl> 278void 279DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 280{ 281 timeBuffer = tb_ptr; 282 283 // Setup wire to send information back to IEW. 284 toIEW = timeBuffer->getWire(0); 285 286 // Setup wire to read data from IEW (for the ROB). 287 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 288} 289 290template <class Impl> 291void 292DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 293{ 294 fetchQueue = fq_ptr; 295 296 // Setup wire to get instructions from rename (for the ROB). 297 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 298} 299 300template <class Impl> 301void 302DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 303{ 304 renameQueue = rq_ptr; 305 306 // Setup wire to get instructions from rename (for the ROB). 307 fromRename = renameQueue->getWire(-renameToROBDelay); 308} 309 310template <class Impl> 311void 312DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 313{ 314 iewQueue = iq_ptr; 315 316 // Setup wire to get instructions from IEW. 317 fromIEW = iewQueue->getWire(-iewToCommitDelay); 318} 319 320template <class Impl> 321void 322DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 323{ 324 iewStage = iew_stage; 325} 326 327template<class Impl> 328void 329DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 330{ 331 activeThreads = at_ptr; 332} 333 334template <class Impl> 335void 336DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 337{ 338 for (ThreadID tid = 0; tid < numThreads; tid++) 339 renameMap[tid] = &rm_ptr[tid]; 340} 341 342template <class Impl> 343void 344DefaultCommit<Impl>::setROB(ROB *rob_ptr) 345{ 346 rob = rob_ptr; 347} 348 349template <class Impl> 350void 351DefaultCommit<Impl>::initStage() 352{ 353 rob->setActiveThreads(activeThreads); 354 rob->resetEntries(); 355 356 // Broadcast the number of free entries. 357 for (ThreadID tid = 0; tid < numThreads; tid++) { 358 toIEW->commitInfo[tid].usedROB = true; 359 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 360 toIEW->commitInfo[tid].emptyROB = true; 361 } 362 363 // Commit must broadcast the number of free entries it has at the 364 // start of the simulation, so it starts as active. 365 cpu->activateStage(O3CPU::CommitIdx); 366 367 cpu->activityThisCycle(); 368 trapLatency = cpu->ticks(trapLatency); 369} 370 371template <class Impl> 372bool 373DefaultCommit<Impl>::drain() 374{ 375 drainPending = true; 376 377 return false; 378} 379 380template <class Impl> 381void 382DefaultCommit<Impl>::switchOut() 383{ 384 switchedOut = true; 385 drainPending = false; 386 rob->switchOut(); 387} 388 389template <class Impl> 390void 391DefaultCommit<Impl>::resume() 392{ 393 drainPending = false; 394} 395 396template <class Impl> 397void 398DefaultCommit<Impl>::takeOverFrom() 399{ 400 switchedOut = false; 401 _status = Active; 402 _nextStatus = Inactive; 403 for (ThreadID tid = 0; tid < numThreads; tid++) { 404 commitStatus[tid] = Idle; 405 changedROBNumEntries[tid] = false; 406 trapSquash[tid] = false; 407 tcSquash[tid] = false; 408 } 409 squashCounter = 0; 410 rob->takeOverFrom(); 411} 412 413template <class Impl> 414void 415DefaultCommit<Impl>::updateStatus() 416{ 417 // reset ROB changed variable 418 list<ThreadID>::iterator threads = activeThreads->begin(); 419 list<ThreadID>::iterator end = activeThreads->end(); 420 421 while (threads != end) { 422 ThreadID tid = *threads++; 423 424 changedROBNumEntries[tid] = false; 425 426 // Also check if any of the threads has a trap pending 427 if (commitStatus[tid] == TrapPending || 428 commitStatus[tid] == FetchTrapPending) { 429 _nextStatus = Active; 430 } 431 } 432 433 if (_nextStatus == Inactive && _status == Active) { 434 DPRINTF(Activity, "Deactivating stage.\n"); 435 cpu->deactivateStage(O3CPU::CommitIdx); 436 } else if (_nextStatus == Active && _status == Inactive) { 437 DPRINTF(Activity, "Activating stage.\n"); 438 cpu->activateStage(O3CPU::CommitIdx); 439 } 440 441 _status = _nextStatus; 442} 443 444template <class Impl> 445void 446DefaultCommit<Impl>::setNextStatus() 447{ 448 int squashes = 0; 449 450 list<ThreadID>::iterator threads = activeThreads->begin(); 451 list<ThreadID>::iterator end = activeThreads->end(); 452 453 while (threads != end) { 454 ThreadID tid = *threads++; 455 456 if (commitStatus[tid] == ROBSquashing) { 457 squashes++; 458 } 459 } 460 461 squashCounter = squashes; 462 463 // If commit is currently squashing, then it will have activity for the 464 // next cycle. Set its next status as active. 465 if (squashCounter) { 466 _nextStatus = Active; 467 } 468} 469 470template <class Impl> 471bool 472DefaultCommit<Impl>::changedROBEntries() 473{ 474 list<ThreadID>::iterator threads = activeThreads->begin(); 475 list<ThreadID>::iterator end = activeThreads->end(); 476 477 while (threads != end) { 478 ThreadID tid = *threads++; 479 480 if (changedROBNumEntries[tid]) { 481 return true; 482 } 483 } 484 485 return false; 486} 487 488template <class Impl> 489size_t 490DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 491{ 492 return rob->numFreeEntries(tid); 493} 494 495template <class Impl> 496void 497DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 498{ 499 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 500 501 TrapEvent *trap = new TrapEvent(this, tid); 502 503 cpu->schedule(trap, curTick() + trapLatency); 504 trapInFlight[tid] = true; 505 thread[tid]->trapPending = true; 506} 507 508template <class Impl> 509void 510DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 511{ 512 assert(!trapInFlight[tid]); 513 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 514 515 tcSquash[tid] = true; 516} 517 518template <class Impl> 519void 520DefaultCommit<Impl>::squashAll(ThreadID tid) 521{ 522 // If we want to include the squashing instruction in the squash, 523 // then use one older sequence number. 524 // Hopefully this doesn't mess things up. Basically I want to squash 525 // all instructions of this thread. 526 InstSeqNum squashed_inst = rob->isEmpty() ? 527 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 528 529 // All younger instructions will be squashed. Set the sequence 530 // number as the youngest instruction in the ROB (0 in this case. 531 // Hopefully nothing breaks.) 532 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 533 534 rob->squash(squashed_inst, tid); 535 changedROBNumEntries[tid] = true; 536 537 // Send back the sequence number of the squashed instruction. 538 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 539 540 // Send back the squash signal to tell stages that they should 541 // squash. 542 toIEW->commitInfo[tid].squash = true; 543 544 // Send back the rob squashing signal so other stages know that 545 // the ROB is in the process of squashing. 546 toIEW->commitInfo[tid].robSquashing = true; 547 548 toIEW->commitInfo[tid].mispredictInst = NULL; 549 toIEW->commitInfo[tid].squashInst = NULL; 550 551 toIEW->commitInfo[tid].pc = pc[tid]; 552} 553 554template <class Impl> 555void 556DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 557{ 558 squashAll(tid); 559 560 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 561 562 thread[tid]->trapPending = false; 563 thread[tid]->inSyscall = false; 564 trapInFlight[tid] = false; 565 566 trapSquash[tid] = false; 567 568 commitStatus[tid] = ROBSquashing; 569 cpu->activityThisCycle(); 570} 571 572template <class Impl> 573void 574DefaultCommit<Impl>::squashFromTC(ThreadID tid) 575{ 576 squashAll(tid); 577 578 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 579 580 thread[tid]->inSyscall = false; 581 assert(!thread[tid]->trapPending); 582 583 commitStatus[tid] = ROBSquashing; 584 cpu->activityThisCycle(); 585 586 tcSquash[tid] = false; 587} 588 589template <class Impl> 590void 591DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst, 592 uint64_t squash_after_seq_num) 593{ 594 youngestSeqNum[tid] = squash_after_seq_num; 595 596 rob->squash(squash_after_seq_num, tid); 597 changedROBNumEntries[tid] = true; 598 599 // Send back the sequence number of the squashed instruction. 600 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 601 602 toIEW->commitInfo[tid].squashInst = head_inst; 603 // Send back the squash signal to tell stages that they should squash. 604 toIEW->commitInfo[tid].squash = true; 605 606 // Send back the rob squashing signal so other stages know that 607 // the ROB is in the process of squashing. 608 toIEW->commitInfo[tid].robSquashing = true; 609 610 toIEW->commitInfo[tid].mispredictInst = NULL; 611 612 toIEW->commitInfo[tid].pc = pc[tid]; 613 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 614 tid, squash_after_seq_num); 615 commitStatus[tid] = ROBSquashing; 616} 617 618template <class Impl> 619void 620DefaultCommit<Impl>::tick() 621{ 622 wroteToTimeBuffer = false; 623 _nextStatus = Inactive; 624 625 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 626 cpu->signalDrained(); 627 drainPending = false; 628 return; 629 } 630 631 if (activeThreads->empty()) 632 return; 633 634 list<ThreadID>::iterator threads = activeThreads->begin(); 635 list<ThreadID>::iterator end = activeThreads->end(); 636 637 // Check if any of the threads are done squashing. Change the 638 // status if they are done. 639 while (threads != end) { 640 ThreadID tid = *threads++; 641 642 // Clear the bit saying if the thread has committed stores 643 // this cycle. 644 committedStores[tid] = false; 645 646 if (commitStatus[tid] == ROBSquashing) { 647 648 if (rob->isDoneSquashing(tid)) { 649 commitStatus[tid] = Running; 650 } else { 651 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 652 " insts this cycle.\n", tid); 653 rob->doSquash(tid); 654 toIEW->commitInfo[tid].robSquashing = true; 655 wroteToTimeBuffer = true; 656 } 657 } 658 } 659 660 commit(); 661 662 markCompletedInsts(); 663 664 threads = activeThreads->begin(); 665 666 while (threads != end) { 667 ThreadID tid = *threads++; 668 669 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 670 // The ROB has more instructions it can commit. Its next status 671 // will be active. 672 _nextStatus = Active; 673 674 DynInstPtr inst = rob->readHeadInst(tid); 675 676 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 677 " ROB and ready to commit\n", 678 tid, inst->seqNum, inst->pcState()); 679 680 } else if (!rob->isEmpty(tid)) { 681 DynInstPtr inst = rob->readHeadInst(tid); 682 683 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 684 "%s is head of ROB and not ready\n", 685 tid, inst->seqNum, inst->pcState()); 686 } 687 688 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 689 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 690 } 691 692 693 if (wroteToTimeBuffer) { 694 DPRINTF(Activity, "Activity This Cycle.\n"); 695 cpu->activityThisCycle(); 696 } 697 698 updateStatus(); 699} 700 701template <class Impl> 702void 703DefaultCommit<Impl>::handleInterrupt() 704{ 705 // Verify that we still have an interrupt to handle 706 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 707 DPRINTF(Commit, "Pending interrupt is cleared by master before " 708 "it got handled. Restart fetching from the orig path.\n"); 709 toIEW->commitInfo[0].clearInterrupt = true; 710 interrupt = NoFault; 711 return; 712 } 713 714 // Wait until all in flight instructions are finished before enterring 715 // the interrupt. 716 if (cpu->instList.empty()) { 717 // Squash or record that I need to squash this cycle if 718 // an interrupt needed to be handled. 719 DPRINTF(Commit, "Interrupt detected.\n"); 720 721 // Clear the interrupt now that it's going to be handled 722 toIEW->commitInfo[0].clearInterrupt = true; 723 724 assert(!thread[0]->inSyscall); 725 thread[0]->inSyscall = true; 726 727 // CPU will handle interrupt. 728 cpu->processInterrupts(interrupt); 729 730 thread[0]->inSyscall = false; 731 732 commitStatus[0] = TrapPending; 733 734 // Generate trap squash event. 735 generateTrapEvent(0); 736 737 interrupt = NoFault; 738 } else { 739 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 740 } 741} 742 743template <class Impl> 744void 745DefaultCommit<Impl>::propagateInterrupt() 746{ 747 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 748 tcSquash[0]) 749 return; 750 751 // Process interrupts if interrupts are enabled, not in PAL 752 // mode, and no other traps or external squashes are currently 753 // pending. 754 // @todo: Allow other threads to handle interrupts. 755 756 // Get any interrupt that happened 757 interrupt = cpu->getInterrupts(); 758 759 // Tell fetch that there is an interrupt pending. This 760 // will make fetch wait until it sees a non PAL-mode PC, 761 // at which point it stops fetching instructions. 762 if (interrupt != NoFault) 763 toIEW->commitInfo[0].interruptPending = true; 764} 765 766template <class Impl> 767void 768DefaultCommit<Impl>::commit() 769{ 770 if (FullSystem) { 771 // Check for any interrupt that we've already squashed for and start 772 // processing it. 773 if (interrupt != NoFault) 774 handleInterrupt(); 775 776 // Check if we have a interrupt and get read to handle it 777 if (cpu->checkInterrupts(cpu->tcBase(0))) 778 propagateInterrupt(); 779 } 780 781 //////////////////////////////////// 782 // Check for any possible squashes, handle them first 783 //////////////////////////////////// 784 list<ThreadID>::iterator threads = activeThreads->begin(); 785 list<ThreadID>::iterator end = activeThreads->end(); 786 787 while (threads != end) { 788 ThreadID tid = *threads++; 789 790 // Not sure which one takes priority. I think if we have 791 // both, that's a bad sign. 792 if (trapSquash[tid] == true) { 793 assert(!tcSquash[tid]); 794 squashFromTrap(tid); 795 } else if (tcSquash[tid] == true) { 796 assert(commitStatus[tid] != TrapPending); 797 squashFromTC(tid); 798 } 799 800 // Squashed sequence number must be older than youngest valid 801 // instruction in the ROB. This prevents squashes from younger 802 // instructions overriding squashes from older instructions. 803 if (fromIEW->squash[tid] && 804 commitStatus[tid] != TrapPending && 805 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 806 807 if (fromIEW->mispredictInst[tid]) { 808 DPRINTF(Commit, 809 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 810 tid, 811 fromIEW->mispredictInst[tid]->instAddr(), 812 fromIEW->squashedSeqNum[tid]); 813 } else { 814 DPRINTF(Commit, 815 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 816 tid, fromIEW->squashedSeqNum[tid]); 817 } 818 819 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 820 tid, 821 fromIEW->pc[tid].nextInstAddr()); 822 823 commitStatus[tid] = ROBSquashing; 824 825 // If we want to include the squashing instruction in the squash, 826 // then use one older sequence number. 827 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 828 829 if (fromIEW->includeSquashInst[tid] == true) { 830 squashed_inst--; 831 } 832 833 // All younger instructions will be squashed. Set the sequence 834 // number as the youngest instruction in the ROB. 835 youngestSeqNum[tid] = squashed_inst; 836 837 rob->squash(squashed_inst, tid); 838 changedROBNumEntries[tid] = true; 839 840 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 841 842 toIEW->commitInfo[tid].squash = true; 843 844 // Send back the rob squashing signal so other stages know that 845 // the ROB is in the process of squashing. 846 toIEW->commitInfo[tid].robSquashing = true; 847 848 toIEW->commitInfo[tid].mispredictInst = 849 fromIEW->mispredictInst[tid]; 850 toIEW->commitInfo[tid].branchTaken = 851 fromIEW->branchTaken[tid]; 852 toIEW->commitInfo[tid].squashInst = NULL; 853 854 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 855 856 if (toIEW->commitInfo[tid].mispredictInst) { 857 ++branchMispredicts; 858 } 859 } 860 861 } 862 863 setNextStatus(); 864 865 if (squashCounter != numThreads) { 866 // If we're not currently squashing, then get instructions. 867 getInsts(); 868 869 // Try to commit any instructions. 870 commitInsts(); 871 } 872 873 //Check for any activity 874 threads = activeThreads->begin(); 875 876 while (threads != end) { 877 ThreadID tid = *threads++; 878 879 if (changedROBNumEntries[tid]) { 880 toIEW->commitInfo[tid].usedROB = true; 881 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 882 883 wroteToTimeBuffer = true; 884 changedROBNumEntries[tid] = false; 885 if (rob->isEmpty(tid)) 886 checkEmptyROB[tid] = true; 887 } 888 889 // ROB is only considered "empty" for previous stages if: a) 890 // ROB is empty, b) there are no outstanding stores, c) IEW 891 // stage has received any information regarding stores that 892 // committed. 893 // c) is checked by making sure to not consider the ROB empty 894 // on the same cycle as when stores have been committed. 895 // @todo: Make this handle multi-cycle communication between 896 // commit and IEW. 897 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 898 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 899 checkEmptyROB[tid] = false; 900 toIEW->commitInfo[tid].usedROB = true; 901 toIEW->commitInfo[tid].emptyROB = true; 902 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 903 wroteToTimeBuffer = true; 904 } 905 906 } 907} 908 909template <class Impl> 910void 911DefaultCommit<Impl>::commitInsts() 912{ 913 //////////////////////////////////// 914 // Handle commit 915 // Note that commit will be handled prior to putting new 916 // instructions in the ROB so that the ROB only tries to commit 917 // instructions it has in this current cycle, and not instructions 918 // it is writing in during this cycle. Can't commit and squash 919 // things at the same time... 920 //////////////////////////////////// 921 922 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 923 924 unsigned num_committed = 0; 925 926 DynInstPtr head_inst; 927 928 // Commit as many instructions as possible until the commit bandwidth 929 // limit is reached, or it becomes impossible to commit any more. 930 while (num_committed < commitWidth) { 931 int commit_thread = getCommittingThread(); 932 933 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 934 break; 935 936 head_inst = rob->readHeadInst(commit_thread); 937 938 ThreadID tid = head_inst->threadNumber; 939 940 assert(tid == commit_thread); 941 942 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 943 head_inst->seqNum, tid); 944 945 // If the head instruction is squashed, it is ready to retire 946 // (be removed from the ROB) at any time. 947 if (head_inst->isSquashed()) { 948 949 DPRINTF(Commit, "Retiring squashed instruction from " 950 "ROB.\n"); 951 952 rob->retireHead(commit_thread); 953 954 ++commitSquashedInsts; 955 956 // Record that the number of ROB entries has changed. 957 changedROBNumEntries[tid] = true; 958 } else { 959 pc[tid] = head_inst->pcState(); 960 961 // Increment the total number of non-speculative instructions 962 // executed. 963 // Hack for now: it really shouldn't happen until after the 964 // commit is deemed to be successful, but this count is needed 965 // for syscalls. 966 thread[tid]->funcExeInst++; 967 968 // Try to commit the head instruction. 969 bool commit_success = commitHead(head_inst, num_committed); 970 971 if (commit_success) { 972 ++num_committed; 973 974 changedROBNumEntries[tid] = true; 975 976 // Set the doneSeqNum to the youngest committed instruction. 977 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 978 979 ++commitCommittedInsts; 980 981 // To match the old model, don't count nops and instruction 982 // prefetches towards the total commit count. 983 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 984 cpu->instDone(tid); 985 } 986 987 // Updates misc. registers. 988 head_inst->updateMiscRegs(); 989 990 TheISA::advancePC(pc[tid], head_inst->staticInst); 991 992 // Keep track of the last sequence number commited 993 lastCommitedSeqNum[tid] = head_inst->seqNum; 994 995 // If this is an instruction that doesn't play nicely with 996 // others squash everything and restart fetch 997 if (head_inst->isSquashAfter()) 998 squashAfter(tid, head_inst, head_inst->seqNum); 999 1000 int count = 0; 1001 Addr oldpc; 1002 // Debug statement. Checks to make sure we're not 1003 // currently updating state while handling PC events. 1004 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 1005 do { 1006 oldpc = pc[tid].instAddr(); 1007 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1008 count++; 1009 } while (oldpc != pc[tid].instAddr()); 1010 if (count > 1) { 1011 DPRINTF(Commit, 1012 "PC skip function event, stopping commit\n"); 1013 break; 1014 } 1015 } else { 1016 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1017 "[tid:%i] [sn:%i].\n", 1018 head_inst->pcState(), tid ,head_inst->seqNum); 1019 break; 1020 } 1021 } 1022 } 1023 1024 DPRINTF(CommitRate, "%i\n", num_committed); 1025 numCommittedDist.sample(num_committed); 1026 1027 if (num_committed == commitWidth) { 1028 commitEligibleSamples++; 1029 } 1030} 1031 1032template <class Impl> 1033bool 1034DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1035{ 1036 assert(head_inst); 1037 1038 ThreadID tid = head_inst->threadNumber; 1039 1040 // If the instruction is not executed yet, then it will need extra 1041 // handling. Signal backwards that it should be executed. 1042 if (!head_inst->isExecuted()) { 1043 // Keep this number correct. We have not yet actually executed 1044 // and committed this instruction. 1045 thread[tid]->funcExeInst--; 1046 1047 if (head_inst->isNonSpeculative() || 1048 head_inst->isStoreConditional() || 1049 head_inst->isMemBarrier() || 1050 head_inst->isWriteBarrier()) { 1051 1052 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1053 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1054 head_inst->seqNum, head_inst->pcState()); 1055 1056 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1057 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1058 return false; 1059 } 1060 1061 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1062 1063 // Change the instruction so it won't try to commit again until 1064 // it is executed. 1065 head_inst->clearCanCommit(); 1066 1067 ++commitNonSpecStalls; 1068 1069 return false; 1070 } else if (head_inst->isLoad()) { 1071 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1072 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1073 return false; 1074 } 1075 1076 assert(head_inst->uncacheable()); 1077 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1078 head_inst->seqNum, head_inst->pcState()); 1079 1080 // Send back the non-speculative instruction's sequence 1081 // number. Tell the lsq to re-execute the load. 1082 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1083 toIEW->commitInfo[tid].uncached = true; 1084 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1085 1086 head_inst->clearCanCommit(); 1087 1088 return false; 1089 } else { 1090 panic("Trying to commit un-executed instruction " 1091 "of unknown type!\n"); 1092 } 1093 } 1094 1095 if (head_inst->isThreadSync()) { 1096 // Not handled for now. 1097 panic("Thread sync instructions are not handled yet.\n"); 1098 } 1099 1100 // Check if the instruction caused a fault. If so, trap. 1101 Fault inst_fault = head_inst->getFault(); 1102 1103 // Stores mark themselves as completed. 1104 if (!head_inst->isStore() && inst_fault == NoFault) { 1105 head_inst->setCompleted(); 1106 } 1107 1108#if USE_CHECKER 1109 // Use checker prior to updating anything due to traps or PC 1110 // based events. 1111 if (cpu->checker) { 1112 cpu->checker->verify(head_inst); 1113 } 1114#endif 1115 1116 if (inst_fault != NoFault) { 1117 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1118 head_inst->seqNum, head_inst->pcState()); 1119 1120 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1121 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1122 return false; 1123 } 1124 1125 head_inst->setCompleted(); 1126 1127#if USE_CHECKER 1128 if (cpu->checker && head_inst->isStore()) { 1129 cpu->checker->verify(head_inst); 1130 } 1131#endif 1132 1133 assert(!thread[tid]->inSyscall); 1134 1135 // Mark that we're in state update mode so that the trap's 1136 // execution doesn't generate extra squashes. 1137 thread[tid]->inSyscall = true; 1138 1139 // Execute the trap. Although it's slightly unrealistic in 1140 // terms of timing (as it doesn't wait for the full timing of 1141 // the trap event to complete before updating state), it's 1142 // needed to update the state as soon as possible. This 1143 // prevents external agents from changing any specific state 1144 // that the trap need. 1145 cpu->trap(inst_fault, tid, head_inst->staticInst); 1146 1147 // Exit state update mode to avoid accidental updating. 1148 thread[tid]->inSyscall = false; 1149 1150 commitStatus[tid] = TrapPending; 1151 1152 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1153 head_inst->seqNum); 1154 if (head_inst->traceData) { 1155 if (DTRACE(ExecFaulting)) { 1156 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1157 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1158 head_inst->traceData->dump(); 1159 } 1160 delete head_inst->traceData; 1161 head_inst->traceData = NULL; 1162 } 1163 1164 // Generate trap squash event. 1165 generateTrapEvent(tid); 1166 return false; 1167 } 1168 1169 updateComInstStats(head_inst); 1170 1171 if (FullSystem) { 1172 if (thread[tid]->profile) { 1173 thread[tid]->profilePC = head_inst->instAddr(); 1174 ProfileNode *node = thread[tid]->profile->consume( 1175 thread[tid]->getTC(), head_inst->staticInst); 1176 1177 if (node) 1178 thread[tid]->profileNode = node; 1179 } 1180 if (CPA::available()) { 1181 if (head_inst->isControl()) { 1182 ThreadContext *tc = thread[tid]->getTC(); 1183 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1184 } 1185 } 1186 } 1187 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1188 head_inst->seqNum, head_inst->pcState()); 1189 if (head_inst->traceData) { 1190 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1191 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1192 head_inst->traceData->dump(); 1193 delete head_inst->traceData; 1194 head_inst->traceData = NULL; 1195 } 1196 1197 // Update the commit rename map 1198 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1199 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1200 head_inst->renamedDestRegIdx(i)); 1201 } 1202 1203 // Finally clear the head ROB entry. 1204 rob->retireHead(tid); 1205 1206#if TRACING_ON 1207 // Print info needed by the pipeline activity viewer. 1208 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 1209 head_inst->fetchTick, 1210 head_inst->instAddr(), 1211 head_inst->microPC(), 1212 head_inst->seqNum, 1213 head_inst->staticInst->disassemble(head_inst->instAddr())); 1214 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick); 1215 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick); 1216 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick); 1217 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick); 1218 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick); 1219 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick()); 1220#endif 1221 1222 // If this was a store, record it for this cycle. 1223 if (head_inst->isStore()) 1224 committedStores[tid] = true; 1225 1226 // Return true to indicate that we have committed an instruction. 1227 return true; 1228} 1229 1230template <class Impl> 1231void 1232DefaultCommit<Impl>::getInsts() 1233{ 1234 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1235 1236 // Read any renamed instructions and place them into the ROB. 1237 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1238 1239 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1240 DynInstPtr inst; 1241 1242 inst = fromRename->insts[inst_num]; 1243 ThreadID tid = inst->threadNumber; 1244 1245 if (!inst->isSquashed() && 1246 commitStatus[tid] != ROBSquashing && 1247 commitStatus[tid] != TrapPending) { 1248 changedROBNumEntries[tid] = true; 1249 1250 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1251 inst->pcState(), inst->seqNum, tid); 1252 1253 rob->insertInst(inst); 1254 1255 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1256 1257 youngestSeqNum[tid] = inst->seqNum; 1258 } else { 1259 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1260 "squashed, skipping.\n", 1261 inst->pcState(), inst->seqNum, tid); 1262 } 1263 } 1264} 1265 1266template <class Impl> 1267void 1268DefaultCommit<Impl>::skidInsert() 1269{ 1270 DPRINTF(Commit, "Attempting to any instructions from rename into " 1271 "skidBuffer.\n"); 1272 1273 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1274 DynInstPtr inst = fromRename->insts[inst_num]; 1275 1276 if (!inst->isSquashed()) { 1277 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1278 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1279 inst->threadNumber); 1280 skidBuffer.push(inst); 1281 } else { 1282 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1283 "squashed, skipping.\n", 1284 inst->pcState(), inst->seqNum, inst->threadNumber); 1285 } 1286 } 1287} 1288 1289template <class Impl> 1290void 1291DefaultCommit<Impl>::markCompletedInsts() 1292{ 1293 // Grab completed insts out of the IEW instruction queue, and mark 1294 // instructions completed within the ROB. 1295 for (int inst_num = 0; 1296 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1297 ++inst_num) 1298 { 1299 if (!fromIEW->insts[inst_num]->isSquashed()) { 1300 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1301 "within ROB.\n", 1302 fromIEW->insts[inst_num]->threadNumber, 1303 fromIEW->insts[inst_num]->pcState(), 1304 fromIEW->insts[inst_num]->seqNum); 1305 1306 // Mark the instruction as ready to commit. 1307 fromIEW->insts[inst_num]->setCanCommit(); 1308 } 1309 } 1310} 1311 1312template <class Impl> 1313bool 1314DefaultCommit<Impl>::robDoneSquashing() 1315{ 1316 list<ThreadID>::iterator threads = activeThreads->begin(); 1317 list<ThreadID>::iterator end = activeThreads->end(); 1318 1319 while (threads != end) { 1320 ThreadID tid = *threads++; 1321 1322 if (!rob->isDoneSquashing(tid)) 1323 return false; 1324 } 1325 1326 return true; 1327} 1328 1329template <class Impl> 1330void 1331DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1332{ 1333 ThreadID tid = inst->threadNumber; 1334 1335 // 1336 // Pick off the software prefetches 1337 // 1338#ifdef TARGET_ALPHA 1339 if (inst->isDataPrefetch()) { 1340 statComSwp[tid]++; 1341 } else { 1342 statComInst[tid]++; 1343 } 1344#else 1345 statComInst[tid]++; 1346#endif 1347 1348 // 1349 // Control Instructions 1350 // 1351 if (inst->isControl()) 1352 statComBranches[tid]++; 1353 1354 // 1355 // Memory references 1356 // 1357 if (inst->isMemRef()) { 1358 statComRefs[tid]++; 1359 1360 if (inst->isLoad()) { 1361 statComLoads[tid]++; 1362 } 1363 } 1364 1365 if (inst->isMemBarrier()) { 1366 statComMembars[tid]++; 1367 } 1368 1369 // Integer Instruction 1370 if (inst->isInteger()) 1371 statComInteger[tid]++; 1372 1373 // Floating Point Instruction 1374 if (inst->isFloating()) 1375 statComFloating[tid]++; 1376 1377 // Function Calls 1378 if (inst->isCall()) 1379 statComFunctionCalls[tid]++; 1380 1381} 1382 1383//////////////////////////////////////// 1384// // 1385// SMT COMMIT POLICY MAINTAINED HERE // 1386// // 1387//////////////////////////////////////// 1388template <class Impl> 1389ThreadID 1390DefaultCommit<Impl>::getCommittingThread() 1391{ 1392 if (numThreads > 1) { 1393 switch (commitPolicy) { 1394 1395 case Aggressive: 1396 //If Policy is Aggressive, commit will call 1397 //this function multiple times per 1398 //cycle 1399 return oldestReady(); 1400 1401 case RoundRobin: 1402 return roundRobin(); 1403 1404 case OldestReady: 1405 return oldestReady(); 1406 1407 default: 1408 return InvalidThreadID; 1409 } 1410 } else { 1411 assert(!activeThreads->empty()); 1412 ThreadID tid = activeThreads->front(); 1413 1414 if (commitStatus[tid] == Running || 1415 commitStatus[tid] == Idle || 1416 commitStatus[tid] == FetchTrapPending) { 1417 return tid; 1418 } else { 1419 return InvalidThreadID; 1420 } 1421 } 1422} 1423 1424template<class Impl> 1425ThreadID 1426DefaultCommit<Impl>::roundRobin() 1427{ 1428 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1429 list<ThreadID>::iterator end = priority_list.end(); 1430 1431 while (pri_iter != end) { 1432 ThreadID tid = *pri_iter; 1433 1434 if (commitStatus[tid] == Running || 1435 commitStatus[tid] == Idle || 1436 commitStatus[tid] == FetchTrapPending) { 1437 1438 if (rob->isHeadReady(tid)) { 1439 priority_list.erase(pri_iter); 1440 priority_list.push_back(tid); 1441 1442 return tid; 1443 } 1444 } 1445 1446 pri_iter++; 1447 } 1448 1449 return InvalidThreadID; 1450} 1451 1452template<class Impl> 1453ThreadID 1454DefaultCommit<Impl>::oldestReady() 1455{ 1456 unsigned oldest = 0; 1457 bool first = true; 1458 1459 list<ThreadID>::iterator threads = activeThreads->begin(); 1460 list<ThreadID>::iterator end = activeThreads->end(); 1461 1462 while (threads != end) { 1463 ThreadID tid = *threads++; 1464 1465 if (!rob->isEmpty(tid) && 1466 (commitStatus[tid] == Running || 1467 commitStatus[tid] == Idle || 1468 commitStatus[tid] == FetchTrapPending)) { 1469 1470 if (rob->isHeadReady(tid)) { 1471 1472 DynInstPtr head_inst = rob->readHeadInst(tid); 1473 1474 if (first) { 1475 oldest = tid; 1476 first = false; 1477 } else if (head_inst->seqNum < oldest) { 1478 oldest = tid; 1479 } 1480 } 1481 } 1482 } 1483 1484 if (!first) { 1485 return oldest; 1486 } else { 1487 return InvalidThreadID; 1488 } 1489} 1490