commit_impl.hh revision 8733:64a7bf8fa56c
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "config/full_system.hh" 51#include "config/the_isa.hh" 52#include "config/use_checker.hh" 53#include "cpu/o3/commit.hh" 54#include "cpu/o3/thread_state.hh" 55#include "cpu/base.hh" 56#include "cpu/exetrace.hh" 57#include "cpu/timebuf.hh" 58#include "debug/Activity.hh" 59#include "debug/Commit.hh" 60#include "debug/CommitRate.hh" 61#include "debug/ExecFaulting.hh" 62#include "debug/O3PipeView.hh" 63#include "params/DerivO3CPU.hh" 64#include "sim/faults.hh" 65 66#if USE_CHECKER 67#include "cpu/checker/cpu.hh" 68#endif 69 70using namespace std; 71 72template <class Impl> 73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 74 ThreadID _tid) 75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 76{ 77} 78 79template <class Impl> 80void 81DefaultCommit<Impl>::TrapEvent::process() 82{ 83 // This will get reset by commit if it was switched out at the 84 // time of this event processing. 85 commit->trapSquash[tid] = true; 86} 87 88template <class Impl> 89const char * 90DefaultCommit<Impl>::TrapEvent::description() const 91{ 92 return "Trap"; 93} 94 95template <class Impl> 96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 97 : cpu(_cpu), 98 squashCounter(0), 99 iewToCommitDelay(params->iewToCommitDelay), 100 commitToIEWDelay(params->commitToIEWDelay), 101 renameToROBDelay(params->renameToROBDelay), 102 fetchToCommitDelay(params->commitToFetchDelay), 103 renameWidth(params->renameWidth), 104 commitWidth(params->commitWidth), 105 numThreads(params->numThreads), 106 drainPending(false), 107 switchedOut(false), 108 trapLatency(params->trapLatency) 109{ 110 _status = Active; 111 _nextStatus = Inactive; 112 std::string policy = params->smtCommitPolicy; 113 114 //Convert string to lowercase 115 std::transform(policy.begin(), policy.end(), policy.begin(), 116 (int(*)(int)) tolower); 117 118 //Assign commit policy 119 if (policy == "aggressive"){ 120 commitPolicy = Aggressive; 121 122 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 123 } else if (policy == "roundrobin"){ 124 commitPolicy = RoundRobin; 125 126 //Set-Up Priority List 127 for (ThreadID tid = 0; tid < numThreads; tid++) { 128 priority_list.push_back(tid); 129 } 130 131 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 132 } else if (policy == "oldestready"){ 133 commitPolicy = OldestReady; 134 135 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 136 } else { 137 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 138 "RoundRobin,OldestReady}"); 139 } 140 141 for (ThreadID tid = 0; tid < numThreads; tid++) { 142 commitStatus[tid] = Idle; 143 changedROBNumEntries[tid] = false; 144 checkEmptyROB[tid] = false; 145 trapInFlight[tid] = false; 146 committedStores[tid] = false; 147 trapSquash[tid] = false; 148 tcSquash[tid] = false; 149 pc[tid].set(0); 150 lastCommitedSeqNum[tid] = 0; 151 } 152#if FULL_SYSTEM 153 interrupt = NoFault; 154#endif 155} 156 157template <class Impl> 158std::string 159DefaultCommit<Impl>::name() const 160{ 161 return cpu->name() + ".commit"; 162} 163 164template <class Impl> 165void 166DefaultCommit<Impl>::regStats() 167{ 168 using namespace Stats; 169 commitCommittedInsts 170 .name(name() + ".commitCommittedInsts") 171 .desc("The number of committed instructions") 172 .prereq(commitCommittedInsts); 173 commitSquashedInsts 174 .name(name() + ".commitSquashedInsts") 175 .desc("The number of squashed insts skipped by commit") 176 .prereq(commitSquashedInsts); 177 commitSquashEvents 178 .name(name() + ".commitSquashEvents") 179 .desc("The number of times commit is told to squash") 180 .prereq(commitSquashEvents); 181 commitNonSpecStalls 182 .name(name() + ".commitNonSpecStalls") 183 .desc("The number of times commit has been forced to stall to " 184 "communicate backwards") 185 .prereq(commitNonSpecStalls); 186 branchMispredicts 187 .name(name() + ".branchMispredicts") 188 .desc("The number of times a branch was mispredicted") 189 .prereq(branchMispredicts); 190 numCommittedDist 191 .init(0,commitWidth,1) 192 .name(name() + ".committed_per_cycle") 193 .desc("Number of insts commited each cycle") 194 .flags(Stats::pdf) 195 ; 196 197 statComInst 198 .init(cpu->numThreads) 199 .name(name() + ".count") 200 .desc("Number of instructions committed") 201 .flags(total) 202 ; 203 204 statComSwp 205 .init(cpu->numThreads) 206 .name(name() + ".swp_count") 207 .desc("Number of s/w prefetches committed") 208 .flags(total) 209 ; 210 211 statComRefs 212 .init(cpu->numThreads) 213 .name(name() + ".refs") 214 .desc("Number of memory references committed") 215 .flags(total) 216 ; 217 218 statComLoads 219 .init(cpu->numThreads) 220 .name(name() + ".loads") 221 .desc("Number of loads committed") 222 .flags(total) 223 ; 224 225 statComMembars 226 .init(cpu->numThreads) 227 .name(name() + ".membars") 228 .desc("Number of memory barriers committed") 229 .flags(total) 230 ; 231 232 statComBranches 233 .init(cpu->numThreads) 234 .name(name() + ".branches") 235 .desc("Number of branches committed") 236 .flags(total) 237 ; 238 239 statComFloating 240 .init(cpu->numThreads) 241 .name(name() + ".fp_insts") 242 .desc("Number of committed floating point instructions.") 243 .flags(total) 244 ; 245 246 statComInteger 247 .init(cpu->numThreads) 248 .name(name()+".int_insts") 249 .desc("Number of committed integer instructions.") 250 .flags(total) 251 ; 252 253 statComFunctionCalls 254 .init(cpu->numThreads) 255 .name(name()+".function_calls") 256 .desc("Number of function calls committed.") 257 .flags(total) 258 ; 259 260 commitEligible 261 .init(cpu->numThreads) 262 .name(name() + ".bw_limited") 263 .desc("number of insts not committed due to BW limits") 264 .flags(total) 265 ; 266 267 commitEligibleSamples 268 .name(name() + ".bw_lim_events") 269 .desc("number cycles where commit BW limit reached") 270 ; 271} 272 273template <class Impl> 274void 275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 276{ 277 thread = threads; 278} 279 280template <class Impl> 281void 282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 283{ 284 timeBuffer = tb_ptr; 285 286 // Setup wire to send information back to IEW. 287 toIEW = timeBuffer->getWire(0); 288 289 // Setup wire to read data from IEW (for the ROB). 290 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 291} 292 293template <class Impl> 294void 295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 296{ 297 fetchQueue = fq_ptr; 298 299 // Setup wire to get instructions from rename (for the ROB). 300 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 301} 302 303template <class Impl> 304void 305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 306{ 307 renameQueue = rq_ptr; 308 309 // Setup wire to get instructions from rename (for the ROB). 310 fromRename = renameQueue->getWire(-renameToROBDelay); 311} 312 313template <class Impl> 314void 315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 316{ 317 iewQueue = iq_ptr; 318 319 // Setup wire to get instructions from IEW. 320 fromIEW = iewQueue->getWire(-iewToCommitDelay); 321} 322 323template <class Impl> 324void 325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 326{ 327 iewStage = iew_stage; 328} 329 330template<class Impl> 331void 332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 333{ 334 activeThreads = at_ptr; 335} 336 337template <class Impl> 338void 339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 340{ 341 for (ThreadID tid = 0; tid < numThreads; tid++) 342 renameMap[tid] = &rm_ptr[tid]; 343} 344 345template <class Impl> 346void 347DefaultCommit<Impl>::setROB(ROB *rob_ptr) 348{ 349 rob = rob_ptr; 350} 351 352template <class Impl> 353void 354DefaultCommit<Impl>::initStage() 355{ 356 rob->setActiveThreads(activeThreads); 357 rob->resetEntries(); 358 359 // Broadcast the number of free entries. 360 for (ThreadID tid = 0; tid < numThreads; tid++) { 361 toIEW->commitInfo[tid].usedROB = true; 362 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 363 toIEW->commitInfo[tid].emptyROB = true; 364 } 365 366 // Commit must broadcast the number of free entries it has at the 367 // start of the simulation, so it starts as active. 368 cpu->activateStage(O3CPU::CommitIdx); 369 370 cpu->activityThisCycle(); 371 trapLatency = cpu->ticks(trapLatency); 372} 373 374template <class Impl> 375bool 376DefaultCommit<Impl>::drain() 377{ 378 drainPending = true; 379 380 return false; 381} 382 383template <class Impl> 384void 385DefaultCommit<Impl>::switchOut() 386{ 387 switchedOut = true; 388 drainPending = false; 389 rob->switchOut(); 390} 391 392template <class Impl> 393void 394DefaultCommit<Impl>::resume() 395{ 396 drainPending = false; 397} 398 399template <class Impl> 400void 401DefaultCommit<Impl>::takeOverFrom() 402{ 403 switchedOut = false; 404 _status = Active; 405 _nextStatus = Inactive; 406 for (ThreadID tid = 0; tid < numThreads; tid++) { 407 commitStatus[tid] = Idle; 408 changedROBNumEntries[tid] = false; 409 trapSquash[tid] = false; 410 tcSquash[tid] = false; 411 } 412 squashCounter = 0; 413 rob->takeOverFrom(); 414} 415 416template <class Impl> 417void 418DefaultCommit<Impl>::updateStatus() 419{ 420 // reset ROB changed variable 421 list<ThreadID>::iterator threads = activeThreads->begin(); 422 list<ThreadID>::iterator end = activeThreads->end(); 423 424 while (threads != end) { 425 ThreadID tid = *threads++; 426 427 changedROBNumEntries[tid] = false; 428 429 // Also check if any of the threads has a trap pending 430 if (commitStatus[tid] == TrapPending || 431 commitStatus[tid] == FetchTrapPending) { 432 _nextStatus = Active; 433 } 434 } 435 436 if (_nextStatus == Inactive && _status == Active) { 437 DPRINTF(Activity, "Deactivating stage.\n"); 438 cpu->deactivateStage(O3CPU::CommitIdx); 439 } else if (_nextStatus == Active && _status == Inactive) { 440 DPRINTF(Activity, "Activating stage.\n"); 441 cpu->activateStage(O3CPU::CommitIdx); 442 } 443 444 _status = _nextStatus; 445} 446 447template <class Impl> 448void 449DefaultCommit<Impl>::setNextStatus() 450{ 451 int squashes = 0; 452 453 list<ThreadID>::iterator threads = activeThreads->begin(); 454 list<ThreadID>::iterator end = activeThreads->end(); 455 456 while (threads != end) { 457 ThreadID tid = *threads++; 458 459 if (commitStatus[tid] == ROBSquashing) { 460 squashes++; 461 } 462 } 463 464 squashCounter = squashes; 465 466 // If commit is currently squashing, then it will have activity for the 467 // next cycle. Set its next status as active. 468 if (squashCounter) { 469 _nextStatus = Active; 470 } 471} 472 473template <class Impl> 474bool 475DefaultCommit<Impl>::changedROBEntries() 476{ 477 list<ThreadID>::iterator threads = activeThreads->begin(); 478 list<ThreadID>::iterator end = activeThreads->end(); 479 480 while (threads != end) { 481 ThreadID tid = *threads++; 482 483 if (changedROBNumEntries[tid]) { 484 return true; 485 } 486 } 487 488 return false; 489} 490 491template <class Impl> 492size_t 493DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 494{ 495 return rob->numFreeEntries(tid); 496} 497 498template <class Impl> 499void 500DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 501{ 502 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 503 504 TrapEvent *trap = new TrapEvent(this, tid); 505 506 cpu->schedule(trap, curTick() + trapLatency); 507 trapInFlight[tid] = true; 508 thread[tid]->trapPending = true; 509} 510 511template <class Impl> 512void 513DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 514{ 515 assert(!trapInFlight[tid]); 516 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 517 518 tcSquash[tid] = true; 519} 520 521template <class Impl> 522void 523DefaultCommit<Impl>::squashAll(ThreadID tid) 524{ 525 // If we want to include the squashing instruction in the squash, 526 // then use one older sequence number. 527 // Hopefully this doesn't mess things up. Basically I want to squash 528 // all instructions of this thread. 529 InstSeqNum squashed_inst = rob->isEmpty() ? 530 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 531 532 // All younger instructions will be squashed. Set the sequence 533 // number as the youngest instruction in the ROB (0 in this case. 534 // Hopefully nothing breaks.) 535 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 536 537 rob->squash(squashed_inst, tid); 538 changedROBNumEntries[tid] = true; 539 540 // Send back the sequence number of the squashed instruction. 541 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 542 543 // Send back the squash signal to tell stages that they should 544 // squash. 545 toIEW->commitInfo[tid].squash = true; 546 547 // Send back the rob squashing signal so other stages know that 548 // the ROB is in the process of squashing. 549 toIEW->commitInfo[tid].robSquashing = true; 550 551 toIEW->commitInfo[tid].mispredictInst = NULL; 552 toIEW->commitInfo[tid].squashInst = NULL; 553 554 toIEW->commitInfo[tid].pc = pc[tid]; 555} 556 557template <class Impl> 558void 559DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 560{ 561 squashAll(tid); 562 563 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 564 565 thread[tid]->trapPending = false; 566 thread[tid]->inSyscall = false; 567 trapInFlight[tid] = false; 568 569 trapSquash[tid] = false; 570 571 commitStatus[tid] = ROBSquashing; 572 cpu->activityThisCycle(); 573} 574 575template <class Impl> 576void 577DefaultCommit<Impl>::squashFromTC(ThreadID tid) 578{ 579 squashAll(tid); 580 581 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 582 583 thread[tid]->inSyscall = false; 584 assert(!thread[tid]->trapPending); 585 586 commitStatus[tid] = ROBSquashing; 587 cpu->activityThisCycle(); 588 589 tcSquash[tid] = false; 590} 591 592template <class Impl> 593void 594DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst, 595 uint64_t squash_after_seq_num) 596{ 597 youngestSeqNum[tid] = squash_after_seq_num; 598 599 rob->squash(squash_after_seq_num, tid); 600 changedROBNumEntries[tid] = true; 601 602 // Send back the sequence number of the squashed instruction. 603 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 604 605 toIEW->commitInfo[tid].squashInst = head_inst; 606 // Send back the squash signal to tell stages that they should squash. 607 toIEW->commitInfo[tid].squash = true; 608 609 // Send back the rob squashing signal so other stages know that 610 // the ROB is in the process of squashing. 611 toIEW->commitInfo[tid].robSquashing = true; 612 613 toIEW->commitInfo[tid].mispredictInst = NULL; 614 615 toIEW->commitInfo[tid].pc = pc[tid]; 616 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 617 tid, squash_after_seq_num); 618 commitStatus[tid] = ROBSquashing; 619} 620 621template <class Impl> 622void 623DefaultCommit<Impl>::tick() 624{ 625 wroteToTimeBuffer = false; 626 _nextStatus = Inactive; 627 628 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 629 cpu->signalDrained(); 630 drainPending = false; 631 return; 632 } 633 634 if (activeThreads->empty()) 635 return; 636 637 list<ThreadID>::iterator threads = activeThreads->begin(); 638 list<ThreadID>::iterator end = activeThreads->end(); 639 640 // Check if any of the threads are done squashing. Change the 641 // status if they are done. 642 while (threads != end) { 643 ThreadID tid = *threads++; 644 645 // Clear the bit saying if the thread has committed stores 646 // this cycle. 647 committedStores[tid] = false; 648 649 if (commitStatus[tid] == ROBSquashing) { 650 651 if (rob->isDoneSquashing(tid)) { 652 commitStatus[tid] = Running; 653 } else { 654 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 655 " insts this cycle.\n", tid); 656 rob->doSquash(tid); 657 toIEW->commitInfo[tid].robSquashing = true; 658 wroteToTimeBuffer = true; 659 } 660 } 661 } 662 663 commit(); 664 665 markCompletedInsts(); 666 667 threads = activeThreads->begin(); 668 669 while (threads != end) { 670 ThreadID tid = *threads++; 671 672 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 673 // The ROB has more instructions it can commit. Its next status 674 // will be active. 675 _nextStatus = Active; 676 677 DynInstPtr inst = rob->readHeadInst(tid); 678 679 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 680 " ROB and ready to commit\n", 681 tid, inst->seqNum, inst->pcState()); 682 683 } else if (!rob->isEmpty(tid)) { 684 DynInstPtr inst = rob->readHeadInst(tid); 685 686 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 687 "%s is head of ROB and not ready\n", 688 tid, inst->seqNum, inst->pcState()); 689 } 690 691 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 692 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 693 } 694 695 696 if (wroteToTimeBuffer) { 697 DPRINTF(Activity, "Activity This Cycle.\n"); 698 cpu->activityThisCycle(); 699 } 700 701 updateStatus(); 702} 703 704#if FULL_SYSTEM 705template <class Impl> 706void 707DefaultCommit<Impl>::handleInterrupt() 708{ 709 // Verify that we still have an interrupt to handle 710 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 711 DPRINTF(Commit, "Pending interrupt is cleared by master before " 712 "it got handled. Restart fetching from the orig path.\n"); 713 toIEW->commitInfo[0].clearInterrupt = true; 714 interrupt = NoFault; 715 return; 716 } 717 718 // Wait until all in flight instructions are finished before enterring 719 // the interrupt. 720 if (cpu->instList.empty()) { 721 // Squash or record that I need to squash this cycle if 722 // an interrupt needed to be handled. 723 DPRINTF(Commit, "Interrupt detected.\n"); 724 725 // Clear the interrupt now that it's going to be handled 726 toIEW->commitInfo[0].clearInterrupt = true; 727 728 assert(!thread[0]->inSyscall); 729 thread[0]->inSyscall = true; 730 731#if USE_CHECKER 732 if (cpu->checker) { 733 cpu->checker->handlePendingInt(); 734 } 735#endif 736 737 // CPU will handle interrupt. 738 cpu->processInterrupts(interrupt); 739 740 thread[0]->inSyscall = false; 741 742 commitStatus[0] = TrapPending; 743 744 // Generate trap squash event. 745 generateTrapEvent(0); 746 747 interrupt = NoFault; 748 } else { 749 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 750 } 751} 752 753template <class Impl> 754void 755DefaultCommit<Impl>::propagateInterrupt() 756{ 757 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 758 tcSquash[0]) 759 return; 760 761 // Process interrupts if interrupts are enabled, not in PAL 762 // mode, and no other traps or external squashes are currently 763 // pending. 764 // @todo: Allow other threads to handle interrupts. 765 766 // Get any interrupt that happened 767 interrupt = cpu->getInterrupts(); 768 769 // Tell fetch that there is an interrupt pending. This 770 // will make fetch wait until it sees a non PAL-mode PC, 771 // at which point it stops fetching instructions. 772 if (interrupt != NoFault) 773 toIEW->commitInfo[0].interruptPending = true; 774} 775 776#endif // FULL_SYSTEM 777 778template <class Impl> 779void 780DefaultCommit<Impl>::commit() 781{ 782 783#if FULL_SYSTEM 784 // Check for any interrupt that we've already squashed for and 785 // start processing it. 786 if (interrupt != NoFault) 787 handleInterrupt(); 788 789 // Check if we have a interrupt and get read to handle it 790 if (cpu->checkInterrupts(cpu->tcBase(0))) 791 propagateInterrupt(); 792#endif // FULL_SYSTEM 793 794 //////////////////////////////////// 795 // Check for any possible squashes, handle them first 796 //////////////////////////////////// 797 list<ThreadID>::iterator threads = activeThreads->begin(); 798 list<ThreadID>::iterator end = activeThreads->end(); 799 800 while (threads != end) { 801 ThreadID tid = *threads++; 802 803 // Not sure which one takes priority. I think if we have 804 // both, that's a bad sign. 805 if (trapSquash[tid] == true) { 806 assert(!tcSquash[tid]); 807 squashFromTrap(tid); 808 } else if (tcSquash[tid] == true) { 809 assert(commitStatus[tid] != TrapPending); 810 squashFromTC(tid); 811 } 812 813 // Squashed sequence number must be older than youngest valid 814 // instruction in the ROB. This prevents squashes from younger 815 // instructions overriding squashes from older instructions. 816 if (fromIEW->squash[tid] && 817 commitStatus[tid] != TrapPending && 818 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 819 820 if (fromIEW->mispredictInst[tid]) { 821 DPRINTF(Commit, 822 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 823 tid, 824 fromIEW->mispredictInst[tid]->instAddr(), 825 fromIEW->squashedSeqNum[tid]); 826 } else { 827 DPRINTF(Commit, 828 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 829 tid, fromIEW->squashedSeqNum[tid]); 830 } 831 832 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 833 tid, 834 fromIEW->pc[tid].nextInstAddr()); 835 836 commitStatus[tid] = ROBSquashing; 837 838 // If we want to include the squashing instruction in the squash, 839 // then use one older sequence number. 840 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 841 842 if (fromIEW->includeSquashInst[tid] == true) { 843 squashed_inst--; 844 } 845 846 // All younger instructions will be squashed. Set the sequence 847 // number as the youngest instruction in the ROB. 848 youngestSeqNum[tid] = squashed_inst; 849 850 rob->squash(squashed_inst, tid); 851 changedROBNumEntries[tid] = true; 852 853 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 854 855 toIEW->commitInfo[tid].squash = true; 856 857 // Send back the rob squashing signal so other stages know that 858 // the ROB is in the process of squashing. 859 toIEW->commitInfo[tid].robSquashing = true; 860 861 toIEW->commitInfo[tid].mispredictInst = 862 fromIEW->mispredictInst[tid]; 863 toIEW->commitInfo[tid].branchTaken = 864 fromIEW->branchTaken[tid]; 865 toIEW->commitInfo[tid].squashInst = NULL; 866 867 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 868 869 if (toIEW->commitInfo[tid].mispredictInst) { 870 ++branchMispredicts; 871 } 872 } 873 874 } 875 876 setNextStatus(); 877 878 if (squashCounter != numThreads) { 879 // If we're not currently squashing, then get instructions. 880 getInsts(); 881 882 // Try to commit any instructions. 883 commitInsts(); 884 } 885 886 //Check for any activity 887 threads = activeThreads->begin(); 888 889 while (threads != end) { 890 ThreadID tid = *threads++; 891 892 if (changedROBNumEntries[tid]) { 893 toIEW->commitInfo[tid].usedROB = true; 894 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 895 896 wroteToTimeBuffer = true; 897 changedROBNumEntries[tid] = false; 898 if (rob->isEmpty(tid)) 899 checkEmptyROB[tid] = true; 900 } 901 902 // ROB is only considered "empty" for previous stages if: a) 903 // ROB is empty, b) there are no outstanding stores, c) IEW 904 // stage has received any information regarding stores that 905 // committed. 906 // c) is checked by making sure to not consider the ROB empty 907 // on the same cycle as when stores have been committed. 908 // @todo: Make this handle multi-cycle communication between 909 // commit and IEW. 910 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 911 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 912 checkEmptyROB[tid] = false; 913 toIEW->commitInfo[tid].usedROB = true; 914 toIEW->commitInfo[tid].emptyROB = true; 915 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 916 wroteToTimeBuffer = true; 917 } 918 919 } 920} 921 922template <class Impl> 923void 924DefaultCommit<Impl>::commitInsts() 925{ 926 //////////////////////////////////// 927 // Handle commit 928 // Note that commit will be handled prior to putting new 929 // instructions in the ROB so that the ROB only tries to commit 930 // instructions it has in this current cycle, and not instructions 931 // it is writing in during this cycle. Can't commit and squash 932 // things at the same time... 933 //////////////////////////////////// 934 935 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 936 937 unsigned num_committed = 0; 938 939 DynInstPtr head_inst; 940 941 // Commit as many instructions as possible until the commit bandwidth 942 // limit is reached, or it becomes impossible to commit any more. 943 while (num_committed < commitWidth) { 944 int commit_thread = getCommittingThread(); 945 946 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 947 break; 948 949 head_inst = rob->readHeadInst(commit_thread); 950 951 ThreadID tid = head_inst->threadNumber; 952 953 assert(tid == commit_thread); 954 955 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 956 head_inst->seqNum, tid); 957 958 // If the head instruction is squashed, it is ready to retire 959 // (be removed from the ROB) at any time. 960 if (head_inst->isSquashed()) { 961 962 DPRINTF(Commit, "Retiring squashed instruction from " 963 "ROB.\n"); 964 965 rob->retireHead(commit_thread); 966 967 ++commitSquashedInsts; 968 969 // Record that the number of ROB entries has changed. 970 changedROBNumEntries[tid] = true; 971 } else { 972 pc[tid] = head_inst->pcState(); 973 974 // Increment the total number of non-speculative instructions 975 // executed. 976 // Hack for now: it really shouldn't happen until after the 977 // commit is deemed to be successful, but this count is needed 978 // for syscalls. 979 thread[tid]->funcExeInst++; 980 981 // Try to commit the head instruction. 982 bool commit_success = commitHead(head_inst, num_committed); 983 984 if (commit_success) { 985 ++num_committed; 986 987 changedROBNumEntries[tid] = true; 988 989 // Set the doneSeqNum to the youngest committed instruction. 990 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 991 992 ++commitCommittedInsts; 993 994 // To match the old model, don't count nops and instruction 995 // prefetches towards the total commit count. 996 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 997 cpu->instDone(tid); 998 } 999 1000 // Updates misc. registers. 1001 head_inst->updateMiscRegs(); 1002 1003 cpu->traceFunctions(pc[tid].instAddr()); 1004 1005 TheISA::advancePC(pc[tid], head_inst->staticInst); 1006 1007 // Keep track of the last sequence number commited 1008 lastCommitedSeqNum[tid] = head_inst->seqNum; 1009 1010 // If this is an instruction that doesn't play nicely with 1011 // others squash everything and restart fetch 1012 if (head_inst->isSquashAfter()) 1013 squashAfter(tid, head_inst, head_inst->seqNum); 1014 1015 int count = 0; 1016 Addr oldpc; 1017 // Debug statement. Checks to make sure we're not 1018 // currently updating state while handling PC events. 1019 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 1020 do { 1021 oldpc = pc[tid].instAddr(); 1022 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1023 count++; 1024 } while (oldpc != pc[tid].instAddr()); 1025 if (count > 1) { 1026 DPRINTF(Commit, 1027 "PC skip function event, stopping commit\n"); 1028 break; 1029 } 1030 } else { 1031 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1032 "[tid:%i] [sn:%i].\n", 1033 head_inst->pcState(), tid ,head_inst->seqNum); 1034 break; 1035 } 1036 } 1037 } 1038 1039 DPRINTF(CommitRate, "%i\n", num_committed); 1040 numCommittedDist.sample(num_committed); 1041 1042 if (num_committed == commitWidth) { 1043 commitEligibleSamples++; 1044 } 1045} 1046 1047template <class Impl> 1048bool 1049DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1050{ 1051 assert(head_inst); 1052 1053 ThreadID tid = head_inst->threadNumber; 1054 1055 // If the instruction is not executed yet, then it will need extra 1056 // handling. Signal backwards that it should be executed. 1057 if (!head_inst->isExecuted()) { 1058 // Keep this number correct. We have not yet actually executed 1059 // and committed this instruction. 1060 thread[tid]->funcExeInst--; 1061 1062 if (head_inst->isNonSpeculative() || 1063 head_inst->isStoreConditional() || 1064 head_inst->isMemBarrier() || 1065 head_inst->isWriteBarrier()) { 1066 1067 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1068 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1069 head_inst->seqNum, head_inst->pcState()); 1070 1071 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1072 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1073 return false; 1074 } 1075 1076 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1077 1078 // Change the instruction so it won't try to commit again until 1079 // it is executed. 1080 head_inst->clearCanCommit(); 1081 1082 ++commitNonSpecStalls; 1083 1084 return false; 1085 } else if (head_inst->isLoad()) { 1086 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1087 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1088 return false; 1089 } 1090 1091 assert(head_inst->uncacheable()); 1092 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1093 head_inst->seqNum, head_inst->pcState()); 1094 1095 // Send back the non-speculative instruction's sequence 1096 // number. Tell the lsq to re-execute the load. 1097 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1098 toIEW->commitInfo[tid].uncached = true; 1099 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1100 1101 head_inst->clearCanCommit(); 1102 1103 return false; 1104 } else { 1105 panic("Trying to commit un-executed instruction " 1106 "of unknown type!\n"); 1107 } 1108 } 1109 1110 if (head_inst->isThreadSync()) { 1111 // Not handled for now. 1112 panic("Thread sync instructions are not handled yet.\n"); 1113 } 1114 1115 // Check if the instruction caused a fault. If so, trap. 1116 Fault inst_fault = head_inst->getFault(); 1117 1118 // Stores mark themselves as completed. 1119 if (!head_inst->isStore() && inst_fault == NoFault) { 1120 head_inst->setCompleted(); 1121 } 1122 1123#if USE_CHECKER 1124 // Use checker prior to updating anything due to traps or PC 1125 // based events. 1126 if (cpu->checker) { 1127 cpu->checker->verify(head_inst); 1128 } 1129#endif 1130 1131 if (inst_fault != NoFault) { 1132 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1133 head_inst->seqNum, head_inst->pcState()); 1134 1135 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1136 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1137 return false; 1138 } 1139 1140 head_inst->setCompleted(); 1141 1142#if USE_CHECKER 1143 if (cpu->checker) { 1144 // Need to check the instruction before its fault is processed 1145 cpu->checker->verify(head_inst); 1146 } 1147#endif 1148 1149 assert(!thread[tid]->inSyscall); 1150 1151 // Mark that we're in state update mode so that the trap's 1152 // execution doesn't generate extra squashes. 1153 thread[tid]->inSyscall = true; 1154 1155 // Execute the trap. Although it's slightly unrealistic in 1156 // terms of timing (as it doesn't wait for the full timing of 1157 // the trap event to complete before updating state), it's 1158 // needed to update the state as soon as possible. This 1159 // prevents external agents from changing any specific state 1160 // that the trap need. 1161 cpu->trap(inst_fault, tid, head_inst->staticInst); 1162 1163 // Exit state update mode to avoid accidental updating. 1164 thread[tid]->inSyscall = false; 1165 1166 commitStatus[tid] = TrapPending; 1167 1168 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1169 head_inst->seqNum); 1170 if (head_inst->traceData) { 1171 if (DTRACE(ExecFaulting)) { 1172 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1173 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1174 head_inst->traceData->dump(); 1175 } 1176 delete head_inst->traceData; 1177 head_inst->traceData = NULL; 1178 } 1179 1180 // Generate trap squash event. 1181 generateTrapEvent(tid); 1182 return false; 1183 } 1184 1185 updateComInstStats(head_inst); 1186 1187#if FULL_SYSTEM 1188 if (thread[tid]->profile) { 1189 thread[tid]->profilePC = head_inst->instAddr(); 1190 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1191 head_inst->staticInst); 1192 1193 if (node) 1194 thread[tid]->profileNode = node; 1195 } 1196 if (CPA::available()) { 1197 if (head_inst->isControl()) { 1198 ThreadContext *tc = thread[tid]->getTC(); 1199 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1200 } 1201 } 1202#endif 1203 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1204 head_inst->seqNum, head_inst->pcState()); 1205 if (head_inst->traceData) { 1206 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1207 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1208 head_inst->traceData->dump(); 1209 delete head_inst->traceData; 1210 head_inst->traceData = NULL; 1211 } 1212 1213 // Update the commit rename map 1214 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1215 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1216 head_inst->renamedDestRegIdx(i)); 1217 } 1218 1219 // Finally clear the head ROB entry. 1220 rob->retireHead(tid); 1221 1222#if TRACING_ON 1223 // Print info needed by the pipeline activity viewer. 1224 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 1225 head_inst->fetchTick, 1226 head_inst->instAddr(), 1227 head_inst->microPC(), 1228 head_inst->seqNum, 1229 head_inst->staticInst->disassemble(head_inst->instAddr())); 1230 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick); 1231 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick); 1232 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick); 1233 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick); 1234 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick); 1235 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick()); 1236#endif 1237 1238 // If this was a store, record it for this cycle. 1239 if (head_inst->isStore()) 1240 committedStores[tid] = true; 1241 1242 // Return true to indicate that we have committed an instruction. 1243 return true; 1244} 1245 1246template <class Impl> 1247void 1248DefaultCommit<Impl>::getInsts() 1249{ 1250 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1251 1252 // Read any renamed instructions and place them into the ROB. 1253 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1254 1255 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1256 DynInstPtr inst; 1257 1258 inst = fromRename->insts[inst_num]; 1259 ThreadID tid = inst->threadNumber; 1260 1261 if (!inst->isSquashed() && 1262 commitStatus[tid] != ROBSquashing && 1263 commitStatus[tid] != TrapPending) { 1264 changedROBNumEntries[tid] = true; 1265 1266 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1267 inst->pcState(), inst->seqNum, tid); 1268 1269 rob->insertInst(inst); 1270 1271 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1272 1273 youngestSeqNum[tid] = inst->seqNum; 1274 } else { 1275 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1276 "squashed, skipping.\n", 1277 inst->pcState(), inst->seqNum, tid); 1278 } 1279 } 1280} 1281 1282template <class Impl> 1283void 1284DefaultCommit<Impl>::skidInsert() 1285{ 1286 DPRINTF(Commit, "Attempting to any instructions from rename into " 1287 "skidBuffer.\n"); 1288 1289 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1290 DynInstPtr inst = fromRename->insts[inst_num]; 1291 1292 if (!inst->isSquashed()) { 1293 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1294 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1295 inst->threadNumber); 1296 skidBuffer.push(inst); 1297 } else { 1298 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1299 "squashed, skipping.\n", 1300 inst->pcState(), inst->seqNum, inst->threadNumber); 1301 } 1302 } 1303} 1304 1305template <class Impl> 1306void 1307DefaultCommit<Impl>::markCompletedInsts() 1308{ 1309 // Grab completed insts out of the IEW instruction queue, and mark 1310 // instructions completed within the ROB. 1311 for (int inst_num = 0; 1312 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1313 ++inst_num) 1314 { 1315 if (!fromIEW->insts[inst_num]->isSquashed()) { 1316 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1317 "within ROB.\n", 1318 fromIEW->insts[inst_num]->threadNumber, 1319 fromIEW->insts[inst_num]->pcState(), 1320 fromIEW->insts[inst_num]->seqNum); 1321 1322 // Mark the instruction as ready to commit. 1323 fromIEW->insts[inst_num]->setCanCommit(); 1324 } 1325 } 1326} 1327 1328template <class Impl> 1329bool 1330DefaultCommit<Impl>::robDoneSquashing() 1331{ 1332 list<ThreadID>::iterator threads = activeThreads->begin(); 1333 list<ThreadID>::iterator end = activeThreads->end(); 1334 1335 while (threads != end) { 1336 ThreadID tid = *threads++; 1337 1338 if (!rob->isDoneSquashing(tid)) 1339 return false; 1340 } 1341 1342 return true; 1343} 1344 1345template <class Impl> 1346void 1347DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1348{ 1349 ThreadID tid = inst->threadNumber; 1350 1351 // 1352 // Pick off the software prefetches 1353 // 1354#ifdef TARGET_ALPHA 1355 if (inst->isDataPrefetch()) { 1356 statComSwp[tid]++; 1357 } else { 1358 statComInst[tid]++; 1359 } 1360#else 1361 statComInst[tid]++; 1362#endif 1363 1364 // 1365 // Control Instructions 1366 // 1367 if (inst->isControl()) 1368 statComBranches[tid]++; 1369 1370 // 1371 // Memory references 1372 // 1373 if (inst->isMemRef()) { 1374 statComRefs[tid]++; 1375 1376 if (inst->isLoad()) { 1377 statComLoads[tid]++; 1378 } 1379 } 1380 1381 if (inst->isMemBarrier()) { 1382 statComMembars[tid]++; 1383 } 1384 1385 // Integer Instruction 1386 if (inst->isInteger()) 1387 statComInteger[tid]++; 1388 1389 // Floating Point Instruction 1390 if (inst->isFloating()) 1391 statComFloating[tid]++; 1392 1393 // Function Calls 1394 if (inst->isCall()) 1395 statComFunctionCalls[tid]++; 1396 1397} 1398 1399//////////////////////////////////////// 1400// // 1401// SMT COMMIT POLICY MAINTAINED HERE // 1402// // 1403//////////////////////////////////////// 1404template <class Impl> 1405ThreadID 1406DefaultCommit<Impl>::getCommittingThread() 1407{ 1408 if (numThreads > 1) { 1409 switch (commitPolicy) { 1410 1411 case Aggressive: 1412 //If Policy is Aggressive, commit will call 1413 //this function multiple times per 1414 //cycle 1415 return oldestReady(); 1416 1417 case RoundRobin: 1418 return roundRobin(); 1419 1420 case OldestReady: 1421 return oldestReady(); 1422 1423 default: 1424 return InvalidThreadID; 1425 } 1426 } else { 1427 assert(!activeThreads->empty()); 1428 ThreadID tid = activeThreads->front(); 1429 1430 if (commitStatus[tid] == Running || 1431 commitStatus[tid] == Idle || 1432 commitStatus[tid] == FetchTrapPending) { 1433 return tid; 1434 } else { 1435 return InvalidThreadID; 1436 } 1437 } 1438} 1439 1440template<class Impl> 1441ThreadID 1442DefaultCommit<Impl>::roundRobin() 1443{ 1444 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1445 list<ThreadID>::iterator end = priority_list.end(); 1446 1447 while (pri_iter != end) { 1448 ThreadID tid = *pri_iter; 1449 1450 if (commitStatus[tid] == Running || 1451 commitStatus[tid] == Idle || 1452 commitStatus[tid] == FetchTrapPending) { 1453 1454 if (rob->isHeadReady(tid)) { 1455 priority_list.erase(pri_iter); 1456 priority_list.push_back(tid); 1457 1458 return tid; 1459 } 1460 } 1461 1462 pri_iter++; 1463 } 1464 1465 return InvalidThreadID; 1466} 1467 1468template<class Impl> 1469ThreadID 1470DefaultCommit<Impl>::oldestReady() 1471{ 1472 unsigned oldest = 0; 1473 bool first = true; 1474 1475 list<ThreadID>::iterator threads = activeThreads->begin(); 1476 list<ThreadID>::iterator end = activeThreads->end(); 1477 1478 while (threads != end) { 1479 ThreadID tid = *threads++; 1480 1481 if (!rob->isEmpty(tid) && 1482 (commitStatus[tid] == Running || 1483 commitStatus[tid] == Idle || 1484 commitStatus[tid] == FetchTrapPending)) { 1485 1486 if (rob->isHeadReady(tid)) { 1487 1488 DynInstPtr head_inst = rob->readHeadInst(tid); 1489 1490 if (first) { 1491 oldest = tid; 1492 first = false; 1493 } else if (head_inst->seqNum < oldest) { 1494 oldest = tid; 1495 } 1496 } 1497 } 1498 } 1499 1500 if (!first) { 1501 return oldest; 1502 } else { 1503 return InvalidThreadID; 1504 } 1505} 1506