commit_impl.hh revision 8662:d4548b381e87 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/base.hh"
56#include "cpu/exetrace.hh"
57#include "cpu/timebuf.hh"
58#include "debug/Activity.hh"
59#include "debug/Commit.hh"
60#include "debug/CommitRate.hh"
61#include "debug/ExecFaulting.hh"
62#include "debug/O3PipeView.hh"
63#include "params/DerivO3CPU.hh"
64#include "sim/faults.hh"
65
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#endif
69
70using namespace std;
71
72template <class Impl>
73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
74                                          ThreadID _tid)
75    : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
76{
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83    // This will get reset by commit if it was switched out at the
84    // time of this event processing.
85    commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92    return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97    : cpu(_cpu),
98      squashCounter(0),
99      iewToCommitDelay(params->iewToCommitDelay),
100      commitToIEWDelay(params->commitToIEWDelay),
101      renameToROBDelay(params->renameToROBDelay),
102      fetchToCommitDelay(params->commitToFetchDelay),
103      renameWidth(params->renameWidth),
104      commitWidth(params->commitWidth),
105      numThreads(params->numThreads),
106      drainPending(false),
107      switchedOut(false),
108      trapLatency(params->trapLatency)
109{
110    _status = Active;
111    _nextStatus = Inactive;
112    std::string policy = params->smtCommitPolicy;
113
114    //Convert string to lowercase
115    std::transform(policy.begin(), policy.end(), policy.begin(),
116                   (int(*)(int)) tolower);
117
118    //Assign commit policy
119    if (policy == "aggressive"){
120        commitPolicy = Aggressive;
121
122        DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
123    } else if (policy == "roundrobin"){
124        commitPolicy = RoundRobin;
125
126        //Set-Up Priority List
127        for (ThreadID tid = 0; tid < numThreads; tid++) {
128            priority_list.push_back(tid);
129        }
130
131        DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
132    } else if (policy == "oldestready"){
133        commitPolicy = OldestReady;
134
135        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
136    } else {
137        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
138               "RoundRobin,OldestReady}");
139    }
140
141    for (ThreadID tid = 0; tid < numThreads; tid++) {
142        commitStatus[tid] = Idle;
143        changedROBNumEntries[tid] = false;
144        checkEmptyROB[tid] = false;
145        trapInFlight[tid] = false;
146        committedStores[tid] = false;
147        trapSquash[tid] = false;
148        tcSquash[tid] = false;
149        pc[tid].set(0);
150        lastCommitedSeqNum[tid] = 0;
151    }
152#if FULL_SYSTEM
153    interrupt = NoFault;
154#endif
155}
156
157template <class Impl>
158std::string
159DefaultCommit<Impl>::name() const
160{
161    return cpu->name() + ".commit";
162}
163
164template <class Impl>
165void
166DefaultCommit<Impl>::regStats()
167{
168    using namespace Stats;
169    commitCommittedInsts
170        .name(name() + ".commitCommittedInsts")
171        .desc("The number of committed instructions")
172        .prereq(commitCommittedInsts);
173    commitSquashedInsts
174        .name(name() + ".commitSquashedInsts")
175        .desc("The number of squashed insts skipped by commit")
176        .prereq(commitSquashedInsts);
177    commitSquashEvents
178        .name(name() + ".commitSquashEvents")
179        .desc("The number of times commit is told to squash")
180        .prereq(commitSquashEvents);
181    commitNonSpecStalls
182        .name(name() + ".commitNonSpecStalls")
183        .desc("The number of times commit has been forced to stall to "
184              "communicate backwards")
185        .prereq(commitNonSpecStalls);
186    branchMispredicts
187        .name(name() + ".branchMispredicts")
188        .desc("The number of times a branch was mispredicted")
189        .prereq(branchMispredicts);
190    numCommittedDist
191        .init(0,commitWidth,1)
192        .name(name() + ".committed_per_cycle")
193        .desc("Number of insts commited each cycle")
194        .flags(Stats::pdf)
195        ;
196
197    statComInst
198        .init(cpu->numThreads)
199        .name(name() + ".count")
200        .desc("Number of instructions committed")
201        .flags(total)
202        ;
203
204    statComSwp
205        .init(cpu->numThreads)
206        .name(name() + ".swp_count")
207        .desc("Number of s/w prefetches committed")
208        .flags(total)
209        ;
210
211    statComRefs
212        .init(cpu->numThreads)
213        .name(name() +  ".refs")
214        .desc("Number of memory references committed")
215        .flags(total)
216        ;
217
218    statComLoads
219        .init(cpu->numThreads)
220        .name(name() +  ".loads")
221        .desc("Number of loads committed")
222        .flags(total)
223        ;
224
225    statComMembars
226        .init(cpu->numThreads)
227        .name(name() +  ".membars")
228        .desc("Number of memory barriers committed")
229        .flags(total)
230        ;
231
232    statComBranches
233        .init(cpu->numThreads)
234        .name(name() + ".branches")
235        .desc("Number of branches committed")
236        .flags(total)
237        ;
238
239    statComFloating
240        .init(cpu->numThreads)
241        .name(name() + ".fp_insts")
242        .desc("Number of committed floating point instructions.")
243        .flags(total)
244        ;
245
246    statComInteger
247        .init(cpu->numThreads)
248        .name(name()+".int_insts")
249        .desc("Number of committed integer instructions.")
250        .flags(total)
251        ;
252
253    statComFunctionCalls
254        .init(cpu->numThreads)
255        .name(name()+".function_calls")
256        .desc("Number of function calls committed.")
257        .flags(total)
258        ;
259
260    commitEligible
261        .init(cpu->numThreads)
262        .name(name() + ".bw_limited")
263        .desc("number of insts not committed due to BW limits")
264        .flags(total)
265        ;
266
267    commitEligibleSamples
268        .name(name() + ".bw_lim_events")
269        .desc("number cycles where commit BW limit reached")
270        ;
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
276{
277    thread = threads;
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
283{
284    timeBuffer = tb_ptr;
285
286    // Setup wire to send information back to IEW.
287    toIEW = timeBuffer->getWire(0);
288
289    // Setup wire to read data from IEW (for the ROB).
290    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
296{
297    fetchQueue = fq_ptr;
298
299    // Setup wire to get instructions from rename (for the ROB).
300    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
306{
307    renameQueue = rq_ptr;
308
309    // Setup wire to get instructions from rename (for the ROB).
310    fromRename = renameQueue->getWire(-renameToROBDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
316{
317    iewQueue = iq_ptr;
318
319    // Setup wire to get instructions from IEW.
320    fromIEW = iewQueue->getWire(-iewToCommitDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
326{
327    iewStage = iew_stage;
328}
329
330template<class Impl>
331void
332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
333{
334    activeThreads = at_ptr;
335}
336
337template <class Impl>
338void
339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
340{
341    for (ThreadID tid = 0; tid < numThreads; tid++)
342        renameMap[tid] = &rm_ptr[tid];
343}
344
345template <class Impl>
346void
347DefaultCommit<Impl>::setROB(ROB *rob_ptr)
348{
349    rob = rob_ptr;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::initStage()
355{
356    rob->setActiveThreads(activeThreads);
357    rob->resetEntries();
358
359    // Broadcast the number of free entries.
360    for (ThreadID tid = 0; tid < numThreads; tid++) {
361        toIEW->commitInfo[tid].usedROB = true;
362        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
363        toIEW->commitInfo[tid].emptyROB = true;
364    }
365
366    // Commit must broadcast the number of free entries it has at the
367    // start of the simulation, so it starts as active.
368    cpu->activateStage(O3CPU::CommitIdx);
369
370    cpu->activityThisCycle();
371    trapLatency = cpu->ticks(trapLatency);
372}
373
374template <class Impl>
375bool
376DefaultCommit<Impl>::drain()
377{
378    drainPending = true;
379
380    return false;
381}
382
383template <class Impl>
384void
385DefaultCommit<Impl>::switchOut()
386{
387    switchedOut = true;
388    drainPending = false;
389    rob->switchOut();
390}
391
392template <class Impl>
393void
394DefaultCommit<Impl>::resume()
395{
396    drainPending = false;
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::takeOverFrom()
402{
403    switchedOut = false;
404    _status = Active;
405    _nextStatus = Inactive;
406    for (ThreadID tid = 0; tid < numThreads; tid++) {
407        commitStatus[tid] = Idle;
408        changedROBNumEntries[tid] = false;
409        trapSquash[tid] = false;
410        tcSquash[tid] = false;
411    }
412    squashCounter = 0;
413    rob->takeOverFrom();
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::updateStatus()
419{
420    // reset ROB changed variable
421    list<ThreadID>::iterator threads = activeThreads->begin();
422    list<ThreadID>::iterator end = activeThreads->end();
423
424    while (threads != end) {
425        ThreadID tid = *threads++;
426
427        changedROBNumEntries[tid] = false;
428
429        // Also check if any of the threads has a trap pending
430        if (commitStatus[tid] == TrapPending ||
431            commitStatus[tid] == FetchTrapPending) {
432            _nextStatus = Active;
433        }
434    }
435
436    if (_nextStatus == Inactive && _status == Active) {
437        DPRINTF(Activity, "Deactivating stage.\n");
438        cpu->deactivateStage(O3CPU::CommitIdx);
439    } else if (_nextStatus == Active && _status == Inactive) {
440        DPRINTF(Activity, "Activating stage.\n");
441        cpu->activateStage(O3CPU::CommitIdx);
442    }
443
444    _status = _nextStatus;
445}
446
447template <class Impl>
448void
449DefaultCommit<Impl>::setNextStatus()
450{
451    int squashes = 0;
452
453    list<ThreadID>::iterator threads = activeThreads->begin();
454    list<ThreadID>::iterator end = activeThreads->end();
455
456    while (threads != end) {
457        ThreadID tid = *threads++;
458
459        if (commitStatus[tid] == ROBSquashing) {
460            squashes++;
461        }
462    }
463
464    squashCounter = squashes;
465
466    // If commit is currently squashing, then it will have activity for the
467    // next cycle. Set its next status as active.
468    if (squashCounter) {
469        _nextStatus = Active;
470    }
471}
472
473template <class Impl>
474bool
475DefaultCommit<Impl>::changedROBEntries()
476{
477    list<ThreadID>::iterator threads = activeThreads->begin();
478    list<ThreadID>::iterator end = activeThreads->end();
479
480    while (threads != end) {
481        ThreadID tid = *threads++;
482
483        if (changedROBNumEntries[tid]) {
484            return true;
485        }
486    }
487
488    return false;
489}
490
491template <class Impl>
492size_t
493DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
494{
495    return rob->numFreeEntries(tid);
496}
497
498template <class Impl>
499void
500DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
501{
502    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
503
504    TrapEvent *trap = new TrapEvent(this, tid);
505
506    cpu->schedule(trap, curTick() + trapLatency);
507    trapInFlight[tid] = true;
508    thread[tid]->trapPending = true;
509}
510
511template <class Impl>
512void
513DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
514{
515    assert(!trapInFlight[tid]);
516    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
517
518    tcSquash[tid] = true;
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::squashAll(ThreadID tid)
524{
525    // If we want to include the squashing instruction in the squash,
526    // then use one older sequence number.
527    // Hopefully this doesn't mess things up.  Basically I want to squash
528    // all instructions of this thread.
529    InstSeqNum squashed_inst = rob->isEmpty() ?
530        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
531
532    // All younger instructions will be squashed. Set the sequence
533    // number as the youngest instruction in the ROB (0 in this case.
534    // Hopefully nothing breaks.)
535    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
536
537    rob->squash(squashed_inst, tid);
538    changedROBNumEntries[tid] = true;
539
540    // Send back the sequence number of the squashed instruction.
541    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
542
543    // Send back the squash signal to tell stages that they should
544    // squash.
545    toIEW->commitInfo[tid].squash = true;
546
547    // Send back the rob squashing signal so other stages know that
548    // the ROB is in the process of squashing.
549    toIEW->commitInfo[tid].robSquashing = true;
550
551    toIEW->commitInfo[tid].mispredictInst = NULL;
552    toIEW->commitInfo[tid].squashInst = NULL;
553
554    toIEW->commitInfo[tid].pc = pc[tid];
555}
556
557template <class Impl>
558void
559DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
560{
561    squashAll(tid);
562
563    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
564
565    thread[tid]->trapPending = false;
566    thread[tid]->inSyscall = false;
567    trapInFlight[tid] = false;
568
569    trapSquash[tid] = false;
570
571    commitStatus[tid] = ROBSquashing;
572    cpu->activityThisCycle();
573}
574
575template <class Impl>
576void
577DefaultCommit<Impl>::squashFromTC(ThreadID tid)
578{
579    squashAll(tid);
580
581    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
582
583    thread[tid]->inSyscall = false;
584    assert(!thread[tid]->trapPending);
585
586    commitStatus[tid] = ROBSquashing;
587    cpu->activityThisCycle();
588
589    tcSquash[tid] = false;
590}
591
592template <class Impl>
593void
594DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
595        uint64_t squash_after_seq_num)
596{
597    youngestSeqNum[tid] = squash_after_seq_num;
598
599    rob->squash(squash_after_seq_num, tid);
600    changedROBNumEntries[tid] = true;
601
602    // Send back the sequence number of the squashed instruction.
603    toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
604
605    toIEW->commitInfo[tid].squashInst = head_inst;
606    // Send back the squash signal to tell stages that they should squash.
607    toIEW->commitInfo[tid].squash = true;
608
609    // Send back the rob squashing signal so other stages know that
610    // the ROB is in the process of squashing.
611    toIEW->commitInfo[tid].robSquashing = true;
612
613    toIEW->commitInfo[tid].mispredictInst = NULL;
614
615    toIEW->commitInfo[tid].pc = pc[tid];
616    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
617            tid, squash_after_seq_num);
618    commitStatus[tid] = ROBSquashing;
619}
620
621template <class Impl>
622void
623DefaultCommit<Impl>::tick()
624{
625    wroteToTimeBuffer = false;
626    _nextStatus = Inactive;
627
628    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
629        cpu->signalDrained();
630        drainPending = false;
631        return;
632    }
633
634    if (activeThreads->empty())
635        return;
636
637    list<ThreadID>::iterator threads = activeThreads->begin();
638    list<ThreadID>::iterator end = activeThreads->end();
639
640    // Check if any of the threads are done squashing.  Change the
641    // status if they are done.
642    while (threads != end) {
643        ThreadID tid = *threads++;
644
645        // Clear the bit saying if the thread has committed stores
646        // this cycle.
647        committedStores[tid] = false;
648
649        if (commitStatus[tid] == ROBSquashing) {
650
651            if (rob->isDoneSquashing(tid)) {
652                commitStatus[tid] = Running;
653            } else {
654                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
655                        " insts this cycle.\n", tid);
656                rob->doSquash(tid);
657                toIEW->commitInfo[tid].robSquashing = true;
658                wroteToTimeBuffer = true;
659            }
660        }
661    }
662
663    commit();
664
665    markCompletedInsts();
666
667    threads = activeThreads->begin();
668
669    while (threads != end) {
670        ThreadID tid = *threads++;
671
672        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
673            // The ROB has more instructions it can commit. Its next status
674            // will be active.
675            _nextStatus = Active;
676
677            DynInstPtr inst = rob->readHeadInst(tid);
678
679            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
680                    " ROB and ready to commit\n",
681                    tid, inst->seqNum, inst->pcState());
682
683        } else if (!rob->isEmpty(tid)) {
684            DynInstPtr inst = rob->readHeadInst(tid);
685
686            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
687                    "%s is head of ROB and not ready\n",
688                    tid, inst->seqNum, inst->pcState());
689        }
690
691        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
692                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
693    }
694
695
696    if (wroteToTimeBuffer) {
697        DPRINTF(Activity, "Activity This Cycle.\n");
698        cpu->activityThisCycle();
699    }
700
701    updateStatus();
702}
703
704#if FULL_SYSTEM
705template <class Impl>
706void
707DefaultCommit<Impl>::handleInterrupt()
708{
709    // Verify that we still have an interrupt to handle
710    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
711        DPRINTF(Commit, "Pending interrupt is cleared by master before "
712                "it got handled. Restart fetching from the orig path.\n");
713        toIEW->commitInfo[0].clearInterrupt = true;
714        interrupt = NoFault;
715        return;
716    }
717
718    // Wait until all in flight instructions are finished before enterring
719    // the interrupt.
720    if (cpu->instList.empty()) {
721        // Squash or record that I need to squash this cycle if
722        // an interrupt needed to be handled.
723        DPRINTF(Commit, "Interrupt detected.\n");
724
725        // Clear the interrupt now that it's going to be handled
726        toIEW->commitInfo[0].clearInterrupt = true;
727
728        assert(!thread[0]->inSyscall);
729        thread[0]->inSyscall = true;
730
731        // CPU will handle interrupt.
732        cpu->processInterrupts(interrupt);
733
734        thread[0]->inSyscall = false;
735
736        commitStatus[0] = TrapPending;
737
738        // Generate trap squash event.
739        generateTrapEvent(0);
740
741        interrupt = NoFault;
742    } else {
743        DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
744    }
745}
746
747template <class Impl>
748void
749DefaultCommit<Impl>::propagateInterrupt()
750{
751    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
752            tcSquash[0])
753        return;
754
755    // Process interrupts if interrupts are enabled, not in PAL
756    // mode, and no other traps or external squashes are currently
757    // pending.
758    // @todo: Allow other threads to handle interrupts.
759
760    // Get any interrupt that happened
761    interrupt = cpu->getInterrupts();
762
763    // Tell fetch that there is an interrupt pending.  This
764    // will make fetch wait until it sees a non PAL-mode PC,
765    // at which point it stops fetching instructions.
766    if (interrupt != NoFault)
767        toIEW->commitInfo[0].interruptPending = true;
768}
769
770#endif // FULL_SYSTEM
771
772template <class Impl>
773void
774DefaultCommit<Impl>::commit()
775{
776
777#if FULL_SYSTEM
778    // Check for any interrupt that we've already squashed for and start processing it.
779    if (interrupt != NoFault)
780        handleInterrupt();
781
782    // Check if we have a interrupt and get read to handle it
783    if (cpu->checkInterrupts(cpu->tcBase(0)))
784        propagateInterrupt();
785#endif // FULL_SYSTEM
786
787    ////////////////////////////////////
788    // Check for any possible squashes, handle them first
789    ////////////////////////////////////
790    list<ThreadID>::iterator threads = activeThreads->begin();
791    list<ThreadID>::iterator end = activeThreads->end();
792
793    while (threads != end) {
794        ThreadID tid = *threads++;
795
796        // Not sure which one takes priority.  I think if we have
797        // both, that's a bad sign.
798        if (trapSquash[tid] == true) {
799            assert(!tcSquash[tid]);
800            squashFromTrap(tid);
801        } else if (tcSquash[tid] == true) {
802            assert(commitStatus[tid] != TrapPending);
803            squashFromTC(tid);
804        }
805
806        // Squashed sequence number must be older than youngest valid
807        // instruction in the ROB. This prevents squashes from younger
808        // instructions overriding squashes from older instructions.
809        if (fromIEW->squash[tid] &&
810            commitStatus[tid] != TrapPending &&
811            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
812
813            if (fromIEW->mispredictInst[tid]) {
814                DPRINTF(Commit,
815                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
816                    tid,
817                    fromIEW->mispredictInst[tid]->instAddr(),
818                    fromIEW->squashedSeqNum[tid]);
819            } else {
820                DPRINTF(Commit,
821                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
822                    tid, fromIEW->squashedSeqNum[tid]);
823            }
824
825            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
826                    tid,
827                    fromIEW->pc[tid].nextInstAddr());
828
829            commitStatus[tid] = ROBSquashing;
830
831            // If we want to include the squashing instruction in the squash,
832            // then use one older sequence number.
833            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
834
835            if (fromIEW->includeSquashInst[tid] == true) {
836                squashed_inst--;
837            }
838
839            // All younger instructions will be squashed. Set the sequence
840            // number as the youngest instruction in the ROB.
841            youngestSeqNum[tid] = squashed_inst;
842
843            rob->squash(squashed_inst, tid);
844            changedROBNumEntries[tid] = true;
845
846            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
847
848            toIEW->commitInfo[tid].squash = true;
849
850            // Send back the rob squashing signal so other stages know that
851            // the ROB is in the process of squashing.
852            toIEW->commitInfo[tid].robSquashing = true;
853
854            toIEW->commitInfo[tid].mispredictInst =
855                fromIEW->mispredictInst[tid];
856            toIEW->commitInfo[tid].branchTaken =
857                fromIEW->branchTaken[tid];
858            toIEW->commitInfo[tid].squashInst = NULL;
859
860            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
861
862            if (toIEW->commitInfo[tid].mispredictInst) {
863                ++branchMispredicts;
864            }
865        }
866
867    }
868
869    setNextStatus();
870
871    if (squashCounter != numThreads) {
872        // If we're not currently squashing, then get instructions.
873        getInsts();
874
875        // Try to commit any instructions.
876        commitInsts();
877    }
878
879    //Check for any activity
880    threads = activeThreads->begin();
881
882    while (threads != end) {
883        ThreadID tid = *threads++;
884
885        if (changedROBNumEntries[tid]) {
886            toIEW->commitInfo[tid].usedROB = true;
887            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
888
889            wroteToTimeBuffer = true;
890            changedROBNumEntries[tid] = false;
891            if (rob->isEmpty(tid))
892                checkEmptyROB[tid] = true;
893        }
894
895        // ROB is only considered "empty" for previous stages if: a)
896        // ROB is empty, b) there are no outstanding stores, c) IEW
897        // stage has received any information regarding stores that
898        // committed.
899        // c) is checked by making sure to not consider the ROB empty
900        // on the same cycle as when stores have been committed.
901        // @todo: Make this handle multi-cycle communication between
902        // commit and IEW.
903        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
904            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
905            checkEmptyROB[tid] = false;
906            toIEW->commitInfo[tid].usedROB = true;
907            toIEW->commitInfo[tid].emptyROB = true;
908            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
909            wroteToTimeBuffer = true;
910        }
911
912    }
913}
914
915template <class Impl>
916void
917DefaultCommit<Impl>::commitInsts()
918{
919    ////////////////////////////////////
920    // Handle commit
921    // Note that commit will be handled prior to putting new
922    // instructions in the ROB so that the ROB only tries to commit
923    // instructions it has in this current cycle, and not instructions
924    // it is writing in during this cycle.  Can't commit and squash
925    // things at the same time...
926    ////////////////////////////////////
927
928    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
929
930    unsigned num_committed = 0;
931
932    DynInstPtr head_inst;
933
934    // Commit as many instructions as possible until the commit bandwidth
935    // limit is reached, or it becomes impossible to commit any more.
936    while (num_committed < commitWidth) {
937        int commit_thread = getCommittingThread();
938
939        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
940            break;
941
942        head_inst = rob->readHeadInst(commit_thread);
943
944        ThreadID tid = head_inst->threadNumber;
945
946        assert(tid == commit_thread);
947
948        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
949                head_inst->seqNum, tid);
950
951        // If the head instruction is squashed, it is ready to retire
952        // (be removed from the ROB) at any time.
953        if (head_inst->isSquashed()) {
954
955            DPRINTF(Commit, "Retiring squashed instruction from "
956                    "ROB.\n");
957
958            rob->retireHead(commit_thread);
959
960            ++commitSquashedInsts;
961
962            // Record that the number of ROB entries has changed.
963            changedROBNumEntries[tid] = true;
964        } else {
965            pc[tid] = head_inst->pcState();
966
967            // Increment the total number of non-speculative instructions
968            // executed.
969            // Hack for now: it really shouldn't happen until after the
970            // commit is deemed to be successful, but this count is needed
971            // for syscalls.
972            thread[tid]->funcExeInst++;
973
974            // Try to commit the head instruction.
975            bool commit_success = commitHead(head_inst, num_committed);
976
977            if (commit_success) {
978                ++num_committed;
979
980                changedROBNumEntries[tid] = true;
981
982                // Set the doneSeqNum to the youngest committed instruction.
983                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
984
985                ++commitCommittedInsts;
986
987                // To match the old model, don't count nops and instruction
988                // prefetches towards the total commit count.
989                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
990                    cpu->instDone(tid);
991                }
992
993                // Updates misc. registers.
994                head_inst->updateMiscRegs();
995
996                cpu->traceFunctions(pc[tid].instAddr());
997
998                TheISA::advancePC(pc[tid], head_inst->staticInst);
999
1000                // Keep track of the last sequence number commited
1001                lastCommitedSeqNum[tid] = head_inst->seqNum;
1002
1003                // If this is an instruction that doesn't play nicely with
1004                // others squash everything and restart fetch
1005                if (head_inst->isSquashAfter())
1006                    squashAfter(tid, head_inst, head_inst->seqNum);
1007
1008                int count = 0;
1009                Addr oldpc;
1010                // Debug statement.  Checks to make sure we're not
1011                // currently updating state while handling PC events.
1012                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1013                do {
1014                    oldpc = pc[tid].instAddr();
1015                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
1016                    count++;
1017                } while (oldpc != pc[tid].instAddr());
1018                if (count > 1) {
1019                    DPRINTF(Commit,
1020                            "PC skip function event, stopping commit\n");
1021                    break;
1022                }
1023            } else {
1024                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1025                        "[tid:%i] [sn:%i].\n",
1026                        head_inst->pcState(), tid ,head_inst->seqNum);
1027                break;
1028            }
1029        }
1030    }
1031
1032    DPRINTF(CommitRate, "%i\n", num_committed);
1033    numCommittedDist.sample(num_committed);
1034
1035    if (num_committed == commitWidth) {
1036        commitEligibleSamples++;
1037    }
1038}
1039
1040template <class Impl>
1041bool
1042DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1043{
1044    assert(head_inst);
1045
1046    ThreadID tid = head_inst->threadNumber;
1047
1048    // If the instruction is not executed yet, then it will need extra
1049    // handling.  Signal backwards that it should be executed.
1050    if (!head_inst->isExecuted()) {
1051        // Keep this number correct.  We have not yet actually executed
1052        // and committed this instruction.
1053        thread[tid]->funcExeInst--;
1054
1055        if (head_inst->isNonSpeculative() ||
1056            head_inst->isStoreConditional() ||
1057            head_inst->isMemBarrier() ||
1058            head_inst->isWriteBarrier()) {
1059
1060            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1061                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1062                    head_inst->seqNum, head_inst->pcState());
1063
1064            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1065                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1066                return false;
1067            }
1068
1069            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1070
1071            // Change the instruction so it won't try to commit again until
1072            // it is executed.
1073            head_inst->clearCanCommit();
1074
1075            ++commitNonSpecStalls;
1076
1077            return false;
1078        } else if (head_inst->isLoad()) {
1079            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1080                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1081                return false;
1082            }
1083
1084            assert(head_inst->uncacheable());
1085            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1086                    head_inst->seqNum, head_inst->pcState());
1087
1088            // Send back the non-speculative instruction's sequence
1089            // number.  Tell the lsq to re-execute the load.
1090            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1091            toIEW->commitInfo[tid].uncached = true;
1092            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1093
1094            head_inst->clearCanCommit();
1095
1096            return false;
1097        } else {
1098            panic("Trying to commit un-executed instruction "
1099                  "of unknown type!\n");
1100        }
1101    }
1102
1103    if (head_inst->isThreadSync()) {
1104        // Not handled for now.
1105        panic("Thread sync instructions are not handled yet.\n");
1106    }
1107
1108    // Check if the instruction caused a fault.  If so, trap.
1109    Fault inst_fault = head_inst->getFault();
1110
1111    // Stores mark themselves as completed.
1112    if (!head_inst->isStore() && inst_fault == NoFault) {
1113        head_inst->setCompleted();
1114    }
1115
1116#if USE_CHECKER
1117    // Use checker prior to updating anything due to traps or PC
1118    // based events.
1119    if (cpu->checker) {
1120        cpu->checker->verify(head_inst);
1121    }
1122#endif
1123
1124    if (inst_fault != NoFault) {
1125        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1126                head_inst->seqNum, head_inst->pcState());
1127
1128        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1129            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1130            return false;
1131        }
1132
1133        head_inst->setCompleted();
1134
1135#if USE_CHECKER
1136        if (cpu->checker && head_inst->isStore()) {
1137            cpu->checker->verify(head_inst);
1138        }
1139#endif
1140
1141        assert(!thread[tid]->inSyscall);
1142
1143        // Mark that we're in state update mode so that the trap's
1144        // execution doesn't generate extra squashes.
1145        thread[tid]->inSyscall = true;
1146
1147        // Execute the trap.  Although it's slightly unrealistic in
1148        // terms of timing (as it doesn't wait for the full timing of
1149        // the trap event to complete before updating state), it's
1150        // needed to update the state as soon as possible.  This
1151        // prevents external agents from changing any specific state
1152        // that the trap need.
1153        cpu->trap(inst_fault, tid, head_inst->staticInst);
1154
1155        // Exit state update mode to avoid accidental updating.
1156        thread[tid]->inSyscall = false;
1157
1158        commitStatus[tid] = TrapPending;
1159
1160        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1161            head_inst->seqNum);
1162        if (head_inst->traceData) {
1163            if (DTRACE(ExecFaulting)) {
1164                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1165                head_inst->traceData->setCPSeq(thread[tid]->numInst);
1166                head_inst->traceData->dump();
1167            }
1168            delete head_inst->traceData;
1169            head_inst->traceData = NULL;
1170        }
1171
1172        // Generate trap squash event.
1173        generateTrapEvent(tid);
1174        return false;
1175    }
1176
1177    updateComInstStats(head_inst);
1178
1179#if FULL_SYSTEM
1180    if (thread[tid]->profile) {
1181        thread[tid]->profilePC = head_inst->instAddr();
1182        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1183                                                          head_inst->staticInst);
1184
1185        if (node)
1186            thread[tid]->profileNode = node;
1187    }
1188    if (CPA::available()) {
1189        if (head_inst->isControl()) {
1190            ThreadContext *tc = thread[tid]->getTC();
1191            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1192        }
1193    }
1194#endif
1195    DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1196            head_inst->seqNum, head_inst->pcState());
1197    if (head_inst->traceData) {
1198        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1199        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1200        head_inst->traceData->dump();
1201        delete head_inst->traceData;
1202        head_inst->traceData = NULL;
1203    }
1204
1205    // Update the commit rename map
1206    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1207        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1208                                 head_inst->renamedDestRegIdx(i));
1209    }
1210
1211    // Finally clear the head ROB entry.
1212    rob->retireHead(tid);
1213
1214#if TRACING_ON
1215    // Print info needed by the pipeline activity viewer.
1216    DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1217             head_inst->fetchTick,
1218             head_inst->instAddr(),
1219             head_inst->microPC(),
1220             head_inst->seqNum,
1221             head_inst->staticInst->disassemble(head_inst->instAddr()));
1222    DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1223    DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1224    DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1225    DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1226    DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1227    DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1228#endif
1229
1230    // If this was a store, record it for this cycle.
1231    if (head_inst->isStore())
1232        committedStores[tid] = true;
1233
1234    // Return true to indicate that we have committed an instruction.
1235    return true;
1236}
1237
1238template <class Impl>
1239void
1240DefaultCommit<Impl>::getInsts()
1241{
1242    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1243
1244    // Read any renamed instructions and place them into the ROB.
1245    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1246
1247    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1248        DynInstPtr inst;
1249
1250        inst = fromRename->insts[inst_num];
1251        ThreadID tid = inst->threadNumber;
1252
1253        if (!inst->isSquashed() &&
1254            commitStatus[tid] != ROBSquashing &&
1255            commitStatus[tid] != TrapPending) {
1256            changedROBNumEntries[tid] = true;
1257
1258            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1259                    inst->pcState(), inst->seqNum, tid);
1260
1261            rob->insertInst(inst);
1262
1263            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1264
1265            youngestSeqNum[tid] = inst->seqNum;
1266        } else {
1267            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1268                    "squashed, skipping.\n",
1269                    inst->pcState(), inst->seqNum, tid);
1270        }
1271    }
1272}
1273
1274template <class Impl>
1275void
1276DefaultCommit<Impl>::skidInsert()
1277{
1278    DPRINTF(Commit, "Attempting to any instructions from rename into "
1279            "skidBuffer.\n");
1280
1281    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1282        DynInstPtr inst = fromRename->insts[inst_num];
1283
1284        if (!inst->isSquashed()) {
1285            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1286                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
1287                    inst->threadNumber);
1288            skidBuffer.push(inst);
1289        } else {
1290            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1291                    "squashed, skipping.\n",
1292                    inst->pcState(), inst->seqNum, inst->threadNumber);
1293        }
1294    }
1295}
1296
1297template <class Impl>
1298void
1299DefaultCommit<Impl>::markCompletedInsts()
1300{
1301    // Grab completed insts out of the IEW instruction queue, and mark
1302    // instructions completed within the ROB.
1303    for (int inst_num = 0;
1304         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1305         ++inst_num)
1306    {
1307        if (!fromIEW->insts[inst_num]->isSquashed()) {
1308            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1309                    "within ROB.\n",
1310                    fromIEW->insts[inst_num]->threadNumber,
1311                    fromIEW->insts[inst_num]->pcState(),
1312                    fromIEW->insts[inst_num]->seqNum);
1313
1314            // Mark the instruction as ready to commit.
1315            fromIEW->insts[inst_num]->setCanCommit();
1316        }
1317    }
1318}
1319
1320template <class Impl>
1321bool
1322DefaultCommit<Impl>::robDoneSquashing()
1323{
1324    list<ThreadID>::iterator threads = activeThreads->begin();
1325    list<ThreadID>::iterator end = activeThreads->end();
1326
1327    while (threads != end) {
1328        ThreadID tid = *threads++;
1329
1330        if (!rob->isDoneSquashing(tid))
1331            return false;
1332    }
1333
1334    return true;
1335}
1336
1337template <class Impl>
1338void
1339DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1340{
1341    ThreadID tid = inst->threadNumber;
1342
1343    //
1344    //  Pick off the software prefetches
1345    //
1346#ifdef TARGET_ALPHA
1347    if (inst->isDataPrefetch()) {
1348        statComSwp[tid]++;
1349    } else {
1350        statComInst[tid]++;
1351    }
1352#else
1353    statComInst[tid]++;
1354#endif
1355
1356    //
1357    //  Control Instructions
1358    //
1359    if (inst->isControl())
1360        statComBranches[tid]++;
1361
1362    //
1363    //  Memory references
1364    //
1365    if (inst->isMemRef()) {
1366        statComRefs[tid]++;
1367
1368        if (inst->isLoad()) {
1369            statComLoads[tid]++;
1370        }
1371    }
1372
1373    if (inst->isMemBarrier()) {
1374        statComMembars[tid]++;
1375    }
1376
1377    // Integer Instruction
1378    if (inst->isInteger())
1379        statComInteger[tid]++;
1380
1381    // Floating Point Instruction
1382    if (inst->isFloating())
1383        statComFloating[tid]++;
1384
1385    // Function Calls
1386    if (inst->isCall())
1387        statComFunctionCalls[tid]++;
1388
1389}
1390
1391////////////////////////////////////////
1392//                                    //
1393//  SMT COMMIT POLICY MAINTAINED HERE //
1394//                                    //
1395////////////////////////////////////////
1396template <class Impl>
1397ThreadID
1398DefaultCommit<Impl>::getCommittingThread()
1399{
1400    if (numThreads > 1) {
1401        switch (commitPolicy) {
1402
1403          case Aggressive:
1404            //If Policy is Aggressive, commit will call
1405            //this function multiple times per
1406            //cycle
1407            return oldestReady();
1408
1409          case RoundRobin:
1410            return roundRobin();
1411
1412          case OldestReady:
1413            return oldestReady();
1414
1415          default:
1416            return InvalidThreadID;
1417        }
1418    } else {
1419        assert(!activeThreads->empty());
1420        ThreadID tid = activeThreads->front();
1421
1422        if (commitStatus[tid] == Running ||
1423            commitStatus[tid] == Idle ||
1424            commitStatus[tid] == FetchTrapPending) {
1425            return tid;
1426        } else {
1427            return InvalidThreadID;
1428        }
1429    }
1430}
1431
1432template<class Impl>
1433ThreadID
1434DefaultCommit<Impl>::roundRobin()
1435{
1436    list<ThreadID>::iterator pri_iter = priority_list.begin();
1437    list<ThreadID>::iterator end      = priority_list.end();
1438
1439    while (pri_iter != end) {
1440        ThreadID tid = *pri_iter;
1441
1442        if (commitStatus[tid] == Running ||
1443            commitStatus[tid] == Idle ||
1444            commitStatus[tid] == FetchTrapPending) {
1445
1446            if (rob->isHeadReady(tid)) {
1447                priority_list.erase(pri_iter);
1448                priority_list.push_back(tid);
1449
1450                return tid;
1451            }
1452        }
1453
1454        pri_iter++;
1455    }
1456
1457    return InvalidThreadID;
1458}
1459
1460template<class Impl>
1461ThreadID
1462DefaultCommit<Impl>::oldestReady()
1463{
1464    unsigned oldest = 0;
1465    bool first = true;
1466
1467    list<ThreadID>::iterator threads = activeThreads->begin();
1468    list<ThreadID>::iterator end = activeThreads->end();
1469
1470    while (threads != end) {
1471        ThreadID tid = *threads++;
1472
1473        if (!rob->isEmpty(tid) &&
1474            (commitStatus[tid] == Running ||
1475             commitStatus[tid] == Idle ||
1476             commitStatus[tid] == FetchTrapPending)) {
1477
1478            if (rob->isHeadReady(tid)) {
1479
1480                DynInstPtr head_inst = rob->readHeadInst(tid);
1481
1482                if (first) {
1483                    oldest = tid;
1484                    first = false;
1485                } else if (head_inst->seqNum < oldest) {
1486                    oldest = tid;
1487                }
1488            }
1489        }
1490    }
1491
1492    if (!first) {
1493        return oldest;
1494    } else {
1495        return InvalidThreadID;
1496    }
1497}
1498