commit_impl.hh revision 8230:845c8eb5ac49 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "params/DerivO3CPU.hh"
58#include "sim/faults.hh"
59
60#if USE_CHECKER
61#include "cpu/checker/cpu.hh"
62#endif
63
64using namespace std;
65
66template <class Impl>
67DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
68                                          ThreadID _tid)
69    : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
70{
71    this->setFlags(AutoDelete);
72}
73
74template <class Impl>
75void
76DefaultCommit<Impl>::TrapEvent::process()
77{
78    // This will get reset by commit if it was switched out at the
79    // time of this event processing.
80    commit->trapSquash[tid] = true;
81}
82
83template <class Impl>
84const char *
85DefaultCommit<Impl>::TrapEvent::description() const
86{
87    return "Trap";
88}
89
90template <class Impl>
91DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
92    : cpu(_cpu),
93      squashCounter(0),
94      iewToCommitDelay(params->iewToCommitDelay),
95      commitToIEWDelay(params->commitToIEWDelay),
96      renameToROBDelay(params->renameToROBDelay),
97      fetchToCommitDelay(params->commitToFetchDelay),
98      renameWidth(params->renameWidth),
99      commitWidth(params->commitWidth),
100      numThreads(params->numThreads),
101      drainPending(false),
102      switchedOut(false),
103      trapLatency(params->trapLatency)
104{
105    _status = Active;
106    _nextStatus = Inactive;
107    std::string policy = params->smtCommitPolicy;
108
109    //Convert string to lowercase
110    std::transform(policy.begin(), policy.end(), policy.begin(),
111                   (int(*)(int)) tolower);
112
113    //Assign commit policy
114    if (policy == "aggressive"){
115        commitPolicy = Aggressive;
116
117        DPRINTF(Commit,"Commit Policy set to Aggressive.");
118    } else if (policy == "roundrobin"){
119        commitPolicy = RoundRobin;
120
121        //Set-Up Priority List
122        for (ThreadID tid = 0; tid < numThreads; tid++) {
123            priority_list.push_back(tid);
124        }
125
126        DPRINTF(Commit,"Commit Policy set to Round Robin.");
127    } else if (policy == "oldestready"){
128        commitPolicy = OldestReady;
129
130        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
131    } else {
132        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
133               "RoundRobin,OldestReady}");
134    }
135
136    for (ThreadID tid = 0; tid < numThreads; tid++) {
137        commitStatus[tid] = Idle;
138        changedROBNumEntries[tid] = false;
139        checkEmptyROB[tid] = false;
140        trapInFlight[tid] = false;
141        committedStores[tid] = false;
142        trapSquash[tid] = false;
143        tcSquash[tid] = false;
144        pc[tid].set(0);
145        lastCommitedSeqNum[tid] = 0;
146    }
147#if FULL_SYSTEM
148    interrupt = NoFault;
149#endif
150}
151
152template <class Impl>
153std::string
154DefaultCommit<Impl>::name() const
155{
156    return cpu->name() + ".commit";
157}
158
159template <class Impl>
160void
161DefaultCommit<Impl>::regStats()
162{
163    using namespace Stats;
164    commitCommittedInsts
165        .name(name() + ".commitCommittedInsts")
166        .desc("The number of committed instructions")
167        .prereq(commitCommittedInsts);
168    commitSquashedInsts
169        .name(name() + ".commitSquashedInsts")
170        .desc("The number of squashed insts skipped by commit")
171        .prereq(commitSquashedInsts);
172    commitSquashEvents
173        .name(name() + ".commitSquashEvents")
174        .desc("The number of times commit is told to squash")
175        .prereq(commitSquashEvents);
176    commitNonSpecStalls
177        .name(name() + ".commitNonSpecStalls")
178        .desc("The number of times commit has been forced to stall to "
179              "communicate backwards")
180        .prereq(commitNonSpecStalls);
181    branchMispredicts
182        .name(name() + ".branchMispredicts")
183        .desc("The number of times a branch was mispredicted")
184        .prereq(branchMispredicts);
185    numCommittedDist
186        .init(0,commitWidth,1)
187        .name(name() + ".COM:committed_per_cycle")
188        .desc("Number of insts commited each cycle")
189        .flags(Stats::pdf)
190        ;
191
192    statComInst
193        .init(cpu->numThreads)
194        .name(name() + ".COM:count")
195        .desc("Number of instructions committed")
196        .flags(total)
197        ;
198
199    statComSwp
200        .init(cpu->numThreads)
201        .name(name() + ".COM:swp_count")
202        .desc("Number of s/w prefetches committed")
203        .flags(total)
204        ;
205
206    statComRefs
207        .init(cpu->numThreads)
208        .name(name() +  ".COM:refs")
209        .desc("Number of memory references committed")
210        .flags(total)
211        ;
212
213    statComLoads
214        .init(cpu->numThreads)
215        .name(name() +  ".COM:loads")
216        .desc("Number of loads committed")
217        .flags(total)
218        ;
219
220    statComMembars
221        .init(cpu->numThreads)
222        .name(name() +  ".COM:membars")
223        .desc("Number of memory barriers committed")
224        .flags(total)
225        ;
226
227    statComBranches
228        .init(cpu->numThreads)
229        .name(name() + ".COM:branches")
230        .desc("Number of branches committed")
231        .flags(total)
232        ;
233
234    statComFloating
235        .init(cpu->numThreads)
236        .name(name() + ".COM:fp_insts")
237        .desc("Number of committed floating point instructions.")
238        .flags(total)
239        ;
240
241    statComInteger
242        .init(cpu->numThreads)
243        .name(name()+".COM:int_insts")
244        .desc("Number of committed integer instructions.")
245        .flags(total)
246        ;
247
248    statComFunctionCalls
249        .init(cpu->numThreads)
250        .name(name()+".COM:function_calls")
251        .desc("Number of function calls committed.")
252        .flags(total)
253        ;
254
255    commitEligible
256        .init(cpu->numThreads)
257        .name(name() + ".COM:bw_limited")
258        .desc("number of insts not committed due to BW limits")
259        .flags(total)
260        ;
261
262    commitEligibleSamples
263        .name(name() + ".COM:bw_lim_events")
264        .desc("number cycles where commit BW limit reached")
265        ;
266}
267
268template <class Impl>
269void
270DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
271{
272    thread = threads;
273}
274
275template <class Impl>
276void
277DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
278{
279    timeBuffer = tb_ptr;
280
281    // Setup wire to send information back to IEW.
282    toIEW = timeBuffer->getWire(0);
283
284    // Setup wire to read data from IEW (for the ROB).
285    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
286}
287
288template <class Impl>
289void
290DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
291{
292    fetchQueue = fq_ptr;
293
294    // Setup wire to get instructions from rename (for the ROB).
295    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
296}
297
298template <class Impl>
299void
300DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
301{
302    renameQueue = rq_ptr;
303
304    // Setup wire to get instructions from rename (for the ROB).
305    fromRename = renameQueue->getWire(-renameToROBDelay);
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
311{
312    iewQueue = iq_ptr;
313
314    // Setup wire to get instructions from IEW.
315    fromIEW = iewQueue->getWire(-iewToCommitDelay);
316}
317
318template <class Impl>
319void
320DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
321{
322    iewStage = iew_stage;
323}
324
325template<class Impl>
326void
327DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
328{
329    activeThreads = at_ptr;
330}
331
332template <class Impl>
333void
334DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
335{
336    for (ThreadID tid = 0; tid < numThreads; tid++)
337        renameMap[tid] = &rm_ptr[tid];
338}
339
340template <class Impl>
341void
342DefaultCommit<Impl>::setROB(ROB *rob_ptr)
343{
344    rob = rob_ptr;
345}
346
347template <class Impl>
348void
349DefaultCommit<Impl>::initStage()
350{
351    rob->setActiveThreads(activeThreads);
352    rob->resetEntries();
353
354    // Broadcast the number of free entries.
355    for (ThreadID tid = 0; tid < numThreads; tid++) {
356        toIEW->commitInfo[tid].usedROB = true;
357        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
358        toIEW->commitInfo[tid].emptyROB = true;
359    }
360
361    // Commit must broadcast the number of free entries it has at the
362    // start of the simulation, so it starts as active.
363    cpu->activateStage(O3CPU::CommitIdx);
364
365    cpu->activityThisCycle();
366    trapLatency = cpu->ticks(trapLatency);
367}
368
369template <class Impl>
370bool
371DefaultCommit<Impl>::drain()
372{
373    drainPending = true;
374
375    return false;
376}
377
378template <class Impl>
379void
380DefaultCommit<Impl>::switchOut()
381{
382    switchedOut = true;
383    drainPending = false;
384    rob->switchOut();
385}
386
387template <class Impl>
388void
389DefaultCommit<Impl>::resume()
390{
391    drainPending = false;
392}
393
394template <class Impl>
395void
396DefaultCommit<Impl>::takeOverFrom()
397{
398    switchedOut = false;
399    _status = Active;
400    _nextStatus = Inactive;
401    for (ThreadID tid = 0; tid < numThreads; tid++) {
402        commitStatus[tid] = Idle;
403        changedROBNumEntries[tid] = false;
404        trapSquash[tid] = false;
405        tcSquash[tid] = false;
406    }
407    squashCounter = 0;
408    rob->takeOverFrom();
409}
410
411template <class Impl>
412void
413DefaultCommit<Impl>::updateStatus()
414{
415    // reset ROB changed variable
416    list<ThreadID>::iterator threads = activeThreads->begin();
417    list<ThreadID>::iterator end = activeThreads->end();
418
419    while (threads != end) {
420        ThreadID tid = *threads++;
421
422        changedROBNumEntries[tid] = false;
423
424        // Also check if any of the threads has a trap pending
425        if (commitStatus[tid] == TrapPending ||
426            commitStatus[tid] == FetchTrapPending) {
427            _nextStatus = Active;
428        }
429    }
430
431    if (_nextStatus == Inactive && _status == Active) {
432        DPRINTF(Activity, "Deactivating stage.\n");
433        cpu->deactivateStage(O3CPU::CommitIdx);
434    } else if (_nextStatus == Active && _status == Inactive) {
435        DPRINTF(Activity, "Activating stage.\n");
436        cpu->activateStage(O3CPU::CommitIdx);
437    }
438
439    _status = _nextStatus;
440}
441
442template <class Impl>
443void
444DefaultCommit<Impl>::setNextStatus()
445{
446    int squashes = 0;
447
448    list<ThreadID>::iterator threads = activeThreads->begin();
449    list<ThreadID>::iterator end = activeThreads->end();
450
451    while (threads != end) {
452        ThreadID tid = *threads++;
453
454        if (commitStatus[tid] == ROBSquashing) {
455            squashes++;
456        }
457    }
458
459    squashCounter = squashes;
460
461    // If commit is currently squashing, then it will have activity for the
462    // next cycle. Set its next status as active.
463    if (squashCounter) {
464        _nextStatus = Active;
465    }
466}
467
468template <class Impl>
469bool
470DefaultCommit<Impl>::changedROBEntries()
471{
472    list<ThreadID>::iterator threads = activeThreads->begin();
473    list<ThreadID>::iterator end = activeThreads->end();
474
475    while (threads != end) {
476        ThreadID tid = *threads++;
477
478        if (changedROBNumEntries[tid]) {
479            return true;
480        }
481    }
482
483    return false;
484}
485
486template <class Impl>
487size_t
488DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
489{
490    return rob->numFreeEntries(tid);
491}
492
493template <class Impl>
494void
495DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
496{
497    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
498
499    TrapEvent *trap = new TrapEvent(this, tid);
500
501    cpu->schedule(trap, curTick() + trapLatency);
502    trapInFlight[tid] = true;
503}
504
505template <class Impl>
506void
507DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
508{
509    assert(!trapInFlight[tid]);
510    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
511
512    tcSquash[tid] = true;
513}
514
515template <class Impl>
516void
517DefaultCommit<Impl>::squashAll(ThreadID tid)
518{
519    // If we want to include the squashing instruction in the squash,
520    // then use one older sequence number.
521    // Hopefully this doesn't mess things up.  Basically I want to squash
522    // all instructions of this thread.
523    InstSeqNum squashed_inst = rob->isEmpty() ?
524        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
525
526    // All younger instructions will be squashed. Set the sequence
527    // number as the youngest instruction in the ROB (0 in this case.
528    // Hopefully nothing breaks.)
529    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
530
531    rob->squash(squashed_inst, tid);
532    changedROBNumEntries[tid] = true;
533
534    // Send back the sequence number of the squashed instruction.
535    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
536
537    // Send back the squash signal to tell stages that they should
538    // squash.
539    toIEW->commitInfo[tid].squash = true;
540
541    // Send back the rob squashing signal so other stages know that
542    // the ROB is in the process of squashing.
543    toIEW->commitInfo[tid].robSquashing = true;
544
545    toIEW->commitInfo[tid].mispredictInst = NULL;
546    toIEW->commitInfo[tid].squashInst = NULL;
547
548    toIEW->commitInfo[tid].pc = pc[tid];
549}
550
551template <class Impl>
552void
553DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
554{
555    squashAll(tid);
556
557    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
558
559    thread[tid]->trapPending = false;
560    thread[tid]->inSyscall = false;
561    trapInFlight[tid] = false;
562
563    trapSquash[tid] = false;
564
565    commitStatus[tid] = ROBSquashing;
566    cpu->activityThisCycle();
567}
568
569template <class Impl>
570void
571DefaultCommit<Impl>::squashFromTC(ThreadID tid)
572{
573    squashAll(tid);
574
575    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
576
577    thread[tid]->inSyscall = false;
578    assert(!thread[tid]->trapPending);
579
580    commitStatus[tid] = ROBSquashing;
581    cpu->activityThisCycle();
582
583    tcSquash[tid] = false;
584}
585
586template <class Impl>
587void
588DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
589        uint64_t squash_after_seq_num)
590{
591    youngestSeqNum[tid] = squash_after_seq_num;
592
593    rob->squash(squash_after_seq_num, tid);
594    changedROBNumEntries[tid] = true;
595
596    // Send back the sequence number of the squashed instruction.
597    toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
598
599    toIEW->commitInfo[tid].squashInst = head_inst;
600    // Send back the squash signal to tell stages that they should squash.
601    toIEW->commitInfo[tid].squash = true;
602
603    // Send back the rob squashing signal so other stages know that
604    // the ROB is in the process of squashing.
605    toIEW->commitInfo[tid].robSquashing = true;
606
607    toIEW->commitInfo[tid].mispredictInst = NULL;
608
609    toIEW->commitInfo[tid].pc = pc[tid];
610    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
611            tid, squash_after_seq_num);
612    commitStatus[tid] = ROBSquashing;
613}
614
615template <class Impl>
616void
617DefaultCommit<Impl>::tick()
618{
619    wroteToTimeBuffer = false;
620    _nextStatus = Inactive;
621
622    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
623        cpu->signalDrained();
624        drainPending = false;
625        return;
626    }
627
628    if (activeThreads->empty())
629        return;
630
631    list<ThreadID>::iterator threads = activeThreads->begin();
632    list<ThreadID>::iterator end = activeThreads->end();
633
634    // Check if any of the threads are done squashing.  Change the
635    // status if they are done.
636    while (threads != end) {
637        ThreadID tid = *threads++;
638
639        // Clear the bit saying if the thread has committed stores
640        // this cycle.
641        committedStores[tid] = false;
642
643        if (commitStatus[tid] == ROBSquashing) {
644
645            if (rob->isDoneSquashing(tid)) {
646                commitStatus[tid] = Running;
647            } else {
648                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
649                        " insts this cycle.\n", tid);
650                rob->doSquash(tid);
651                toIEW->commitInfo[tid].robSquashing = true;
652                wroteToTimeBuffer = true;
653            }
654        }
655    }
656
657    commit();
658
659    markCompletedInsts();
660
661    threads = activeThreads->begin();
662
663    while (threads != end) {
664        ThreadID tid = *threads++;
665
666        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
667            // The ROB has more instructions it can commit. Its next status
668            // will be active.
669            _nextStatus = Active;
670
671            DynInstPtr inst = rob->readHeadInst(tid);
672
673            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
674                    " ROB and ready to commit\n",
675                    tid, inst->seqNum, inst->pcState());
676
677        } else if (!rob->isEmpty(tid)) {
678            DynInstPtr inst = rob->readHeadInst(tid);
679
680            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
681                    "%s is head of ROB and not ready\n",
682                    tid, inst->seqNum, inst->pcState());
683        }
684
685        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
686                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
687    }
688
689
690    if (wroteToTimeBuffer) {
691        DPRINTF(Activity, "Activity This Cycle.\n");
692        cpu->activityThisCycle();
693    }
694
695    updateStatus();
696}
697
698#if FULL_SYSTEM
699template <class Impl>
700void
701DefaultCommit<Impl>::handleInterrupt()
702{
703    // Verify that we still have an interrupt to handle
704    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
705        DPRINTF(Commit, "Pending interrupt is cleared by master before "
706                "it got handled. Restart fetching from the orig path.\n");
707        toIEW->commitInfo[0].clearInterrupt = true;
708        interrupt = NoFault;
709        return;
710    }
711
712    // Wait until the ROB is empty and all stores have drained in
713    // order to enter the interrupt.
714    if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
715        // Squash or record that I need to squash this cycle if
716        // an interrupt needed to be handled.
717        DPRINTF(Commit, "Interrupt detected.\n");
718
719        // Clear the interrupt now that it's going to be handled
720        toIEW->commitInfo[0].clearInterrupt = true;
721
722        assert(!thread[0]->inSyscall);
723        thread[0]->inSyscall = true;
724
725        // CPU will handle interrupt.
726        cpu->processInterrupts(interrupt);
727
728        thread[0]->inSyscall = false;
729
730        commitStatus[0] = TrapPending;
731
732        // Generate trap squash event.
733        generateTrapEvent(0);
734
735        interrupt = NoFault;
736    } else {
737        DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
738    }
739}
740
741template <class Impl>
742void
743DefaultCommit<Impl>::propagateInterrupt()
744{
745    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
746            tcSquash[0])
747        return;
748
749    // Process interrupts if interrupts are enabled, not in PAL
750    // mode, and no other traps or external squashes are currently
751    // pending.
752    // @todo: Allow other threads to handle interrupts.
753
754    // Get any interrupt that happened
755    interrupt = cpu->getInterrupts();
756
757    // Tell fetch that there is an interrupt pending.  This
758    // will make fetch wait until it sees a non PAL-mode PC,
759    // at which point it stops fetching instructions.
760    if (interrupt != NoFault)
761        toIEW->commitInfo[0].interruptPending = true;
762}
763
764#endif // FULL_SYSTEM
765
766template <class Impl>
767void
768DefaultCommit<Impl>::commit()
769{
770
771#if FULL_SYSTEM
772    // Check for any interrupt that we've already squashed for and start processing it.
773    if (interrupt != NoFault)
774        handleInterrupt();
775
776    // Check if we have a interrupt and get read to handle it
777    if (cpu->checkInterrupts(cpu->tcBase(0)))
778        propagateInterrupt();
779#endif // FULL_SYSTEM
780
781    ////////////////////////////////////
782    // Check for any possible squashes, handle them first
783    ////////////////////////////////////
784    list<ThreadID>::iterator threads = activeThreads->begin();
785    list<ThreadID>::iterator end = activeThreads->end();
786
787    while (threads != end) {
788        ThreadID tid = *threads++;
789
790        // Not sure which one takes priority.  I think if we have
791        // both, that's a bad sign.
792        if (trapSquash[tid] == true) {
793            assert(!tcSquash[tid]);
794            squashFromTrap(tid);
795        } else if (tcSquash[tid] == true) {
796            assert(commitStatus[tid] != TrapPending);
797            squashFromTC(tid);
798        }
799
800        // Squashed sequence number must be older than youngest valid
801        // instruction in the ROB. This prevents squashes from younger
802        // instructions overriding squashes from older instructions.
803        if (fromIEW->squash[tid] &&
804            commitStatus[tid] != TrapPending &&
805            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
806
807            if (fromIEW->mispredictInst[tid]) {
808                DPRINTF(Commit,
809                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
810                    tid,
811                    fromIEW->mispredictInst[tid]->instAddr(),
812                    fromIEW->squashedSeqNum[tid]);
813            } else {
814                DPRINTF(Commit,
815                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
816                    tid, fromIEW->squashedSeqNum[tid]);
817            }
818
819            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
820                    tid,
821                    fromIEW->pc[tid].nextInstAddr());
822
823            commitStatus[tid] = ROBSquashing;
824
825            // If we want to include the squashing instruction in the squash,
826            // then use one older sequence number.
827            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
828
829            if (fromIEW->includeSquashInst[tid] == true) {
830                squashed_inst--;
831            }
832
833            // All younger instructions will be squashed. Set the sequence
834            // number as the youngest instruction in the ROB.
835            youngestSeqNum[tid] = squashed_inst;
836
837            rob->squash(squashed_inst, tid);
838            changedROBNumEntries[tid] = true;
839
840            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
841
842            toIEW->commitInfo[tid].squash = true;
843
844            // Send back the rob squashing signal so other stages know that
845            // the ROB is in the process of squashing.
846            toIEW->commitInfo[tid].robSquashing = true;
847
848            toIEW->commitInfo[tid].mispredictInst =
849                fromIEW->mispredictInst[tid];
850            toIEW->commitInfo[tid].branchTaken =
851                fromIEW->branchTaken[tid];
852            toIEW->commitInfo[tid].squashInst = NULL;
853
854            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
855
856            if (toIEW->commitInfo[tid].mispredictInst) {
857                ++branchMispredicts;
858            }
859        }
860
861    }
862
863    setNextStatus();
864
865    if (squashCounter != numThreads) {
866        // If we're not currently squashing, then get instructions.
867        getInsts();
868
869        // Try to commit any instructions.
870        commitInsts();
871    }
872
873    //Check for any activity
874    threads = activeThreads->begin();
875
876    while (threads != end) {
877        ThreadID tid = *threads++;
878
879        if (changedROBNumEntries[tid]) {
880            toIEW->commitInfo[tid].usedROB = true;
881            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
882
883            wroteToTimeBuffer = true;
884            changedROBNumEntries[tid] = false;
885            if (rob->isEmpty(tid))
886                checkEmptyROB[tid] = true;
887        }
888
889        // ROB is only considered "empty" for previous stages if: a)
890        // ROB is empty, b) there are no outstanding stores, c) IEW
891        // stage has received any information regarding stores that
892        // committed.
893        // c) is checked by making sure to not consider the ROB empty
894        // on the same cycle as when stores have been committed.
895        // @todo: Make this handle multi-cycle communication between
896        // commit and IEW.
897        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
898            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
899            checkEmptyROB[tid] = false;
900            toIEW->commitInfo[tid].usedROB = true;
901            toIEW->commitInfo[tid].emptyROB = true;
902            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
903            wroteToTimeBuffer = true;
904        }
905
906    }
907}
908
909template <class Impl>
910void
911DefaultCommit<Impl>::commitInsts()
912{
913    ////////////////////////////////////
914    // Handle commit
915    // Note that commit will be handled prior to putting new
916    // instructions in the ROB so that the ROB only tries to commit
917    // instructions it has in this current cycle, and not instructions
918    // it is writing in during this cycle.  Can't commit and squash
919    // things at the same time...
920    ////////////////////////////////////
921
922    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
923
924    unsigned num_committed = 0;
925
926    DynInstPtr head_inst;
927
928    // Commit as many instructions as possible until the commit bandwidth
929    // limit is reached, or it becomes impossible to commit any more.
930    while (num_committed < commitWidth) {
931        int commit_thread = getCommittingThread();
932
933        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
934            break;
935
936        head_inst = rob->readHeadInst(commit_thread);
937
938        ThreadID tid = head_inst->threadNumber;
939
940        assert(tid == commit_thread);
941
942        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
943                head_inst->seqNum, tid);
944
945        // If the head instruction is squashed, it is ready to retire
946        // (be removed from the ROB) at any time.
947        if (head_inst->isSquashed()) {
948
949            DPRINTF(Commit, "Retiring squashed instruction from "
950                    "ROB.\n");
951
952            rob->retireHead(commit_thread);
953
954            ++commitSquashedInsts;
955
956            // Record that the number of ROB entries has changed.
957            changedROBNumEntries[tid] = true;
958        } else {
959            pc[tid] = head_inst->pcState();
960
961            // Increment the total number of non-speculative instructions
962            // executed.
963            // Hack for now: it really shouldn't happen until after the
964            // commit is deemed to be successful, but this count is needed
965            // for syscalls.
966            thread[tid]->funcExeInst++;
967
968            // Try to commit the head instruction.
969            bool commit_success = commitHead(head_inst, num_committed);
970
971            if (commit_success) {
972                ++num_committed;
973
974                changedROBNumEntries[tid] = true;
975
976                // Set the doneSeqNum to the youngest committed instruction.
977                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
978
979                ++commitCommittedInsts;
980
981                // To match the old model, don't count nops and instruction
982                // prefetches towards the total commit count.
983                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
984                    cpu->instDone(tid);
985                }
986
987                // Updates misc. registers.
988                head_inst->updateMiscRegs();
989
990                TheISA::advancePC(pc[tid], head_inst->staticInst);
991
992                // Keep track of the last sequence number commited
993                lastCommitedSeqNum[tid] = head_inst->seqNum;
994
995                // If this is an instruction that doesn't play nicely with
996                // others squash everything and restart fetch
997                if (head_inst->isSquashAfter())
998                    squashAfter(tid, head_inst, head_inst->seqNum);
999
1000                int count = 0;
1001                Addr oldpc;
1002                // Debug statement.  Checks to make sure we're not
1003                // currently updating state while handling PC events.
1004                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1005                do {
1006                    oldpc = pc[tid].instAddr();
1007                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
1008                    count++;
1009                } while (oldpc != pc[tid].instAddr());
1010                if (count > 1) {
1011                    DPRINTF(Commit,
1012                            "PC skip function event, stopping commit\n");
1013                    break;
1014                }
1015            } else {
1016                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1017                        "[tid:%i] [sn:%i].\n",
1018                        head_inst->pcState(), tid ,head_inst->seqNum);
1019                break;
1020            }
1021        }
1022    }
1023
1024    DPRINTF(CommitRate, "%i\n", num_committed);
1025    numCommittedDist.sample(num_committed);
1026
1027    if (num_committed == commitWidth) {
1028        commitEligibleSamples++;
1029    }
1030}
1031
1032template <class Impl>
1033bool
1034DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1035{
1036    assert(head_inst);
1037
1038    ThreadID tid = head_inst->threadNumber;
1039
1040    // If the instruction is not executed yet, then it will need extra
1041    // handling.  Signal backwards that it should be executed.
1042    if (!head_inst->isExecuted()) {
1043        // Keep this number correct.  We have not yet actually executed
1044        // and committed this instruction.
1045        thread[tid]->funcExeInst--;
1046
1047        if (head_inst->isNonSpeculative() ||
1048            head_inst->isStoreConditional() ||
1049            head_inst->isMemBarrier() ||
1050            head_inst->isWriteBarrier()) {
1051
1052            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1053                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1054                    head_inst->seqNum, head_inst->pcState());
1055
1056            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1057                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1058                return false;
1059            }
1060
1061            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1062
1063            // Change the instruction so it won't try to commit again until
1064            // it is executed.
1065            head_inst->clearCanCommit();
1066
1067            ++commitNonSpecStalls;
1068
1069            return false;
1070        } else if (head_inst->isLoad()) {
1071            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1072                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1073                return false;
1074            }
1075
1076            assert(head_inst->uncacheable());
1077            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1078                    head_inst->seqNum, head_inst->pcState());
1079
1080            // Send back the non-speculative instruction's sequence
1081            // number.  Tell the lsq to re-execute the load.
1082            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1083            toIEW->commitInfo[tid].uncached = true;
1084            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1085
1086            head_inst->clearCanCommit();
1087
1088            return false;
1089        } else {
1090            panic("Trying to commit un-executed instruction "
1091                  "of unknown type!\n");
1092        }
1093    }
1094
1095    if (head_inst->isThreadSync()) {
1096        // Not handled for now.
1097        panic("Thread sync instructions are not handled yet.\n");
1098    }
1099
1100    // Check if the instruction caused a fault.  If so, trap.
1101    Fault inst_fault = head_inst->getFault();
1102
1103    // Stores mark themselves as completed.
1104    if (!head_inst->isStore() && inst_fault == NoFault) {
1105        head_inst->setCompleted();
1106    }
1107
1108#if USE_CHECKER
1109    // Use checker prior to updating anything due to traps or PC
1110    // based events.
1111    if (cpu->checker) {
1112        cpu->checker->verify(head_inst);
1113    }
1114#endif
1115
1116    if (inst_fault != NoFault) {
1117        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1118                head_inst->seqNum, head_inst->pcState());
1119
1120        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1121            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1122            return false;
1123        }
1124
1125        head_inst->setCompleted();
1126
1127#if USE_CHECKER
1128        if (cpu->checker && head_inst->isStore()) {
1129            cpu->checker->verify(head_inst);
1130        }
1131#endif
1132
1133        assert(!thread[tid]->inSyscall);
1134
1135        // Mark that we're in state update mode so that the trap's
1136        // execution doesn't generate extra squashes.
1137        thread[tid]->inSyscall = true;
1138
1139        // Execute the trap.  Although it's slightly unrealistic in
1140        // terms of timing (as it doesn't wait for the full timing of
1141        // the trap event to complete before updating state), it's
1142        // needed to update the state as soon as possible.  This
1143        // prevents external agents from changing any specific state
1144        // that the trap need.
1145        cpu->trap(inst_fault, tid, head_inst->staticInst);
1146
1147        // Exit state update mode to avoid accidental updating.
1148        thread[tid]->inSyscall = false;
1149
1150        commitStatus[tid] = TrapPending;
1151
1152        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1153            head_inst->seqNum);
1154        if (head_inst->traceData) {
1155            if (DTRACE(ExecFaulting)) {
1156                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1157                head_inst->traceData->setCPSeq(thread[tid]->numInst);
1158                head_inst->traceData->dump();
1159            }
1160            delete head_inst->traceData;
1161            head_inst->traceData = NULL;
1162        }
1163
1164        // Generate trap squash event.
1165        generateTrapEvent(tid);
1166        return false;
1167    }
1168
1169    updateComInstStats(head_inst);
1170
1171#if FULL_SYSTEM
1172    if (thread[tid]->profile) {
1173        thread[tid]->profilePC = head_inst->instAddr();
1174        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1175                                                          head_inst->staticInst);
1176
1177        if (node)
1178            thread[tid]->profileNode = node;
1179    }
1180    if (CPA::available()) {
1181        if (head_inst->isControl()) {
1182            ThreadContext *tc = thread[tid]->getTC();
1183            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1184        }
1185    }
1186#endif
1187    DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
1188            head_inst->seqNum);
1189    if (head_inst->traceData) {
1190        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1191        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1192        head_inst->traceData->dump();
1193        delete head_inst->traceData;
1194        head_inst->traceData = NULL;
1195    }
1196
1197    // Update the commit rename map
1198    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1199        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1200                                 head_inst->renamedDestRegIdx(i));
1201    }
1202
1203    // Finally clear the head ROB entry.
1204    rob->retireHead(tid);
1205
1206    // If this was a store, record it for this cycle.
1207    if (head_inst->isStore())
1208        committedStores[tid] = true;
1209
1210    // Return true to indicate that we have committed an instruction.
1211    return true;
1212}
1213
1214template <class Impl>
1215void
1216DefaultCommit<Impl>::getInsts()
1217{
1218    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1219
1220    // Read any renamed instructions and place them into the ROB.
1221    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1222
1223    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1224        DynInstPtr inst;
1225
1226        inst = fromRename->insts[inst_num];
1227        ThreadID tid = inst->threadNumber;
1228
1229        if (!inst->isSquashed() &&
1230            commitStatus[tid] != ROBSquashing &&
1231            commitStatus[tid] != TrapPending) {
1232            changedROBNumEntries[tid] = true;
1233
1234            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1235                    inst->pcState(), inst->seqNum, tid);
1236
1237            rob->insertInst(inst);
1238
1239            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1240
1241            youngestSeqNum[tid] = inst->seqNum;
1242        } else {
1243            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1244                    "squashed, skipping.\n",
1245                    inst->pcState(), inst->seqNum, tid);
1246        }
1247    }
1248}
1249
1250template <class Impl>
1251void
1252DefaultCommit<Impl>::skidInsert()
1253{
1254    DPRINTF(Commit, "Attempting to any instructions from rename into "
1255            "skidBuffer.\n");
1256
1257    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1258        DynInstPtr inst = fromRename->insts[inst_num];
1259
1260        if (!inst->isSquashed()) {
1261            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1262                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
1263                    inst->threadNumber);
1264            skidBuffer.push(inst);
1265        } else {
1266            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1267                    "squashed, skipping.\n",
1268                    inst->pcState(), inst->seqNum, inst->threadNumber);
1269        }
1270    }
1271}
1272
1273template <class Impl>
1274void
1275DefaultCommit<Impl>::markCompletedInsts()
1276{
1277    // Grab completed insts out of the IEW instruction queue, and mark
1278    // instructions completed within the ROB.
1279    for (int inst_num = 0;
1280         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1281         ++inst_num)
1282    {
1283        if (!fromIEW->insts[inst_num]->isSquashed()) {
1284            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1285                    "within ROB.\n",
1286                    fromIEW->insts[inst_num]->threadNumber,
1287                    fromIEW->insts[inst_num]->pcState(),
1288                    fromIEW->insts[inst_num]->seqNum);
1289
1290            // Mark the instruction as ready to commit.
1291            fromIEW->insts[inst_num]->setCanCommit();
1292        }
1293    }
1294}
1295
1296template <class Impl>
1297bool
1298DefaultCommit<Impl>::robDoneSquashing()
1299{
1300    list<ThreadID>::iterator threads = activeThreads->begin();
1301    list<ThreadID>::iterator end = activeThreads->end();
1302
1303    while (threads != end) {
1304        ThreadID tid = *threads++;
1305
1306        if (!rob->isDoneSquashing(tid))
1307            return false;
1308    }
1309
1310    return true;
1311}
1312
1313template <class Impl>
1314void
1315DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1316{
1317    ThreadID tid = inst->threadNumber;
1318
1319    //
1320    //  Pick off the software prefetches
1321    //
1322#ifdef TARGET_ALPHA
1323    if (inst->isDataPrefetch()) {
1324        statComSwp[tid]++;
1325    } else {
1326        statComInst[tid]++;
1327    }
1328#else
1329    statComInst[tid]++;
1330#endif
1331
1332    //
1333    //  Control Instructions
1334    //
1335    if (inst->isControl())
1336        statComBranches[tid]++;
1337
1338    //
1339    //  Memory references
1340    //
1341    if (inst->isMemRef()) {
1342        statComRefs[tid]++;
1343
1344        if (inst->isLoad()) {
1345            statComLoads[tid]++;
1346        }
1347    }
1348
1349    if (inst->isMemBarrier()) {
1350        statComMembars[tid]++;
1351    }
1352
1353    // Integer Instruction
1354    if (inst->isInteger())
1355        statComInteger[tid]++;
1356
1357    // Floating Point Instruction
1358    if (inst->isFloating())
1359        statComFloating[tid]++;
1360
1361    // Function Calls
1362    if (inst->isCall())
1363        statComFunctionCalls[tid]++;
1364
1365}
1366
1367////////////////////////////////////////
1368//                                    //
1369//  SMT COMMIT POLICY MAINTAINED HERE //
1370//                                    //
1371////////////////////////////////////////
1372template <class Impl>
1373ThreadID
1374DefaultCommit<Impl>::getCommittingThread()
1375{
1376    if (numThreads > 1) {
1377        switch (commitPolicy) {
1378
1379          case Aggressive:
1380            //If Policy is Aggressive, commit will call
1381            //this function multiple times per
1382            //cycle
1383            return oldestReady();
1384
1385          case RoundRobin:
1386            return roundRobin();
1387
1388          case OldestReady:
1389            return oldestReady();
1390
1391          default:
1392            return InvalidThreadID;
1393        }
1394    } else {
1395        assert(!activeThreads->empty());
1396        ThreadID tid = activeThreads->front();
1397
1398        if (commitStatus[tid] == Running ||
1399            commitStatus[tid] == Idle ||
1400            commitStatus[tid] == FetchTrapPending) {
1401            return tid;
1402        } else {
1403            return InvalidThreadID;
1404        }
1405    }
1406}
1407
1408template<class Impl>
1409ThreadID
1410DefaultCommit<Impl>::roundRobin()
1411{
1412    list<ThreadID>::iterator pri_iter = priority_list.begin();
1413    list<ThreadID>::iterator end      = priority_list.end();
1414
1415    while (pri_iter != end) {
1416        ThreadID tid = *pri_iter;
1417
1418        if (commitStatus[tid] == Running ||
1419            commitStatus[tid] == Idle ||
1420            commitStatus[tid] == FetchTrapPending) {
1421
1422            if (rob->isHeadReady(tid)) {
1423                priority_list.erase(pri_iter);
1424                priority_list.push_back(tid);
1425
1426                return tid;
1427            }
1428        }
1429
1430        pri_iter++;
1431    }
1432
1433    return InvalidThreadID;
1434}
1435
1436template<class Impl>
1437ThreadID
1438DefaultCommit<Impl>::oldestReady()
1439{
1440    unsigned oldest = 0;
1441    bool first = true;
1442
1443    list<ThreadID>::iterator threads = activeThreads->begin();
1444    list<ThreadID>::iterator end = activeThreads->end();
1445
1446    while (threads != end) {
1447        ThreadID tid = *threads++;
1448
1449        if (!rob->isEmpty(tid) &&
1450            (commitStatus[tid] == Running ||
1451             commitStatus[tid] == Idle ||
1452             commitStatus[tid] == FetchTrapPending)) {
1453
1454            if (rob->isHeadReady(tid)) {
1455
1456                DynInstPtr head_inst = rob->readHeadInst(tid);
1457
1458                if (first) {
1459                    oldest = tid;
1460                    first = false;
1461                } else if (head_inst->seqNum < oldest) {
1462                    oldest = tid;
1463                }
1464            }
1465        }
1466    }
1467
1468    if (!first) {
1469        return oldest;
1470    } else {
1471        return InvalidThreadID;
1472    }
1473}
1474