commit_impl.hh revision 7783:9b880b40ac10
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/cp_annotate.hh" 49#include "base/loader/symtab.hh" 50#include "base/timebuf.hh" 51#include "config/full_system.hh" 52#include "config/the_isa.hh" 53#include "config/use_checker.hh" 54#include "cpu/exetrace.hh" 55#include "cpu/o3/commit.hh" 56#include "cpu/o3/thread_state.hh" 57#include "params/DerivO3CPU.hh" 58 59#if USE_CHECKER 60#include "cpu/checker/cpu.hh" 61#endif 62 63using namespace std; 64 65template <class Impl> 66DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 67 ThreadID _tid) 68 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) 69{ 70 this->setFlags(AutoDelete); 71} 72 73template <class Impl> 74void 75DefaultCommit<Impl>::TrapEvent::process() 76{ 77 // This will get reset by commit if it was switched out at the 78 // time of this event processing. 79 commit->trapSquash[tid] = true; 80} 81 82template <class Impl> 83const char * 84DefaultCommit<Impl>::TrapEvent::description() const 85{ 86 return "Trap"; 87} 88 89template <class Impl> 90DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 91 : cpu(_cpu), 92 squashCounter(0), 93 iewToCommitDelay(params->iewToCommitDelay), 94 commitToIEWDelay(params->commitToIEWDelay), 95 renameToROBDelay(params->renameToROBDelay), 96 fetchToCommitDelay(params->commitToFetchDelay), 97 renameWidth(params->renameWidth), 98 commitWidth(params->commitWidth), 99 numThreads(params->numThreads), 100 drainPending(false), 101 switchedOut(false), 102 trapLatency(params->trapLatency) 103{ 104 _status = Active; 105 _nextStatus = Inactive; 106 std::string policy = params->smtCommitPolicy; 107 108 //Convert string to lowercase 109 std::transform(policy.begin(), policy.end(), policy.begin(), 110 (int(*)(int)) tolower); 111 112 //Assign commit policy 113 if (policy == "aggressive"){ 114 commitPolicy = Aggressive; 115 116 DPRINTF(Commit,"Commit Policy set to Aggressive."); 117 } else if (policy == "roundrobin"){ 118 commitPolicy = RoundRobin; 119 120 //Set-Up Priority List 121 for (ThreadID tid = 0; tid < numThreads; tid++) { 122 priority_list.push_back(tid); 123 } 124 125 DPRINTF(Commit,"Commit Policy set to Round Robin."); 126 } else if (policy == "oldestready"){ 127 commitPolicy = OldestReady; 128 129 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 130 } else { 131 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 132 "RoundRobin,OldestReady}"); 133 } 134 135 for (ThreadID tid = 0; tid < numThreads; tid++) { 136 commitStatus[tid] = Idle; 137 changedROBNumEntries[tid] = false; 138 checkEmptyROB[tid] = false; 139 trapInFlight[tid] = false; 140 committedStores[tid] = false; 141 trapSquash[tid] = false; 142 tcSquash[tid] = false; 143 pc[tid].set(0); 144 } 145#if FULL_SYSTEM 146 interrupt = NoFault; 147#endif 148} 149 150template <class Impl> 151std::string 152DefaultCommit<Impl>::name() const 153{ 154 return cpu->name() + ".commit"; 155} 156 157template <class Impl> 158void 159DefaultCommit<Impl>::regStats() 160{ 161 using namespace Stats; 162 commitCommittedInsts 163 .name(name() + ".commitCommittedInsts") 164 .desc("The number of committed instructions") 165 .prereq(commitCommittedInsts); 166 commitSquashedInsts 167 .name(name() + ".commitSquashedInsts") 168 .desc("The number of squashed insts skipped by commit") 169 .prereq(commitSquashedInsts); 170 commitSquashEvents 171 .name(name() + ".commitSquashEvents") 172 .desc("The number of times commit is told to squash") 173 .prereq(commitSquashEvents); 174 commitNonSpecStalls 175 .name(name() + ".commitNonSpecStalls") 176 .desc("The number of times commit has been forced to stall to " 177 "communicate backwards") 178 .prereq(commitNonSpecStalls); 179 branchMispredicts 180 .name(name() + ".branchMispredicts") 181 .desc("The number of times a branch was mispredicted") 182 .prereq(branchMispredicts); 183 numCommittedDist 184 .init(0,commitWidth,1) 185 .name(name() + ".COM:committed_per_cycle") 186 .desc("Number of insts commited each cycle") 187 .flags(Stats::pdf) 188 ; 189 190 statComInst 191 .init(cpu->numThreads) 192 .name(name() + ".COM:count") 193 .desc("Number of instructions committed") 194 .flags(total) 195 ; 196 197 statComSwp 198 .init(cpu->numThreads) 199 .name(name() + ".COM:swp_count") 200 .desc("Number of s/w prefetches committed") 201 .flags(total) 202 ; 203 204 statComRefs 205 .init(cpu->numThreads) 206 .name(name() + ".COM:refs") 207 .desc("Number of memory references committed") 208 .flags(total) 209 ; 210 211 statComLoads 212 .init(cpu->numThreads) 213 .name(name() + ".COM:loads") 214 .desc("Number of loads committed") 215 .flags(total) 216 ; 217 218 statComMembars 219 .init(cpu->numThreads) 220 .name(name() + ".COM:membars") 221 .desc("Number of memory barriers committed") 222 .flags(total) 223 ; 224 225 statComBranches 226 .init(cpu->numThreads) 227 .name(name() + ".COM:branches") 228 .desc("Number of branches committed") 229 .flags(total) 230 ; 231 232 commitEligible 233 .init(cpu->numThreads) 234 .name(name() + ".COM:bw_limited") 235 .desc("number of insts not committed due to BW limits") 236 .flags(total) 237 ; 238 239 commitEligibleSamples 240 .name(name() + ".COM:bw_lim_events") 241 .desc("number cycles where commit BW limit reached") 242 ; 243} 244 245template <class Impl> 246void 247DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 248{ 249 thread = threads; 250} 251 252template <class Impl> 253void 254DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 255{ 256 timeBuffer = tb_ptr; 257 258 // Setup wire to send information back to IEW. 259 toIEW = timeBuffer->getWire(0); 260 261 // Setup wire to read data from IEW (for the ROB). 262 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 263} 264 265template <class Impl> 266void 267DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 268{ 269 fetchQueue = fq_ptr; 270 271 // Setup wire to get instructions from rename (for the ROB). 272 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 273} 274 275template <class Impl> 276void 277DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 278{ 279 renameQueue = rq_ptr; 280 281 // Setup wire to get instructions from rename (for the ROB). 282 fromRename = renameQueue->getWire(-renameToROBDelay); 283} 284 285template <class Impl> 286void 287DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 288{ 289 iewQueue = iq_ptr; 290 291 // Setup wire to get instructions from IEW. 292 fromIEW = iewQueue->getWire(-iewToCommitDelay); 293} 294 295template <class Impl> 296void 297DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 298{ 299 iewStage = iew_stage; 300} 301 302template<class Impl> 303void 304DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 305{ 306 activeThreads = at_ptr; 307} 308 309template <class Impl> 310void 311DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 312{ 313 for (ThreadID tid = 0; tid < numThreads; tid++) 314 renameMap[tid] = &rm_ptr[tid]; 315} 316 317template <class Impl> 318void 319DefaultCommit<Impl>::setROB(ROB *rob_ptr) 320{ 321 rob = rob_ptr; 322} 323 324template <class Impl> 325void 326DefaultCommit<Impl>::initStage() 327{ 328 rob->setActiveThreads(activeThreads); 329 rob->resetEntries(); 330 331 // Broadcast the number of free entries. 332 for (ThreadID tid = 0; tid < numThreads; tid++) { 333 toIEW->commitInfo[tid].usedROB = true; 334 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 335 toIEW->commitInfo[tid].emptyROB = true; 336 } 337 338 // Commit must broadcast the number of free entries it has at the 339 // start of the simulation, so it starts as active. 340 cpu->activateStage(O3CPU::CommitIdx); 341 342 cpu->activityThisCycle(); 343 trapLatency = cpu->ticks(trapLatency); 344} 345 346template <class Impl> 347bool 348DefaultCommit<Impl>::drain() 349{ 350 drainPending = true; 351 352 return false; 353} 354 355template <class Impl> 356void 357DefaultCommit<Impl>::switchOut() 358{ 359 switchedOut = true; 360 drainPending = false; 361 rob->switchOut(); 362} 363 364template <class Impl> 365void 366DefaultCommit<Impl>::resume() 367{ 368 drainPending = false; 369} 370 371template <class Impl> 372void 373DefaultCommit<Impl>::takeOverFrom() 374{ 375 switchedOut = false; 376 _status = Active; 377 _nextStatus = Inactive; 378 for (ThreadID tid = 0; tid < numThreads; tid++) { 379 commitStatus[tid] = Idle; 380 changedROBNumEntries[tid] = false; 381 trapSquash[tid] = false; 382 tcSquash[tid] = false; 383 } 384 squashCounter = 0; 385 rob->takeOverFrom(); 386} 387 388template <class Impl> 389void 390DefaultCommit<Impl>::updateStatus() 391{ 392 // reset ROB changed variable 393 list<ThreadID>::iterator threads = activeThreads->begin(); 394 list<ThreadID>::iterator end = activeThreads->end(); 395 396 while (threads != end) { 397 ThreadID tid = *threads++; 398 399 changedROBNumEntries[tid] = false; 400 401 // Also check if any of the threads has a trap pending 402 if (commitStatus[tid] == TrapPending || 403 commitStatus[tid] == FetchTrapPending) { 404 _nextStatus = Active; 405 } 406 } 407 408 if (_nextStatus == Inactive && _status == Active) { 409 DPRINTF(Activity, "Deactivating stage.\n"); 410 cpu->deactivateStage(O3CPU::CommitIdx); 411 } else if (_nextStatus == Active && _status == Inactive) { 412 DPRINTF(Activity, "Activating stage.\n"); 413 cpu->activateStage(O3CPU::CommitIdx); 414 } 415 416 _status = _nextStatus; 417} 418 419template <class Impl> 420void 421DefaultCommit<Impl>::setNextStatus() 422{ 423 int squashes = 0; 424 425 list<ThreadID>::iterator threads = activeThreads->begin(); 426 list<ThreadID>::iterator end = activeThreads->end(); 427 428 while (threads != end) { 429 ThreadID tid = *threads++; 430 431 if (commitStatus[tid] == ROBSquashing) { 432 squashes++; 433 } 434 } 435 436 squashCounter = squashes; 437 438 // If commit is currently squashing, then it will have activity for the 439 // next cycle. Set its next status as active. 440 if (squashCounter) { 441 _nextStatus = Active; 442 } 443} 444 445template <class Impl> 446bool 447DefaultCommit<Impl>::changedROBEntries() 448{ 449 list<ThreadID>::iterator threads = activeThreads->begin(); 450 list<ThreadID>::iterator end = activeThreads->end(); 451 452 while (threads != end) { 453 ThreadID tid = *threads++; 454 455 if (changedROBNumEntries[tid]) { 456 return true; 457 } 458 } 459 460 return false; 461} 462 463template <class Impl> 464size_t 465DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 466{ 467 return rob->numFreeEntries(tid); 468} 469 470template <class Impl> 471void 472DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 473{ 474 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 475 476 TrapEvent *trap = new TrapEvent(this, tid); 477 478 cpu->schedule(trap, curTick + trapLatency); 479 trapInFlight[tid] = true; 480} 481 482template <class Impl> 483void 484DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 485{ 486 assert(!trapInFlight[tid]); 487 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 488 489 tcSquash[tid] = true; 490} 491 492template <class Impl> 493void 494DefaultCommit<Impl>::squashAll(ThreadID tid) 495{ 496 // If we want to include the squashing instruction in the squash, 497 // then use one older sequence number. 498 // Hopefully this doesn't mess things up. Basically I want to squash 499 // all instructions of this thread. 500 InstSeqNum squashed_inst = rob->isEmpty() ? 501 0 : rob->readHeadInst(tid)->seqNum - 1; 502 503 // All younger instructions will be squashed. Set the sequence 504 // number as the youngest instruction in the ROB (0 in this case. 505 // Hopefully nothing breaks.) 506 youngestSeqNum[tid] = 0; 507 508 rob->squash(squashed_inst, tid); 509 changedROBNumEntries[tid] = true; 510 511 // Send back the sequence number of the squashed instruction. 512 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 513 514 // Send back the squash signal to tell stages that they should 515 // squash. 516 toIEW->commitInfo[tid].squash = true; 517 518 // Send back the rob squashing signal so other stages know that 519 // the ROB is in the process of squashing. 520 toIEW->commitInfo[tid].robSquashing = true; 521 522 toIEW->commitInfo[tid].branchMispredict = false; 523 524 toIEW->commitInfo[tid].pc = pc[tid]; 525} 526 527template <class Impl> 528void 529DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 530{ 531 squashAll(tid); 532 533 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 534 535 thread[tid]->trapPending = false; 536 thread[tid]->inSyscall = false; 537 trapInFlight[tid] = false; 538 539 trapSquash[tid] = false; 540 541 commitStatus[tid] = ROBSquashing; 542 cpu->activityThisCycle(); 543} 544 545template <class Impl> 546void 547DefaultCommit<Impl>::squashFromTC(ThreadID tid) 548{ 549 squashAll(tid); 550 551 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 552 553 thread[tid]->inSyscall = false; 554 assert(!thread[tid]->trapPending); 555 556 commitStatus[tid] = ROBSquashing; 557 cpu->activityThisCycle(); 558 559 tcSquash[tid] = false; 560} 561 562template <class Impl> 563void 564DefaultCommit<Impl>::tick() 565{ 566 wroteToTimeBuffer = false; 567 _nextStatus = Inactive; 568 569 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 570 cpu->signalDrained(); 571 drainPending = false; 572 return; 573 } 574 575 if (activeThreads->empty()) 576 return; 577 578 list<ThreadID>::iterator threads = activeThreads->begin(); 579 list<ThreadID>::iterator end = activeThreads->end(); 580 581 // Check if any of the threads are done squashing. Change the 582 // status if they are done. 583 while (threads != end) { 584 ThreadID tid = *threads++; 585 586 // Clear the bit saying if the thread has committed stores 587 // this cycle. 588 committedStores[tid] = false; 589 590 if (commitStatus[tid] == ROBSquashing) { 591 592 if (rob->isDoneSquashing(tid)) { 593 commitStatus[tid] = Running; 594 } else { 595 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 596 " insts this cycle.\n", tid); 597 rob->doSquash(tid); 598 toIEW->commitInfo[tid].robSquashing = true; 599 wroteToTimeBuffer = true; 600 } 601 } 602 } 603 604 commit(); 605 606 markCompletedInsts(); 607 608 threads = activeThreads->begin(); 609 610 while (threads != end) { 611 ThreadID tid = *threads++; 612 613 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 614 // The ROB has more instructions it can commit. Its next status 615 // will be active. 616 _nextStatus = Active; 617 618 DynInstPtr inst = rob->readHeadInst(tid); 619 620 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 621 " ROB and ready to commit\n", 622 tid, inst->seqNum, inst->pcState()); 623 624 } else if (!rob->isEmpty(tid)) { 625 DynInstPtr inst = rob->readHeadInst(tid); 626 627 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 628 "%s is head of ROB and not ready\n", 629 tid, inst->seqNum, inst->pcState()); 630 } 631 632 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 633 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 634 } 635 636 637 if (wroteToTimeBuffer) { 638 DPRINTF(Activity, "Activity This Cycle.\n"); 639 cpu->activityThisCycle(); 640 } 641 642 updateStatus(); 643} 644 645#if FULL_SYSTEM 646template <class Impl> 647void 648DefaultCommit<Impl>::handleInterrupt() 649{ 650 if (interrupt != NoFault) { 651 // Wait until the ROB is empty and all stores have drained in 652 // order to enter the interrupt. 653 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 654 // Squash or record that I need to squash this cycle if 655 // an interrupt needed to be handled. 656 DPRINTF(Commit, "Interrupt detected.\n"); 657 658 // Clear the interrupt now that it's going to be handled 659 toIEW->commitInfo[0].clearInterrupt = true; 660 661 assert(!thread[0]->inSyscall); 662 thread[0]->inSyscall = true; 663 664 // CPU will handle interrupt. 665 cpu->processInterrupts(interrupt); 666 667 thread[0]->inSyscall = false; 668 669 commitStatus[0] = TrapPending; 670 671 // Generate trap squash event. 672 generateTrapEvent(0); 673 674 interrupt = NoFault; 675 } else { 676 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 677 } 678 } else if (commitStatus[0] != TrapPending && 679 cpu->checkInterrupts(cpu->tcBase(0)) && 680 !trapSquash[0] && 681 !tcSquash[0]) { 682 // Process interrupts if interrupts are enabled, not in PAL 683 // mode, and no other traps or external squashes are currently 684 // pending. 685 // @todo: Allow other threads to handle interrupts. 686 687 // Get any interrupt that happened 688 interrupt = cpu->getInterrupts(); 689 690 if (interrupt != NoFault) { 691 // Tell fetch that there is an interrupt pending. This 692 // will make fetch wait until it sees a non PAL-mode PC, 693 // at which point it stops fetching instructions. 694 toIEW->commitInfo[0].interruptPending = true; 695 } 696 } 697} 698#endif // FULL_SYSTEM 699 700template <class Impl> 701void 702DefaultCommit<Impl>::commit() 703{ 704 705#if FULL_SYSTEM 706 // Check for any interrupt, and start processing it. Or if we 707 // have an outstanding interrupt and are at a point when it is 708 // valid to take an interrupt, process it. 709 if (cpu->checkInterrupts(cpu->tcBase(0))) { 710 handleInterrupt(); 711 } 712#endif // FULL_SYSTEM 713 714 //////////////////////////////////// 715 // Check for any possible squashes, handle them first 716 //////////////////////////////////// 717 list<ThreadID>::iterator threads = activeThreads->begin(); 718 list<ThreadID>::iterator end = activeThreads->end(); 719 720 while (threads != end) { 721 ThreadID tid = *threads++; 722 723 // Not sure which one takes priority. I think if we have 724 // both, that's a bad sign. 725 if (trapSquash[tid] == true) { 726 assert(!tcSquash[tid]); 727 squashFromTrap(tid); 728 } else if (tcSquash[tid] == true) { 729 assert(commitStatus[tid] != TrapPending); 730 squashFromTC(tid); 731 } 732 733 // Squashed sequence number must be older than youngest valid 734 // instruction in the ROB. This prevents squashes from younger 735 // instructions overriding squashes from older instructions. 736 if (fromIEW->squash[tid] && 737 commitStatus[tid] != TrapPending && 738 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 739 740 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 741 tid, 742 fromIEW->mispredPC[tid], 743 fromIEW->squashedSeqNum[tid]); 744 745 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 746 tid, 747 fromIEW->pc[tid].nextInstAddr()); 748 749 commitStatus[tid] = ROBSquashing; 750 751 // If we want to include the squashing instruction in the squash, 752 // then use one older sequence number. 753 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 754 755 if (fromIEW->includeSquashInst[tid] == true) { 756 squashed_inst--; 757 } 758 759 // All younger instructions will be squashed. Set the sequence 760 // number as the youngest instruction in the ROB. 761 youngestSeqNum[tid] = squashed_inst; 762 763 rob->squash(squashed_inst, tid); 764 changedROBNumEntries[tid] = true; 765 766 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 767 768 toIEW->commitInfo[tid].squash = true; 769 770 // Send back the rob squashing signal so other stages know that 771 // the ROB is in the process of squashing. 772 toIEW->commitInfo[tid].robSquashing = true; 773 774 toIEW->commitInfo[tid].branchMispredict = 775 fromIEW->branchMispredict[tid]; 776 777 toIEW->commitInfo[tid].branchTaken = 778 fromIEW->branchTaken[tid]; 779 780 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 781 782 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 783 784 if (toIEW->commitInfo[tid].branchMispredict) { 785 ++branchMispredicts; 786 } 787 } 788 789 } 790 791 setNextStatus(); 792 793 if (squashCounter != numThreads) { 794 // If we're not currently squashing, then get instructions. 795 getInsts(); 796 797 // Try to commit any instructions. 798 commitInsts(); 799 } 800 801 //Check for any activity 802 threads = activeThreads->begin(); 803 804 while (threads != end) { 805 ThreadID tid = *threads++; 806 807 if (changedROBNumEntries[tid]) { 808 toIEW->commitInfo[tid].usedROB = true; 809 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 810 811 wroteToTimeBuffer = true; 812 changedROBNumEntries[tid] = false; 813 if (rob->isEmpty(tid)) 814 checkEmptyROB[tid] = true; 815 } 816 817 // ROB is only considered "empty" for previous stages if: a) 818 // ROB is empty, b) there are no outstanding stores, c) IEW 819 // stage has received any information regarding stores that 820 // committed. 821 // c) is checked by making sure to not consider the ROB empty 822 // on the same cycle as when stores have been committed. 823 // @todo: Make this handle multi-cycle communication between 824 // commit and IEW. 825 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 826 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 827 checkEmptyROB[tid] = false; 828 toIEW->commitInfo[tid].usedROB = true; 829 toIEW->commitInfo[tid].emptyROB = true; 830 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 831 wroteToTimeBuffer = true; 832 } 833 834 } 835} 836 837template <class Impl> 838void 839DefaultCommit<Impl>::commitInsts() 840{ 841 //////////////////////////////////// 842 // Handle commit 843 // Note that commit will be handled prior to putting new 844 // instructions in the ROB so that the ROB only tries to commit 845 // instructions it has in this current cycle, and not instructions 846 // it is writing in during this cycle. Can't commit and squash 847 // things at the same time... 848 //////////////////////////////////// 849 850 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 851 852 unsigned num_committed = 0; 853 854 DynInstPtr head_inst; 855 856 // Commit as many instructions as possible until the commit bandwidth 857 // limit is reached, or it becomes impossible to commit any more. 858 while (num_committed < commitWidth) { 859 int commit_thread = getCommittingThread(); 860 861 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 862 break; 863 864 head_inst = rob->readHeadInst(commit_thread); 865 866 ThreadID tid = head_inst->threadNumber; 867 868 assert(tid == commit_thread); 869 870 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 871 head_inst->seqNum, tid); 872 873 // If the head instruction is squashed, it is ready to retire 874 // (be removed from the ROB) at any time. 875 if (head_inst->isSquashed()) { 876 877 DPRINTF(Commit, "Retiring squashed instruction from " 878 "ROB.\n"); 879 880 rob->retireHead(commit_thread); 881 882 ++commitSquashedInsts; 883 884 // Record that the number of ROB entries has changed. 885 changedROBNumEntries[tid] = true; 886 } else { 887 pc[tid] = head_inst->pcState(); 888 889 // Increment the total number of non-speculative instructions 890 // executed. 891 // Hack for now: it really shouldn't happen until after the 892 // commit is deemed to be successful, but this count is needed 893 // for syscalls. 894 thread[tid]->funcExeInst++; 895 896 // Try to commit the head instruction. 897 bool commit_success = commitHead(head_inst, num_committed); 898 899 if (commit_success) { 900 ++num_committed; 901 902 changedROBNumEntries[tid] = true; 903 904 // Set the doneSeqNum to the youngest committed instruction. 905 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 906 907 ++commitCommittedInsts; 908 909 // To match the old model, don't count nops and instruction 910 // prefetches towards the total commit count. 911 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 912 cpu->instDone(tid); 913 } 914 915 // Updates misc. registers. 916 head_inst->updateMiscRegs(); 917 918 TheISA::advancePC(pc[tid], head_inst->staticInst); 919 920 int count = 0; 921 Addr oldpc; 922 // Debug statement. Checks to make sure we're not 923 // currently updating state while handling PC events. 924 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 925 do { 926 oldpc = pc[tid].instAddr(); 927 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 928 count++; 929 } while (oldpc != pc[tid].instAddr()); 930 if (count > 1) { 931 DPRINTF(Commit, 932 "PC skip function event, stopping commit\n"); 933 break; 934 } 935 } else { 936 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 937 "[tid:%i] [sn:%i].\n", 938 head_inst->pcState(), tid ,head_inst->seqNum); 939 break; 940 } 941 } 942 } 943 944 DPRINTF(CommitRate, "%i\n", num_committed); 945 numCommittedDist.sample(num_committed); 946 947 if (num_committed == commitWidth) { 948 commitEligibleSamples++; 949 } 950} 951 952template <class Impl> 953bool 954DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 955{ 956 assert(head_inst); 957 958 ThreadID tid = head_inst->threadNumber; 959 960 // If the instruction is not executed yet, then it will need extra 961 // handling. Signal backwards that it should be executed. 962 if (!head_inst->isExecuted()) { 963 // Keep this number correct. We have not yet actually executed 964 // and committed this instruction. 965 thread[tid]->funcExeInst--; 966 967 if (head_inst->isNonSpeculative() || 968 head_inst->isStoreConditional() || 969 head_inst->isMemBarrier() || 970 head_inst->isWriteBarrier()) { 971 972 DPRINTF(Commit, "Encountered a barrier or non-speculative " 973 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 974 head_inst->seqNum, head_inst->pcState()); 975 976 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 977 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 978 return false; 979 } 980 981 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 982 983 // Change the instruction so it won't try to commit again until 984 // it is executed. 985 head_inst->clearCanCommit(); 986 987 ++commitNonSpecStalls; 988 989 return false; 990 } else if (head_inst->isLoad()) { 991 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 992 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 993 return false; 994 } 995 996 assert(head_inst->uncacheable()); 997 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 998 head_inst->seqNum, head_inst->pcState()); 999 1000 // Send back the non-speculative instruction's sequence 1001 // number. Tell the lsq to re-execute the load. 1002 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1003 toIEW->commitInfo[tid].uncached = true; 1004 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1005 1006 head_inst->clearCanCommit(); 1007 1008 return false; 1009 } else { 1010 panic("Trying to commit un-executed instruction " 1011 "of unknown type!\n"); 1012 } 1013 } 1014 1015 if (head_inst->isThreadSync()) { 1016 // Not handled for now. 1017 panic("Thread sync instructions are not handled yet.\n"); 1018 } 1019 1020 // Check if the instruction caused a fault. If so, trap. 1021 Fault inst_fault = head_inst->getFault(); 1022 1023 // Stores mark themselves as completed. 1024 if (!head_inst->isStore() && inst_fault == NoFault) { 1025 head_inst->setCompleted(); 1026 } 1027 1028#if USE_CHECKER 1029 // Use checker prior to updating anything due to traps or PC 1030 // based events. 1031 if (cpu->checker) { 1032 cpu->checker->verify(head_inst); 1033 } 1034#endif 1035 1036 if (inst_fault != NoFault) { 1037 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1038 head_inst->seqNum, head_inst->pcState()); 1039 1040 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1041 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1042 return false; 1043 } 1044 1045 head_inst->setCompleted(); 1046 1047#if USE_CHECKER 1048 if (cpu->checker && head_inst->isStore()) { 1049 cpu->checker->verify(head_inst); 1050 } 1051#endif 1052 1053 assert(!thread[tid]->inSyscall); 1054 1055 // Mark that we're in state update mode so that the trap's 1056 // execution doesn't generate extra squashes. 1057 thread[tid]->inSyscall = true; 1058 1059 // Execute the trap. Although it's slightly unrealistic in 1060 // terms of timing (as it doesn't wait for the full timing of 1061 // the trap event to complete before updating state), it's 1062 // needed to update the state as soon as possible. This 1063 // prevents external agents from changing any specific state 1064 // that the trap need. 1065 cpu->trap(inst_fault, tid, head_inst->staticInst); 1066 1067 // Exit state update mode to avoid accidental updating. 1068 thread[tid]->inSyscall = false; 1069 1070 commitStatus[tid] = TrapPending; 1071 1072 if (head_inst->traceData) { 1073 if (DTRACE(ExecFaulting)) { 1074 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1075 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1076 head_inst->traceData->dump(); 1077 } 1078 delete head_inst->traceData; 1079 head_inst->traceData = NULL; 1080 } 1081 1082 // Generate trap squash event. 1083 generateTrapEvent(tid); 1084 return false; 1085 } 1086 1087 updateComInstStats(head_inst); 1088 1089#if FULL_SYSTEM 1090 if (thread[tid]->profile) { 1091 thread[tid]->profilePC = head_inst->instAddr(); 1092 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1093 head_inst->staticInst); 1094 1095 if (node) 1096 thread[tid]->profileNode = node; 1097 } 1098 if (CPA::available()) { 1099 if (head_inst->isControl()) { 1100 ThreadContext *tc = thread[tid]->getTC(); 1101 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1102 } 1103 } 1104#endif 1105 1106 if (head_inst->traceData) { 1107 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1108 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1109 head_inst->traceData->dump(); 1110 delete head_inst->traceData; 1111 head_inst->traceData = NULL; 1112 } 1113 1114 // Update the commit rename map 1115 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1116 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1117 head_inst->renamedDestRegIdx(i)); 1118 } 1119 1120 if (head_inst->isCopy()) 1121 panic("Should not commit any copy instructions!"); 1122 1123 // Finally clear the head ROB entry. 1124 rob->retireHead(tid); 1125 1126 // If this was a store, record it for this cycle. 1127 if (head_inst->isStore()) 1128 committedStores[tid] = true; 1129 1130 // Return true to indicate that we have committed an instruction. 1131 return true; 1132} 1133 1134template <class Impl> 1135void 1136DefaultCommit<Impl>::getInsts() 1137{ 1138 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1139 1140 // Read any renamed instructions and place them into the ROB. 1141 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1142 1143 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1144 DynInstPtr inst; 1145 1146 inst = fromRename->insts[inst_num]; 1147 ThreadID tid = inst->threadNumber; 1148 1149 if (!inst->isSquashed() && 1150 commitStatus[tid] != ROBSquashing && 1151 commitStatus[tid] != TrapPending) { 1152 changedROBNumEntries[tid] = true; 1153 1154 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1155 inst->pcState(), inst->seqNum, tid); 1156 1157 rob->insertInst(inst); 1158 1159 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1160 1161 youngestSeqNum[tid] = inst->seqNum; 1162 } else { 1163 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1164 "squashed, skipping.\n", 1165 inst->pcState(), inst->seqNum, tid); 1166 } 1167 } 1168} 1169 1170template <class Impl> 1171void 1172DefaultCommit<Impl>::skidInsert() 1173{ 1174 DPRINTF(Commit, "Attempting to any instructions from rename into " 1175 "skidBuffer.\n"); 1176 1177 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1178 DynInstPtr inst = fromRename->insts[inst_num]; 1179 1180 if (!inst->isSquashed()) { 1181 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1182 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1183 inst->threadNumber); 1184 skidBuffer.push(inst); 1185 } else { 1186 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1187 "squashed, skipping.\n", 1188 inst->pcState(), inst->seqNum, inst->threadNumber); 1189 } 1190 } 1191} 1192 1193template <class Impl> 1194void 1195DefaultCommit<Impl>::markCompletedInsts() 1196{ 1197 // Grab completed insts out of the IEW instruction queue, and mark 1198 // instructions completed within the ROB. 1199 for (int inst_num = 0; 1200 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1201 ++inst_num) 1202 { 1203 if (!fromIEW->insts[inst_num]->isSquashed()) { 1204 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1205 "within ROB.\n", 1206 fromIEW->insts[inst_num]->threadNumber, 1207 fromIEW->insts[inst_num]->pcState(), 1208 fromIEW->insts[inst_num]->seqNum); 1209 1210 // Mark the instruction as ready to commit. 1211 fromIEW->insts[inst_num]->setCanCommit(); 1212 } 1213 } 1214} 1215 1216template <class Impl> 1217bool 1218DefaultCommit<Impl>::robDoneSquashing() 1219{ 1220 list<ThreadID>::iterator threads = activeThreads->begin(); 1221 list<ThreadID>::iterator end = activeThreads->end(); 1222 1223 while (threads != end) { 1224 ThreadID tid = *threads++; 1225 1226 if (!rob->isDoneSquashing(tid)) 1227 return false; 1228 } 1229 1230 return true; 1231} 1232 1233template <class Impl> 1234void 1235DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1236{ 1237 ThreadID tid = inst->threadNumber; 1238 1239 // 1240 // Pick off the software prefetches 1241 // 1242#ifdef TARGET_ALPHA 1243 if (inst->isDataPrefetch()) { 1244 statComSwp[tid]++; 1245 } else { 1246 statComInst[tid]++; 1247 } 1248#else 1249 statComInst[tid]++; 1250#endif 1251 1252 // 1253 // Control Instructions 1254 // 1255 if (inst->isControl()) 1256 statComBranches[tid]++; 1257 1258 // 1259 // Memory references 1260 // 1261 if (inst->isMemRef()) { 1262 statComRefs[tid]++; 1263 1264 if (inst->isLoad()) { 1265 statComLoads[tid]++; 1266 } 1267 } 1268 1269 if (inst->isMemBarrier()) { 1270 statComMembars[tid]++; 1271 } 1272} 1273 1274//////////////////////////////////////// 1275// // 1276// SMT COMMIT POLICY MAINTAINED HERE // 1277// // 1278//////////////////////////////////////// 1279template <class Impl> 1280ThreadID 1281DefaultCommit<Impl>::getCommittingThread() 1282{ 1283 if (numThreads > 1) { 1284 switch (commitPolicy) { 1285 1286 case Aggressive: 1287 //If Policy is Aggressive, commit will call 1288 //this function multiple times per 1289 //cycle 1290 return oldestReady(); 1291 1292 case RoundRobin: 1293 return roundRobin(); 1294 1295 case OldestReady: 1296 return oldestReady(); 1297 1298 default: 1299 return InvalidThreadID; 1300 } 1301 } else { 1302 assert(!activeThreads->empty()); 1303 ThreadID tid = activeThreads->front(); 1304 1305 if (commitStatus[tid] == Running || 1306 commitStatus[tid] == Idle || 1307 commitStatus[tid] == FetchTrapPending) { 1308 return tid; 1309 } else { 1310 return InvalidThreadID; 1311 } 1312 } 1313} 1314 1315template<class Impl> 1316ThreadID 1317DefaultCommit<Impl>::roundRobin() 1318{ 1319 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1320 list<ThreadID>::iterator end = priority_list.end(); 1321 1322 while (pri_iter != end) { 1323 ThreadID tid = *pri_iter; 1324 1325 if (commitStatus[tid] == Running || 1326 commitStatus[tid] == Idle || 1327 commitStatus[tid] == FetchTrapPending) { 1328 1329 if (rob->isHeadReady(tid)) { 1330 priority_list.erase(pri_iter); 1331 priority_list.push_back(tid); 1332 1333 return tid; 1334 } 1335 } 1336 1337 pri_iter++; 1338 } 1339 1340 return InvalidThreadID; 1341} 1342 1343template<class Impl> 1344ThreadID 1345DefaultCommit<Impl>::oldestReady() 1346{ 1347 unsigned oldest = 0; 1348 bool first = true; 1349 1350 list<ThreadID>::iterator threads = activeThreads->begin(); 1351 list<ThreadID>::iterator end = activeThreads->end(); 1352 1353 while (threads != end) { 1354 ThreadID tid = *threads++; 1355 1356 if (!rob->isEmpty(tid) && 1357 (commitStatus[tid] == Running || 1358 commitStatus[tid] == Idle || 1359 commitStatus[tid] == FetchTrapPending)) { 1360 1361 if (rob->isHeadReady(tid)) { 1362 1363 DynInstPtr head_inst = rob->readHeadInst(tid); 1364 1365 if (first) { 1366 oldest = tid; 1367 first = false; 1368 } else if (head_inst->seqNum < oldest) { 1369 oldest = tid; 1370 } 1371 } 1372 } 1373 } 1374 1375 if (!first) { 1376 return oldest; 1377 } else { 1378 return InvalidThreadID; 1379 } 1380} 1381