commit_impl.hh revision 4318:eb4241362a80 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51                                          unsigned _tid)
52    : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54    this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61    // This will get reset by commit if it was switched out at the
62    // time of this event processing.
63    commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70    return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75    : squashCounter(0),
76      iewToCommitDelay(params->iewToCommitDelay),
77      commitToIEWDelay(params->commitToIEWDelay),
78      renameToROBDelay(params->renameToROBDelay),
79      fetchToCommitDelay(params->commitToFetchDelay),
80      renameWidth(params->renameWidth),
81      commitWidth(params->commitWidth),
82      numThreads(params->numberOfThreads),
83      drainPending(false),
84      switchedOut(false),
85      trapLatency(params->trapLatency)
86{
87    _status = Active;
88    _nextStatus = Inactive;
89    std::string policy = params->smtCommitPolicy;
90
91    //Convert string to lowercase
92    std::transform(policy.begin(), policy.end(), policy.begin(),
93                   (int(*)(int)) tolower);
94
95    //Assign commit policy
96    if (policy == "aggressive"){
97        commitPolicy = Aggressive;
98
99//        DPRINTF(Commit,"Commit Policy set to Aggressive.");
100    } else if (policy == "roundrobin"){
101        commitPolicy = RoundRobin;
102
103        //Set-Up Priority List
104        for (int tid=0; tid < numThreads; tid++) {
105            priority_list.push_back(tid);
106        }
107
108//        DPRINTF(Commit,"Commit Policy set to Round Robin.");
109    } else if (policy == "oldestready"){
110        commitPolicy = OldestReady;
111
112//        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113    } else {
114        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115               "RoundRobin,OldestReady}");
116    }
117
118    for (int i=0; i < numThreads; i++) {
119        commitStatus[i] = Idle;
120        changedROBNumEntries[i] = false;
121        checkEmptyROB[i] = false;
122        trapInFlight[i] = false;
123        committedStores[i] = false;
124        trapSquash[i] = false;
125        tcSquash[i] = false;
126        PC[i] = nextPC[i] = nextNPC[i] = 0;
127    }
128#if FULL_SYSTEM
129    interrupt = NoFault;
130#endif
131}
132
133template <class Impl>
134std::string
135DefaultCommit<Impl>::name() const
136{
137    return cpu->name() + ".commit";
138}
139
140template <class Impl>
141void
142DefaultCommit<Impl>::regStats()
143{
144    using namespace Stats;
145    commitCommittedInsts
146        .name(name() + ".commitCommittedInsts")
147        .desc("The number of committed instructions")
148        .prereq(commitCommittedInsts);
149    commitSquashedInsts
150        .name(name() + ".commitSquashedInsts")
151        .desc("The number of squashed insts skipped by commit")
152        .prereq(commitSquashedInsts);
153    commitSquashEvents
154        .name(name() + ".commitSquashEvents")
155        .desc("The number of times commit is told to squash")
156        .prereq(commitSquashEvents);
157    commitNonSpecStalls
158        .name(name() + ".commitNonSpecStalls")
159        .desc("The number of times commit has been forced to stall to "
160              "communicate backwards")
161        .prereq(commitNonSpecStalls);
162    branchMispredicts
163        .name(name() + ".branchMispredicts")
164        .desc("The number of times a branch was mispredicted")
165        .prereq(branchMispredicts);
166    numCommittedDist
167        .init(0,commitWidth,1)
168        .name(name() + ".COM:committed_per_cycle")
169        .desc("Number of insts commited each cycle")
170        .flags(Stats::pdf)
171        ;
172
173    statComInst
174        .init(cpu->number_of_threads)
175        .name(name() + ".COM:count")
176        .desc("Number of instructions committed")
177        .flags(total)
178        ;
179
180    statComSwp
181        .init(cpu->number_of_threads)
182        .name(name() + ".COM:swp_count")
183        .desc("Number of s/w prefetches committed")
184        .flags(total)
185        ;
186
187    statComRefs
188        .init(cpu->number_of_threads)
189        .name(name() +  ".COM:refs")
190        .desc("Number of memory references committed")
191        .flags(total)
192        ;
193
194    statComLoads
195        .init(cpu->number_of_threads)
196        .name(name() +  ".COM:loads")
197        .desc("Number of loads committed")
198        .flags(total)
199        ;
200
201    statComMembars
202        .init(cpu->number_of_threads)
203        .name(name() +  ".COM:membars")
204        .desc("Number of memory barriers committed")
205        .flags(total)
206        ;
207
208    statComBranches
209        .init(cpu->number_of_threads)
210        .name(name() + ".COM:branches")
211        .desc("Number of branches committed")
212        .flags(total)
213        ;
214
215    commitEligible
216        .init(cpu->number_of_threads)
217        .name(name() + ".COM:bw_limited")
218        .desc("number of insts not committed due to BW limits")
219        .flags(total)
220        ;
221
222    commitEligibleSamples
223        .name(name() + ".COM:bw_lim_events")
224        .desc("number cycles where commit BW limit reached")
225        ;
226}
227
228template <class Impl>
229void
230DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
231{
232    cpu = cpu_ptr;
233    DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
234
235    // Commit must broadcast the number of free entries it has at the start of
236    // the simulation, so it starts as active.
237    cpu->activateStage(O3CPU::CommitIdx);
238
239    trapLatency = cpu->cycles(trapLatency);
240}
241
242template <class Impl>
243void
244DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
245{
246    thread = threads;
247}
248
249template <class Impl>
250void
251DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
252{
253    timeBuffer = tb_ptr;
254
255    // Setup wire to send information back to IEW.
256    toIEW = timeBuffer->getWire(0);
257
258    // Setup wire to read data from IEW (for the ROB).
259    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
260}
261
262template <class Impl>
263void
264DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
265{
266    fetchQueue = fq_ptr;
267
268    // Setup wire to get instructions from rename (for the ROB).
269    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
270}
271
272template <class Impl>
273void
274DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
275{
276    renameQueue = rq_ptr;
277
278    // Setup wire to get instructions from rename (for the ROB).
279    fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286    iewQueue = iq_ptr;
287
288    // Setup wire to get instructions from IEW.
289    fromIEW = iewQueue->getWire(-iewToCommitDelay);
290}
291
292template <class Impl>
293void
294DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
295{
296    iewStage = iew_stage;
297}
298
299template<class Impl>
300void
301DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
302{
303    activeThreads = at_ptr;
304}
305
306template <class Impl>
307void
308DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
309{
310    for (int i=0; i < numThreads; i++) {
311        renameMap[i] = &rm_ptr[i];
312    }
313}
314
315template <class Impl>
316void
317DefaultCommit<Impl>::setROB(ROB *rob_ptr)
318{
319    rob = rob_ptr;
320}
321
322template <class Impl>
323void
324DefaultCommit<Impl>::initStage()
325{
326    rob->setActiveThreads(activeThreads);
327    rob->resetEntries();
328
329    // Broadcast the number of free entries.
330    for (int i=0; i < numThreads; i++) {
331        toIEW->commitInfo[i].usedROB = true;
332        toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
333        toIEW->commitInfo[i].emptyROB = true;
334    }
335
336    cpu->activityThisCycle();
337}
338
339template <class Impl>
340bool
341DefaultCommit<Impl>::drain()
342{
343    drainPending = true;
344
345    return false;
346}
347
348template <class Impl>
349void
350DefaultCommit<Impl>::switchOut()
351{
352    switchedOut = true;
353    drainPending = false;
354    rob->switchOut();
355}
356
357template <class Impl>
358void
359DefaultCommit<Impl>::resume()
360{
361    drainPending = false;
362}
363
364template <class Impl>
365void
366DefaultCommit<Impl>::takeOverFrom()
367{
368    switchedOut = false;
369    _status = Active;
370    _nextStatus = Inactive;
371    for (int i=0; i < numThreads; i++) {
372        commitStatus[i] = Idle;
373        changedROBNumEntries[i] = false;
374        trapSquash[i] = false;
375        tcSquash[i] = false;
376    }
377    squashCounter = 0;
378    rob->takeOverFrom();
379}
380
381template <class Impl>
382void
383DefaultCommit<Impl>::updateStatus()
384{
385    // reset ROB changed variable
386    std::list<unsigned>::iterator threads = activeThreads->begin();
387    std::list<unsigned>::iterator end = activeThreads->end();
388
389    while (threads != end) {
390        unsigned tid = *threads++;
391
392        changedROBNumEntries[tid] = false;
393
394        // Also check if any of the threads has a trap pending
395        if (commitStatus[tid] == TrapPending ||
396            commitStatus[tid] == FetchTrapPending) {
397            _nextStatus = Active;
398        }
399    }
400
401    if (_nextStatus == Inactive && _status == Active) {
402        DPRINTF(Activity, "Deactivating stage.\n");
403        cpu->deactivateStage(O3CPU::CommitIdx);
404    } else if (_nextStatus == Active && _status == Inactive) {
405        DPRINTF(Activity, "Activating stage.\n");
406        cpu->activateStage(O3CPU::CommitIdx);
407    }
408
409    _status = _nextStatus;
410}
411
412template <class Impl>
413void
414DefaultCommit<Impl>::setNextStatus()
415{
416    int squashes = 0;
417
418    std::list<unsigned>::iterator threads = activeThreads->begin();
419    std::list<unsigned>::iterator end = activeThreads->end();
420
421    while (threads != end) {
422        unsigned tid = *threads++;
423
424        if (commitStatus[tid] == ROBSquashing) {
425            squashes++;
426        }
427    }
428
429    squashCounter = squashes;
430
431    // If commit is currently squashing, then it will have activity for the
432    // next cycle. Set its next status as active.
433    if (squashCounter) {
434        _nextStatus = Active;
435    }
436}
437
438template <class Impl>
439bool
440DefaultCommit<Impl>::changedROBEntries()
441{
442    std::list<unsigned>::iterator threads = activeThreads->begin();
443    std::list<unsigned>::iterator end = activeThreads->end();
444
445    while (threads != end) {
446        unsigned tid = *threads++;
447
448        if (changedROBNumEntries[tid]) {
449            return true;
450        }
451    }
452
453    return false;
454}
455
456template <class Impl>
457unsigned
458DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
459{
460    return rob->numFreeEntries(tid);
461}
462
463template <class Impl>
464void
465DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
466{
467    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
468
469    TrapEvent *trap = new TrapEvent(this, tid);
470
471    trap->schedule(curTick + trapLatency);
472    trapInFlight[tid] = true;
473}
474
475template <class Impl>
476void
477DefaultCommit<Impl>::generateTCEvent(unsigned tid)
478{
479    assert(!trapInFlight[tid]);
480    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
481
482    tcSquash[tid] = true;
483}
484
485template <class Impl>
486void
487DefaultCommit<Impl>::squashAll(unsigned tid)
488{
489    // If we want to include the squashing instruction in the squash,
490    // then use one older sequence number.
491    // Hopefully this doesn't mess things up.  Basically I want to squash
492    // all instructions of this thread.
493    InstSeqNum squashed_inst = rob->isEmpty() ?
494        0 : rob->readHeadInst(tid)->seqNum - 1;
495
496    // All younger instructions will be squashed. Set the sequence
497    // number as the youngest instruction in the ROB (0 in this case.
498    // Hopefully nothing breaks.)
499    youngestSeqNum[tid] = 0;
500
501    rob->squash(squashed_inst, tid);
502    changedROBNumEntries[tid] = true;
503
504    // Send back the sequence number of the squashed instruction.
505    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
506
507    // Send back the squash signal to tell stages that they should
508    // squash.
509    toIEW->commitInfo[tid].squash = true;
510
511    // Send back the rob squashing signal so other stages know that
512    // the ROB is in the process of squashing.
513    toIEW->commitInfo[tid].robSquashing = true;
514
515    toIEW->commitInfo[tid].branchMispredict = false;
516
517    toIEW->commitInfo[tid].nextPC = PC[tid];
518    toIEW->commitInfo[tid].nextNPC = nextPC[tid];
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::squashFromTrap(unsigned tid)
524{
525    squashAll(tid);
526
527    DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
528
529    thread[tid]->trapPending = false;
530    thread[tid]->inSyscall = false;
531    trapInFlight[tid] = false;
532
533    trapSquash[tid] = false;
534
535    commitStatus[tid] = ROBSquashing;
536    cpu->activityThisCycle();
537}
538
539template <class Impl>
540void
541DefaultCommit<Impl>::squashFromTC(unsigned tid)
542{
543    squashAll(tid);
544
545    DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
546
547    thread[tid]->inSyscall = false;
548    assert(!thread[tid]->trapPending);
549
550    commitStatus[tid] = ROBSquashing;
551    cpu->activityThisCycle();
552
553    tcSquash[tid] = false;
554}
555
556template <class Impl>
557void
558DefaultCommit<Impl>::tick()
559{
560    wroteToTimeBuffer = false;
561    _nextStatus = Inactive;
562
563    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
564        cpu->signalDrained();
565        drainPending = false;
566        return;
567    }
568
569    if (activeThreads->empty())
570        return;
571
572    std::list<unsigned>::iterator threads = activeThreads->begin();
573    std::list<unsigned>::iterator end = activeThreads->end();
574
575    // Check if any of the threads are done squashing.  Change the
576    // status if they are done.
577    while (threads != end) {
578        unsigned tid = *threads++;
579
580        // Clear the bit saying if the thread has committed stores
581        // this cycle.
582        committedStores[tid] = false;
583
584        if (commitStatus[tid] == ROBSquashing) {
585
586            if (rob->isDoneSquashing(tid)) {
587                commitStatus[tid] = Running;
588            } else {
589                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
590                        " insts this cycle.\n", tid);
591                rob->doSquash(tid);
592                toIEW->commitInfo[tid].robSquashing = true;
593                wroteToTimeBuffer = true;
594            }
595        }
596    }
597
598    commit();
599
600    markCompletedInsts();
601
602    threads = activeThreads->begin();
603
604    while (threads != end) {
605        unsigned tid = *threads++;
606
607        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
608            // The ROB has more instructions it can commit. Its next status
609            // will be active.
610            _nextStatus = Active;
611
612            DynInstPtr inst = rob->readHeadInst(tid);
613
614            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
615                    " ROB and ready to commit\n",
616                    tid, inst->seqNum, inst->readPC());
617
618        } else if (!rob->isEmpty(tid)) {
619            DynInstPtr inst = rob->readHeadInst(tid);
620
621            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
622                    "%#x is head of ROB and not ready\n",
623                    tid, inst->seqNum, inst->readPC());
624        }
625
626        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
627                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
628    }
629
630
631    if (wroteToTimeBuffer) {
632        DPRINTF(Activity, "Activity This Cycle.\n");
633        cpu->activityThisCycle();
634    }
635
636    updateStatus();
637}
638
639#if FULL_SYSTEM
640template <class Impl>
641void
642DefaultCommit<Impl>::handleInterrupt()
643{
644    if (interrupt != NoFault) {
645        // Wait until the ROB is empty and all stores have drained in
646        // order to enter the interrupt.
647        if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
648            // Squash or record that I need to squash this cycle if
649            // an interrupt needed to be handled.
650            DPRINTF(Commit, "Interrupt detected.\n");
651
652            Fault new_interrupt = cpu->getInterrupts();
653            assert(new_interrupt != NoFault);
654
655            // Clear the interrupt now that it's going to be handled
656            toIEW->commitInfo[0].clearInterrupt = true;
657
658            assert(!thread[0]->inSyscall);
659            thread[0]->inSyscall = true;
660
661            // CPU will handle interrupt.
662            cpu->processInterrupts(interrupt);
663
664            thread[0]->inSyscall = false;
665
666            commitStatus[0] = TrapPending;
667
668            // Generate trap squash event.
669            generateTrapEvent(0);
670
671            interrupt = NoFault;
672        } else {
673            DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
674        }
675    } else if (commitStatus[0] != TrapPending &&
676               cpu->check_interrupts(cpu->tcBase(0)) &&
677               !trapSquash[0] &&
678               !tcSquash[0]) {
679        // Process interrupts if interrupts are enabled, not in PAL
680        // mode, and no other traps or external squashes are currently
681        // pending.
682        // @todo: Allow other threads to handle interrupts.
683
684        // Get any interrupt that happened
685        interrupt = cpu->getInterrupts();
686
687        if (interrupt != NoFault) {
688            // Tell fetch that there is an interrupt pending.  This
689            // will make fetch wait until it sees a non PAL-mode PC,
690            // at which point it stops fetching instructions.
691            toIEW->commitInfo[0].interruptPending = true;
692        }
693    }
694}
695#endif // FULL_SYSTEM
696
697template <class Impl>
698void
699DefaultCommit<Impl>::commit()
700{
701
702#if FULL_SYSTEM
703    // Check for any interrupt, and start processing it.  Or if we
704    // have an outstanding interrupt and are at a point when it is
705    // valid to take an interrupt, process it.
706    if (cpu->check_interrupts(cpu->tcBase(0))) {
707        handleInterrupt();
708    }
709#endif // FULL_SYSTEM
710
711    ////////////////////////////////////
712    // Check for any possible squashes, handle them first
713    ////////////////////////////////////
714    std::list<unsigned>::iterator threads = activeThreads->begin();
715    std::list<unsigned>::iterator end = activeThreads->end();
716
717    while (threads != end) {
718        unsigned tid = *threads++;
719
720        // Not sure which one takes priority.  I think if we have
721        // both, that's a bad sign.
722        if (trapSquash[tid] == true) {
723            assert(!tcSquash[tid]);
724            squashFromTrap(tid);
725        } else if (tcSquash[tid] == true) {
726            assert(commitStatus[tid] != TrapPending);
727            squashFromTC(tid);
728        }
729
730        // Squashed sequence number must be older than youngest valid
731        // instruction in the ROB. This prevents squashes from younger
732        // instructions overriding squashes from older instructions.
733        if (fromIEW->squash[tid] &&
734            commitStatus[tid] != TrapPending &&
735            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
736
737            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
738                    tid,
739                    fromIEW->mispredPC[tid],
740                    fromIEW->squashedSeqNum[tid]);
741
742            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
743                    tid,
744                    fromIEW->nextPC[tid]);
745
746            commitStatus[tid] = ROBSquashing;
747
748            // If we want to include the squashing instruction in the squash,
749            // then use one older sequence number.
750            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
751
752#if ISA_HAS_DELAY_SLOT
753            InstSeqNum bdelay_done_seq_num = squashed_inst;
754            bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
755            bool branchMispredict = fromIEW->branchMispredict[tid];
756
757            // Squashing/not squashing the branch delay slot only makes
758            // sense when you're squashing from a branch, ie from a branch
759            // mispredict.
760            if (branchMispredict && !squash_bdelay_slot) {
761                bdelay_done_seq_num++;
762            }
763#endif
764
765            if (fromIEW->includeSquashInst[tid] == true) {
766                squashed_inst--;
767#if ISA_HAS_DELAY_SLOT
768                bdelay_done_seq_num--;
769#endif
770            }
771
772            // All younger instructions will be squashed. Set the sequence
773            // number as the youngest instruction in the ROB.
774            youngestSeqNum[tid] = squashed_inst;
775
776#if ISA_HAS_DELAY_SLOT
777            rob->squash(bdelay_done_seq_num, tid);
778            toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
779            toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
780#else
781            rob->squash(squashed_inst, tid);
782            toIEW->commitInfo[tid].squashDelaySlot = true;
783#endif
784            changedROBNumEntries[tid] = true;
785
786            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
787
788            toIEW->commitInfo[tid].squash = true;
789
790            // Send back the rob squashing signal so other stages know that
791            // the ROB is in the process of squashing.
792            toIEW->commitInfo[tid].robSquashing = true;
793
794            toIEW->commitInfo[tid].branchMispredict =
795                fromIEW->branchMispredict[tid];
796
797            toIEW->commitInfo[tid].branchTaken =
798                fromIEW->branchTaken[tid];
799
800            toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
801            toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
802
803            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
804
805            if (toIEW->commitInfo[tid].branchMispredict) {
806                ++branchMispredicts;
807            }
808        }
809
810    }
811
812    setNextStatus();
813
814    if (squashCounter != numThreads) {
815        // If we're not currently squashing, then get instructions.
816        getInsts();
817
818        // Try to commit any instructions.
819        commitInsts();
820    } else {
821#if ISA_HAS_DELAY_SLOT
822        skidInsert();
823#endif
824    }
825
826    //Check for any activity
827    threads = activeThreads->begin();
828
829    while (threads != end) {
830        unsigned tid = *threads++;
831
832        if (changedROBNumEntries[tid]) {
833            toIEW->commitInfo[tid].usedROB = true;
834            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
835
836            wroteToTimeBuffer = true;
837            changedROBNumEntries[tid] = false;
838            if (rob->isEmpty(tid))
839                checkEmptyROB[tid] = true;
840        }
841
842        // ROB is only considered "empty" for previous stages if: a)
843        // ROB is empty, b) there are no outstanding stores, c) IEW
844        // stage has received any information regarding stores that
845        // committed.
846        // c) is checked by making sure to not consider the ROB empty
847        // on the same cycle as when stores have been committed.
848        // @todo: Make this handle multi-cycle communication between
849        // commit and IEW.
850        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
851            !iewStage->hasStoresToWB() && !committedStores[tid]) {
852            checkEmptyROB[tid] = false;
853            toIEW->commitInfo[tid].usedROB = true;
854            toIEW->commitInfo[tid].emptyROB = true;
855            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
856            wroteToTimeBuffer = true;
857        }
858
859    }
860}
861
862template <class Impl>
863void
864DefaultCommit<Impl>::commitInsts()
865{
866    ////////////////////////////////////
867    // Handle commit
868    // Note that commit will be handled prior to putting new
869    // instructions in the ROB so that the ROB only tries to commit
870    // instructions it has in this current cycle, and not instructions
871    // it is writing in during this cycle.  Can't commit and squash
872    // things at the same time...
873    ////////////////////////////////////
874
875    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
876
877    unsigned num_committed = 0;
878
879    DynInstPtr head_inst;
880
881    // Commit as many instructions as possible until the commit bandwidth
882    // limit is reached, or it becomes impossible to commit any more.
883    while (num_committed < commitWidth) {
884        int commit_thread = getCommittingThread();
885
886        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
887            break;
888
889        head_inst = rob->readHeadInst(commit_thread);
890
891        int tid = head_inst->threadNumber;
892
893        assert(tid == commit_thread);
894
895        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
896                head_inst->seqNum, tid);
897
898        // If the head instruction is squashed, it is ready to retire
899        // (be removed from the ROB) at any time.
900        if (head_inst->isSquashed()) {
901
902            DPRINTF(Commit, "Retiring squashed instruction from "
903                    "ROB.\n");
904
905            rob->retireHead(commit_thread);
906
907            ++commitSquashedInsts;
908
909            // Record that the number of ROB entries has changed.
910            changedROBNumEntries[tid] = true;
911        } else {
912            PC[tid] = head_inst->readPC();
913            nextPC[tid] = head_inst->readNextPC();
914            nextNPC[tid] = head_inst->readNextNPC();
915
916            // Increment the total number of non-speculative instructions
917            // executed.
918            // Hack for now: it really shouldn't happen until after the
919            // commit is deemed to be successful, but this count is needed
920            // for syscalls.
921            thread[tid]->funcExeInst++;
922
923            // Try to commit the head instruction.
924            bool commit_success = commitHead(head_inst, num_committed);
925
926            if (commit_success) {
927                ++num_committed;
928
929                changedROBNumEntries[tid] = true;
930
931                // Set the doneSeqNum to the youngest committed instruction.
932                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
933
934                ++commitCommittedInsts;
935
936                // To match the old model, don't count nops and instruction
937                // prefetches towards the total commit count.
938                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
939                    cpu->instDone(tid);
940                }
941
942                PC[tid] = nextPC[tid];
943#if ISA_HAS_DELAY_SLOT
944                nextPC[tid] = nextNPC[tid];
945                nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
946#else
947                nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
948#endif
949
950#if FULL_SYSTEM
951                int count = 0;
952                Addr oldpc;
953                do {
954                    // Debug statement.  Checks to make sure we're not
955                    // currently updating state while handling PC events.
956                    if (count == 0)
957                        assert(!thread[tid]->inSyscall &&
958                               !thread[tid]->trapPending);
959                    oldpc = PC[tid];
960                    cpu->system->pcEventQueue.service(
961                        thread[tid]->getTC());
962                    count++;
963                } while (oldpc != PC[tid]);
964                if (count > 1) {
965                    DPRINTF(Commit, "PC skip function event, stopping commit\n");
966                    break;
967                }
968#endif
969            } else {
970                DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
971                        "[tid:%i] [sn:%i].\n",
972                        head_inst->readPC(), tid ,head_inst->seqNum);
973                break;
974            }
975        }
976    }
977
978    DPRINTF(CommitRate, "%i\n", num_committed);
979    numCommittedDist.sample(num_committed);
980
981    if (num_committed == commitWidth) {
982        commitEligibleSamples++;
983    }
984}
985
986template <class Impl>
987bool
988DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
989{
990    assert(head_inst);
991
992    int tid = head_inst->threadNumber;
993
994    // If the instruction is not executed yet, then it will need extra
995    // handling.  Signal backwards that it should be executed.
996    if (!head_inst->isExecuted()) {
997        // Keep this number correct.  We have not yet actually executed
998        // and committed this instruction.
999        thread[tid]->funcExeInst--;
1000
1001        if (head_inst->isNonSpeculative() ||
1002            head_inst->isStoreConditional() ||
1003            head_inst->isMemBarrier() ||
1004            head_inst->isWriteBarrier()) {
1005
1006            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1007                    "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
1008                    head_inst->seqNum, head_inst->readPC());
1009
1010            if (inst_num > 0 || iewStage->hasStoresToWB()) {
1011                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1012                return false;
1013            }
1014
1015            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1016
1017            // Change the instruction so it won't try to commit again until
1018            // it is executed.
1019            head_inst->clearCanCommit();
1020
1021            ++commitNonSpecStalls;
1022
1023            return false;
1024        } else if (head_inst->isLoad()) {
1025            if (inst_num > 0 || iewStage->hasStoresToWB()) {
1026                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1027                return false;
1028            }
1029
1030            assert(head_inst->uncacheable());
1031            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1032                    head_inst->seqNum, head_inst->readPC());
1033
1034            // Send back the non-speculative instruction's sequence
1035            // number.  Tell the lsq to re-execute the load.
1036            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1037            toIEW->commitInfo[tid].uncached = true;
1038            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1039
1040            head_inst->clearCanCommit();
1041
1042            return false;
1043        } else {
1044            panic("Trying to commit un-executed instruction "
1045                  "of unknown type!\n");
1046        }
1047    }
1048
1049    if (head_inst->isThreadSync()) {
1050        // Not handled for now.
1051        panic("Thread sync instructions are not handled yet.\n");
1052    }
1053
1054    // Check if the instruction caused a fault.  If so, trap.
1055    Fault inst_fault = head_inst->getFault();
1056
1057    // Stores mark themselves as completed.
1058    if (!head_inst->isStore() && inst_fault == NoFault) {
1059        head_inst->setCompleted();
1060    }
1061
1062#if USE_CHECKER
1063    // Use checker prior to updating anything due to traps or PC
1064    // based events.
1065    if (cpu->checker) {
1066        cpu->checker->verify(head_inst);
1067    }
1068#endif
1069
1070    // DTB will sometimes need the machine instruction for when
1071    // faults happen.  So we will set it here, prior to the DTB
1072    // possibly needing it for its fault.
1073    thread[tid]->setInst(
1074        static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1075
1076    if (inst_fault != NoFault) {
1077        DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1078                head_inst->seqNum, head_inst->readPC());
1079
1080        if (iewStage->hasStoresToWB() || inst_num > 0) {
1081            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1082            return false;
1083        }
1084
1085        head_inst->setCompleted();
1086
1087#if USE_CHECKER
1088        if (cpu->checker && head_inst->isStore()) {
1089            cpu->checker->verify(head_inst);
1090        }
1091#endif
1092
1093        assert(!thread[tid]->inSyscall);
1094
1095        // Mark that we're in state update mode so that the trap's
1096        // execution doesn't generate extra squashes.
1097        thread[tid]->inSyscall = true;
1098
1099        // Execute the trap.  Although it's slightly unrealistic in
1100        // terms of timing (as it doesn't wait for the full timing of
1101        // the trap event to complete before updating state), it's
1102        // needed to update the state as soon as possible.  This
1103        // prevents external agents from changing any specific state
1104        // that the trap need.
1105        cpu->trap(inst_fault, tid);
1106
1107        // Exit state update mode to avoid accidental updating.
1108        thread[tid]->inSyscall = false;
1109
1110        commitStatus[tid] = TrapPending;
1111
1112        if (head_inst->traceData) {
1113            head_inst->traceData->setFetchSeq(head_inst->seqNum);
1114            head_inst->traceData->setCPSeq(thread[tid]->numInst);
1115            head_inst->traceData->dump();
1116            delete head_inst->traceData;
1117            head_inst->traceData = NULL;
1118        }
1119
1120        // Generate trap squash event.
1121        generateTrapEvent(tid);
1122//        warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1123        return false;
1124    }
1125
1126    updateComInstStats(head_inst);
1127
1128#if FULL_SYSTEM
1129    if (thread[tid]->profile) {
1130//        bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1131//        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1132        thread[tid]->profilePC = head_inst->readPC();
1133        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1134                                                          head_inst->staticInst);
1135
1136        if (node)
1137            thread[tid]->profileNode = node;
1138    }
1139#endif
1140
1141    if (head_inst->traceData) {
1142        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1143        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1144        head_inst->traceData->dump();
1145        delete head_inst->traceData;
1146        head_inst->traceData = NULL;
1147    }
1148
1149    // Update the commit rename map
1150    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1151        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1152                                 head_inst->renamedDestRegIdx(i));
1153    }
1154
1155    if (head_inst->isCopy())
1156        panic("Should not commit any copy instructions!");
1157
1158    // Finally clear the head ROB entry.
1159    rob->retireHead(tid);
1160
1161    // If this was a store, record it for this cycle.
1162    if (head_inst->isStore())
1163        committedStores[tid] = true;
1164
1165    // Return true to indicate that we have committed an instruction.
1166    return true;
1167}
1168
1169template <class Impl>
1170void
1171DefaultCommit<Impl>::getInsts()
1172{
1173    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1174
1175#if ISA_HAS_DELAY_SLOT
1176    // Read any renamed instructions and place them into the ROB.
1177    int insts_to_process = std::min((int)renameWidth,
1178                               (int)(fromRename->size + skidBuffer.size()));
1179    int rename_idx = 0;
1180
1181    DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1182            "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1183            skidBuffer.size());
1184#else
1185    // Read any renamed instructions and place them into the ROB.
1186    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1187#endif
1188
1189
1190    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1191        DynInstPtr inst;
1192
1193#if ISA_HAS_DELAY_SLOT
1194        // Get insts from skidBuffer or from Rename
1195        if (skidBuffer.size() > 0) {
1196            DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1197            inst = skidBuffer.front();
1198            skidBuffer.pop();
1199        } else {
1200            DPRINTF(Commit, "Grabbing rename inst.\n");
1201            inst = fromRename->insts[rename_idx++];
1202        }
1203#else
1204        inst = fromRename->insts[inst_num];
1205#endif
1206        int tid = inst->threadNumber;
1207
1208        if (!inst->isSquashed() &&
1209            commitStatus[tid] != ROBSquashing &&
1210            commitStatus[tid] != TrapPending) {
1211            changedROBNumEntries[tid] = true;
1212
1213            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1214                    inst->readPC(), inst->seqNum, tid);
1215
1216            rob->insertInst(inst);
1217
1218            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1219
1220            youngestSeqNum[tid] = inst->seqNum;
1221        } else {
1222            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1223                    "squashed, skipping.\n",
1224                    inst->readPC(), inst->seqNum, tid);
1225        }
1226    }
1227
1228#if ISA_HAS_DELAY_SLOT
1229    if (rename_idx < fromRename->size) {
1230        DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1231
1232        for (;
1233             rename_idx < fromRename->size;
1234             rename_idx++) {
1235            DynInstPtr inst = fromRename->insts[rename_idx];
1236
1237            if (!inst->isSquashed()) {
1238                DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1239                        "skidBuffer.\n", inst->readPC(), inst->seqNum,
1240                        inst->threadNumber);
1241                skidBuffer.push(inst);
1242            } else {
1243                DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1244                        "squashed, skipping.\n",
1245                        inst->readPC(), inst->seqNum, inst->threadNumber);
1246            }
1247        }
1248    }
1249#endif
1250
1251}
1252
1253template <class Impl>
1254void
1255DefaultCommit<Impl>::skidInsert()
1256{
1257    DPRINTF(Commit, "Attempting to any instructions from rename into "
1258            "skidBuffer.\n");
1259
1260    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1261        DynInstPtr inst = fromRename->insts[inst_num];
1262
1263        if (!inst->isSquashed()) {
1264            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1265                    "skidBuffer.\n", inst->readPC(), inst->seqNum,
1266                    inst->threadNumber);
1267            skidBuffer.push(inst);
1268        } else {
1269            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1270                    "squashed, skipping.\n",
1271                    inst->readPC(), inst->seqNum, inst->threadNumber);
1272        }
1273    }
1274}
1275
1276template <class Impl>
1277void
1278DefaultCommit<Impl>::markCompletedInsts()
1279{
1280    // Grab completed insts out of the IEW instruction queue, and mark
1281    // instructions completed within the ROB.
1282    for (int inst_num = 0;
1283         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1284         ++inst_num)
1285    {
1286        if (!fromIEW->insts[inst_num]->isSquashed()) {
1287            DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1288                    "within ROB.\n",
1289                    fromIEW->insts[inst_num]->threadNumber,
1290                    fromIEW->insts[inst_num]->readPC(),
1291                    fromIEW->insts[inst_num]->seqNum);
1292
1293            // Mark the instruction as ready to commit.
1294            fromIEW->insts[inst_num]->setCanCommit();
1295        }
1296    }
1297}
1298
1299template <class Impl>
1300bool
1301DefaultCommit<Impl>::robDoneSquashing()
1302{
1303    std::list<unsigned>::iterator threads = activeThreads->begin();
1304    std::list<unsigned>::iterator end = activeThreads->end();
1305
1306    while (threads != end) {
1307        unsigned tid = *threads++;
1308
1309        if (!rob->isDoneSquashing(tid))
1310            return false;
1311    }
1312
1313    return true;
1314}
1315
1316template <class Impl>
1317void
1318DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1319{
1320    unsigned thread = inst->threadNumber;
1321
1322    //
1323    //  Pick off the software prefetches
1324    //
1325#ifdef TARGET_ALPHA
1326    if (inst->isDataPrefetch()) {
1327        statComSwp[thread]++;
1328    } else {
1329        statComInst[thread]++;
1330    }
1331#else
1332    statComInst[thread]++;
1333#endif
1334
1335    //
1336    //  Control Instructions
1337    //
1338    if (inst->isControl())
1339        statComBranches[thread]++;
1340
1341    //
1342    //  Memory references
1343    //
1344    if (inst->isMemRef()) {
1345        statComRefs[thread]++;
1346
1347        if (inst->isLoad()) {
1348            statComLoads[thread]++;
1349        }
1350    }
1351
1352    if (inst->isMemBarrier()) {
1353        statComMembars[thread]++;
1354    }
1355}
1356
1357////////////////////////////////////////
1358//                                    //
1359//  SMT COMMIT POLICY MAINTAINED HERE //
1360//                                    //
1361////////////////////////////////////////
1362template <class Impl>
1363int
1364DefaultCommit<Impl>::getCommittingThread()
1365{
1366    if (numThreads > 1) {
1367        switch (commitPolicy) {
1368
1369          case Aggressive:
1370            //If Policy is Aggressive, commit will call
1371            //this function multiple times per
1372            //cycle
1373            return oldestReady();
1374
1375          case RoundRobin:
1376            return roundRobin();
1377
1378          case OldestReady:
1379            return oldestReady();
1380
1381          default:
1382            return -1;
1383        }
1384    } else {
1385        assert(!activeThreads->empty());
1386        int tid = activeThreads->front();
1387
1388        if (commitStatus[tid] == Running ||
1389            commitStatus[tid] == Idle ||
1390            commitStatus[tid] == FetchTrapPending) {
1391            return tid;
1392        } else {
1393            return -1;
1394        }
1395    }
1396}
1397
1398template<class Impl>
1399int
1400DefaultCommit<Impl>::roundRobin()
1401{
1402    std::list<unsigned>::iterator pri_iter = priority_list.begin();
1403    std::list<unsigned>::iterator end      = priority_list.end();
1404
1405    while (pri_iter != end) {
1406        unsigned tid = *pri_iter;
1407
1408        if (commitStatus[tid] == Running ||
1409            commitStatus[tid] == Idle ||
1410            commitStatus[tid] == FetchTrapPending) {
1411
1412            if (rob->isHeadReady(tid)) {
1413                priority_list.erase(pri_iter);
1414                priority_list.push_back(tid);
1415
1416                return tid;
1417            }
1418        }
1419
1420        pri_iter++;
1421    }
1422
1423    return -1;
1424}
1425
1426template<class Impl>
1427int
1428DefaultCommit<Impl>::oldestReady()
1429{
1430    unsigned oldest = 0;
1431    bool first = true;
1432
1433    std::list<unsigned>::iterator threads = activeThreads->begin();
1434    std::list<unsigned>::iterator end = activeThreads->end();
1435
1436    while (threads != end) {
1437        unsigned tid = *threads++;
1438
1439        if (!rob->isEmpty(tid) &&
1440            (commitStatus[tid] == Running ||
1441             commitStatus[tid] == Idle ||
1442             commitStatus[tid] == FetchTrapPending)) {
1443
1444            if (rob->isHeadReady(tid)) {
1445
1446                DynInstPtr head_inst = rob->readHeadInst(tid);
1447
1448                if (first) {
1449                    oldest = tid;
1450                    first = false;
1451                } else if (head_inst->seqNum < oldest) {
1452                    oldest = tid;
1453                }
1454            }
1455        }
1456    }
1457
1458    if (!first) {
1459        return oldest;
1460    } else {
1461        return -1;
1462    }
1463}
1464