commit_impl.hh revision 3795:60ecc96c3cee 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51                                          unsigned _tid)
52    : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54    this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61    // This will get reset by commit if it was switched out at the
62    // time of this event processing.
63    commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70    return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75    : squashCounter(0),
76      iewToCommitDelay(params->iewToCommitDelay),
77      commitToIEWDelay(params->commitToIEWDelay),
78      renameToROBDelay(params->renameToROBDelay),
79      fetchToCommitDelay(params->commitToFetchDelay),
80      renameWidth(params->renameWidth),
81      commitWidth(params->commitWidth),
82      numThreads(params->numberOfThreads),
83      drainPending(false),
84      switchedOut(false),
85      trapLatency(params->trapLatency)
86{
87    _status = Active;
88    _nextStatus = Inactive;
89    std::string policy = params->smtCommitPolicy;
90
91    //Convert string to lowercase
92    std::transform(policy.begin(), policy.end(), policy.begin(),
93                   (int(*)(int)) tolower);
94
95    //Assign commit policy
96    if (policy == "aggressive"){
97        commitPolicy = Aggressive;
98
99        DPRINTF(Commit,"Commit Policy set to Aggressive.");
100    } else if (policy == "roundrobin"){
101        commitPolicy = RoundRobin;
102
103        //Set-Up Priority List
104        for (int tid=0; tid < numThreads; tid++) {
105            priority_list.push_back(tid);
106        }
107
108        DPRINTF(Commit,"Commit Policy set to Round Robin.");
109    } else if (policy == "oldestready"){
110        commitPolicy = OldestReady;
111
112        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113    } else {
114        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115               "RoundRobin,OldestReady}");
116    }
117
118    for (int i=0; i < numThreads; i++) {
119        commitStatus[i] = Idle;
120        changedROBNumEntries[i] = false;
121        trapSquash[i] = false;
122        tcSquash[i] = false;
123        PC[i] = nextPC[i] = nextNPC[i] = 0;
124    }
125#if FULL_SYSTEM
126    interrupt = NoFault;
127#endif
128}
129
130template <class Impl>
131std::string
132DefaultCommit<Impl>::name() const
133{
134    return cpu->name() + ".commit";
135}
136
137template <class Impl>
138void
139DefaultCommit<Impl>::regStats()
140{
141    using namespace Stats;
142    commitCommittedInsts
143        .name(name() + ".commitCommittedInsts")
144        .desc("The number of committed instructions")
145        .prereq(commitCommittedInsts);
146    commitSquashedInsts
147        .name(name() + ".commitSquashedInsts")
148        .desc("The number of squashed insts skipped by commit")
149        .prereq(commitSquashedInsts);
150    commitSquashEvents
151        .name(name() + ".commitSquashEvents")
152        .desc("The number of times commit is told to squash")
153        .prereq(commitSquashEvents);
154    commitNonSpecStalls
155        .name(name() + ".commitNonSpecStalls")
156        .desc("The number of times commit has been forced to stall to "
157              "communicate backwards")
158        .prereq(commitNonSpecStalls);
159    branchMispredicts
160        .name(name() + ".branchMispredicts")
161        .desc("The number of times a branch was mispredicted")
162        .prereq(branchMispredicts);
163    numCommittedDist
164        .init(0,commitWidth,1)
165        .name(name() + ".COM:committed_per_cycle")
166        .desc("Number of insts commited each cycle")
167        .flags(Stats::pdf)
168        ;
169
170    statComInst
171        .init(cpu->number_of_threads)
172        .name(name() + ".COM:count")
173        .desc("Number of instructions committed")
174        .flags(total)
175        ;
176
177    statComSwp
178        .init(cpu->number_of_threads)
179        .name(name() + ".COM:swp_count")
180        .desc("Number of s/w prefetches committed")
181        .flags(total)
182        ;
183
184    statComRefs
185        .init(cpu->number_of_threads)
186        .name(name() +  ".COM:refs")
187        .desc("Number of memory references committed")
188        .flags(total)
189        ;
190
191    statComLoads
192        .init(cpu->number_of_threads)
193        .name(name() +  ".COM:loads")
194        .desc("Number of loads committed")
195        .flags(total)
196        ;
197
198    statComMembars
199        .init(cpu->number_of_threads)
200        .name(name() +  ".COM:membars")
201        .desc("Number of memory barriers committed")
202        .flags(total)
203        ;
204
205    statComBranches
206        .init(cpu->number_of_threads)
207        .name(name() + ".COM:branches")
208        .desc("Number of branches committed")
209        .flags(total)
210        ;
211
212    commitEligible
213        .init(cpu->number_of_threads)
214        .name(name() + ".COM:bw_limited")
215        .desc("number of insts not committed due to BW limits")
216        .flags(total)
217        ;
218
219    commitEligibleSamples
220        .name(name() + ".COM:bw_lim_events")
221        .desc("number cycles where commit BW limit reached")
222        ;
223}
224
225template <class Impl>
226void
227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
228{
229    DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
230    cpu = cpu_ptr;
231
232    // Commit must broadcast the number of free entries it has at the start of
233    // the simulation, so it starts as active.
234    cpu->activateStage(O3CPU::CommitIdx);
235
236    trapLatency = cpu->cycles(trapLatency);
237}
238
239template <class Impl>
240void
241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
242{
243    thread = threads;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
250    DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
251    timeBuffer = tb_ptr;
252
253    // Setup wire to send information back to IEW.
254    toIEW = timeBuffer->getWire(0);
255
256    // Setup wire to read data from IEW (for the ROB).
257    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
258}
259
260template <class Impl>
261void
262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
263{
264    DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
265    fetchQueue = fq_ptr;
266
267    // Setup wire to get instructions from rename (for the ROB).
268    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
274{
275    DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276    renameQueue = rq_ptr;
277
278    // Setup wire to get instructions from rename (for the ROB).
279    fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286    DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
287    iewQueue = iq_ptr;
288
289    // Setup wire to get instructions from IEW.
290    fromIEW = iewQueue->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
296{
297    iewStage = iew_stage;
298}
299
300template<class Impl>
301void
302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
303{
304    DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305    activeThreads = at_ptr;
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
311{
312    DPRINTF(Commit, "Setting rename map pointers.\n");
313
314    for (int i=0; i < numThreads; i++) {
315        renameMap[i] = &rm_ptr[i];
316    }
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setROB(ROB *rob_ptr)
322{
323    DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324    rob = rob_ptr;
325}
326
327template <class Impl>
328void
329DefaultCommit<Impl>::initStage()
330{
331    rob->setActiveThreads(activeThreads);
332    rob->resetEntries();
333
334    // Broadcast the number of free entries.
335    for (int i=0; i < numThreads; i++) {
336        toIEW->commitInfo[i].usedROB = true;
337        toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
338    }
339
340    cpu->activityThisCycle();
341}
342
343template <class Impl>
344bool
345DefaultCommit<Impl>::drain()
346{
347    drainPending = true;
348
349    return false;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::switchOut()
355{
356    switchedOut = true;
357    drainPending = false;
358    rob->switchOut();
359}
360
361template <class Impl>
362void
363DefaultCommit<Impl>::resume()
364{
365    drainPending = false;
366}
367
368template <class Impl>
369void
370DefaultCommit<Impl>::takeOverFrom()
371{
372    switchedOut = false;
373    _status = Active;
374    _nextStatus = Inactive;
375    for (int i=0; i < numThreads; i++) {
376        commitStatus[i] = Idle;
377        changedROBNumEntries[i] = false;
378        trapSquash[i] = false;
379        tcSquash[i] = false;
380    }
381    squashCounter = 0;
382    rob->takeOverFrom();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::updateStatus()
388{
389    // reset ROB changed variable
390    std::list<unsigned>::iterator threads = (*activeThreads).begin();
391    while (threads != (*activeThreads).end()) {
392        unsigned tid = *threads++;
393        changedROBNumEntries[tid] = false;
394
395        // Also check if any of the threads has a trap pending
396        if (commitStatus[tid] == TrapPending ||
397            commitStatus[tid] == FetchTrapPending) {
398            _nextStatus = Active;
399        }
400    }
401
402    if (_nextStatus == Inactive && _status == Active) {
403        DPRINTF(Activity, "Deactivating stage.\n");
404        cpu->deactivateStage(O3CPU::CommitIdx);
405    } else if (_nextStatus == Active && _status == Inactive) {
406        DPRINTF(Activity, "Activating stage.\n");
407        cpu->activateStage(O3CPU::CommitIdx);
408    }
409
410    _status = _nextStatus;
411}
412
413template <class Impl>
414void
415DefaultCommit<Impl>::setNextStatus()
416{
417    int squashes = 0;
418
419    std::list<unsigned>::iterator threads = (*activeThreads).begin();
420
421    while (threads != (*activeThreads).end()) {
422        unsigned tid = *threads++;
423
424        if (commitStatus[tid] == ROBSquashing) {
425            squashes++;
426        }
427    }
428
429    squashCounter = squashes;
430
431    // If commit is currently squashing, then it will have activity for the
432    // next cycle. Set its next status as active.
433    if (squashCounter) {
434        _nextStatus = Active;
435    }
436}
437
438template <class Impl>
439bool
440DefaultCommit<Impl>::changedROBEntries()
441{
442    std::list<unsigned>::iterator threads = (*activeThreads).begin();
443
444    while (threads != (*activeThreads).end()) {
445        unsigned tid = *threads++;
446
447        if (changedROBNumEntries[tid]) {
448            return true;
449        }
450    }
451
452    return false;
453}
454
455template <class Impl>
456unsigned
457DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
458{
459    return rob->numFreeEntries(tid);
460}
461
462template <class Impl>
463void
464DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
465{
466    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
467
468    TrapEvent *trap = new TrapEvent(this, tid);
469
470    trap->schedule(curTick + trapLatency);
471
472    thread[tid]->trapPending = true;
473}
474
475template <class Impl>
476void
477DefaultCommit<Impl>::generateTCEvent(unsigned tid)
478{
479    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
480
481    tcSquash[tid] = true;
482}
483
484template <class Impl>
485void
486DefaultCommit<Impl>::squashAll(unsigned tid)
487{
488    // If we want to include the squashing instruction in the squash,
489    // then use one older sequence number.
490    // Hopefully this doesn't mess things up.  Basically I want to squash
491    // all instructions of this thread.
492    InstSeqNum squashed_inst = rob->isEmpty() ?
493        0 : rob->readHeadInst(tid)->seqNum - 1;;
494
495    // All younger instructions will be squashed. Set the sequence
496    // number as the youngest instruction in the ROB (0 in this case.
497    // Hopefully nothing breaks.)
498    youngestSeqNum[tid] = 0;
499
500    rob->squash(squashed_inst, tid);
501    changedROBNumEntries[tid] = true;
502
503    // Send back the sequence number of the squashed instruction.
504    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
505
506    // Send back the squash signal to tell stages that they should
507    // squash.
508    toIEW->commitInfo[tid].squash = true;
509
510    // Send back the rob squashing signal so other stages know that
511    // the ROB is in the process of squashing.
512    toIEW->commitInfo[tid].robSquashing = true;
513
514    toIEW->commitInfo[tid].branchMispredict = false;
515
516    toIEW->commitInfo[tid].nextPC = PC[tid];
517    toIEW->commitInfo[tid].nextNPC = nextPC[tid];
518}
519
520template <class Impl>
521void
522DefaultCommit<Impl>::squashFromTrap(unsigned tid)
523{
524    squashAll(tid);
525
526    DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
527
528    thread[tid]->trapPending = false;
529    thread[tid]->inSyscall = false;
530
531    trapSquash[tid] = false;
532
533    commitStatus[tid] = ROBSquashing;
534    cpu->activityThisCycle();
535}
536
537template <class Impl>
538void
539DefaultCommit<Impl>::squashFromTC(unsigned tid)
540{
541    squashAll(tid);
542
543    DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
544
545    thread[tid]->inSyscall = false;
546    assert(!thread[tid]->trapPending);
547
548    commitStatus[tid] = ROBSquashing;
549    cpu->activityThisCycle();
550
551    tcSquash[tid] = false;
552}
553
554template <class Impl>
555void
556DefaultCommit<Impl>::tick()
557{
558    wroteToTimeBuffer = false;
559    _nextStatus = Inactive;
560
561    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
562        cpu->signalDrained();
563        drainPending = false;
564        return;
565    }
566
567    if ((*activeThreads).size() <= 0)
568        return;
569
570    std::list<unsigned>::iterator threads = (*activeThreads).begin();
571
572    // Check if any of the threads are done squashing.  Change the
573    // status if they are done.
574    while (threads != (*activeThreads).end()) {
575        unsigned tid = *threads++;
576
577        if (commitStatus[tid] == ROBSquashing) {
578
579            if (rob->isDoneSquashing(tid)) {
580                commitStatus[tid] = Running;
581            } else {
582                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
583                        " insts this cycle.\n", tid);
584                rob->doSquash(tid);
585                toIEW->commitInfo[tid].robSquashing = true;
586                wroteToTimeBuffer = true;
587            }
588        }
589    }
590
591    commit();
592
593    markCompletedInsts();
594
595    threads = (*activeThreads).begin();
596
597    while (threads != (*activeThreads).end()) {
598        unsigned tid = *threads++;
599
600        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
601            // The ROB has more instructions it can commit. Its next status
602            // will be active.
603            _nextStatus = Active;
604
605            DynInstPtr inst = rob->readHeadInst(tid);
606
607            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
608                    " ROB and ready to commit\n",
609                    tid, inst->seqNum, inst->readPC());
610
611        } else if (!rob->isEmpty(tid)) {
612            DynInstPtr inst = rob->readHeadInst(tid);
613
614            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
615                    "%#x is head of ROB and not ready\n",
616                    tid, inst->seqNum, inst->readPC());
617        }
618
619        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
620                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
621    }
622
623
624    if (wroteToTimeBuffer) {
625        DPRINTF(Activity, "Activity This Cycle.\n");
626        cpu->activityThisCycle();
627    }
628
629    updateStatus();
630}
631
632template <class Impl>
633void
634DefaultCommit<Impl>::commit()
635{
636
637    //////////////////////////////////////
638    // Check for interrupts
639    //////////////////////////////////////
640
641#if FULL_SYSTEM
642    if (interrupt != NoFault) {
643        // Wait until the ROB is empty and all stores have drained in
644        // order to enter the interrupt.
645        if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
646            // Squash or record that I need to squash this cycle if
647            // an interrupt needed to be handled.
648            DPRINTF(Commit, "Interrupt detected.\n");
649
650            assert(!thread[0]->inSyscall);
651            thread[0]->inSyscall = true;
652
653            // CPU will handle interrupt.
654            cpu->processInterrupts(interrupt);
655
656            thread[0]->inSyscall = false;
657
658            commitStatus[0] = TrapPending;
659
660            // Generate trap squash event.
661            generateTrapEvent(0);
662
663            // Clear the interrupt now that it's been handled
664            toIEW->commitInfo[0].clearInterrupt = true;
665            interrupt = NoFault;
666        } else {
667            DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
668        }
669    } else if (cpu->checkInterrupts &&
670        cpu->check_interrupts(cpu->tcBase(0)) &&
671        commitStatus[0] != TrapPending &&
672        !trapSquash[0] &&
673        !tcSquash[0]) {
674        // Process interrupts if interrupts are enabled, not in PAL
675        // mode, and no other traps or external squashes are currently
676        // pending.
677        // @todo: Allow other threads to handle interrupts.
678
679        // Get any interrupt that happened
680        interrupt = cpu->getInterrupts();
681
682        if (interrupt != NoFault) {
683            // Tell fetch that there is an interrupt pending.  This
684            // will make fetch wait until it sees a non PAL-mode PC,
685            // at which point it stops fetching instructions.
686            toIEW->commitInfo[0].interruptPending = true;
687        }
688    }
689
690#endif // FULL_SYSTEM
691
692    ////////////////////////////////////
693    // Check for any possible squashes, handle them first
694    ////////////////////////////////////
695    std::list<unsigned>::iterator threads = (*activeThreads).begin();
696
697    while (threads != (*activeThreads).end()) {
698        unsigned tid = *threads++;
699
700        // Not sure which one takes priority.  I think if we have
701        // both, that's a bad sign.
702        if (trapSquash[tid] == true) {
703            assert(!tcSquash[tid]);
704            squashFromTrap(tid);
705        } else if (tcSquash[tid] == true) {
706            squashFromTC(tid);
707        }
708
709        // Squashed sequence number must be older than youngest valid
710        // instruction in the ROB. This prevents squashes from younger
711        // instructions overriding squashes from older instructions.
712        if (fromIEW->squash[tid] &&
713            commitStatus[tid] != TrapPending &&
714            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
715
716            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
717                    tid,
718                    fromIEW->mispredPC[tid],
719                    fromIEW->squashedSeqNum[tid]);
720
721            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
722                    tid,
723                    fromIEW->nextPC[tid]);
724
725            commitStatus[tid] = ROBSquashing;
726
727            // If we want to include the squashing instruction in the squash,
728            // then use one older sequence number.
729            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
730
731#if ISA_HAS_DELAY_SLOT
732            InstSeqNum bdelay_done_seq_num = squashed_inst;
733            bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
734
735            if (!squash_bdelay_slot)
736                bdelay_done_seq_num++;
737#endif
738
739            if (fromIEW->includeSquashInst[tid] == true) {
740                squashed_inst--;
741#if ISA_HAS_DELAY_SLOT
742                bdelay_done_seq_num--;
743#endif
744            }
745            // All younger instructions will be squashed. Set the sequence
746            // number as the youngest instruction in the ROB.
747            youngestSeqNum[tid] = squashed_inst;
748
749#if ISA_HAS_DELAY_SLOT
750            rob->squash(bdelay_done_seq_num, tid);
751            toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
752            toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
753#else
754            rob->squash(squashed_inst, tid);
755            toIEW->commitInfo[tid].squashDelaySlot = true;
756#endif
757            changedROBNumEntries[tid] = true;
758
759            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
760
761            toIEW->commitInfo[tid].squash = true;
762
763            // Send back the rob squashing signal so other stages know that
764            // the ROB is in the process of squashing.
765            toIEW->commitInfo[tid].robSquashing = true;
766
767            toIEW->commitInfo[tid].branchMispredict =
768                fromIEW->branchMispredict[tid];
769
770            toIEW->commitInfo[tid].branchTaken =
771                fromIEW->branchTaken[tid];
772
773            toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
774            toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
775
776            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
777
778            if (toIEW->commitInfo[tid].branchMispredict) {
779                ++branchMispredicts;
780            }
781        }
782
783    }
784
785    setNextStatus();
786
787    if (squashCounter != numThreads) {
788        // If we're not currently squashing, then get instructions.
789        getInsts();
790
791        // Try to commit any instructions.
792        commitInsts();
793    } else {
794#if ISA_HAS_DELAY_SLOT
795        skidInsert();
796#endif
797    }
798
799    //Check for any activity
800    threads = (*activeThreads).begin();
801
802    while (threads != (*activeThreads).end()) {
803        unsigned tid = *threads++;
804
805        if (changedROBNumEntries[tid]) {
806            toIEW->commitInfo[tid].usedROB = true;
807            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
808
809            if (rob->isEmpty(tid)) {
810                toIEW->commitInfo[tid].emptyROB = true;
811            }
812
813            wroteToTimeBuffer = true;
814            changedROBNumEntries[tid] = false;
815        }
816    }
817}
818
819template <class Impl>
820void
821DefaultCommit<Impl>::commitInsts()
822{
823    ////////////////////////////////////
824    // Handle commit
825    // Note that commit will be handled prior to putting new
826    // instructions in the ROB so that the ROB only tries to commit
827    // instructions it has in this current cycle, and not instructions
828    // it is writing in during this cycle.  Can't commit and squash
829    // things at the same time...
830    ////////////////////////////////////
831
832    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
833
834    unsigned num_committed = 0;
835
836    DynInstPtr head_inst;
837
838    // Commit as many instructions as possible until the commit bandwidth
839    // limit is reached, or it becomes impossible to commit any more.
840    while (num_committed < commitWidth) {
841        int commit_thread = getCommittingThread();
842
843        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
844            break;
845
846        head_inst = rob->readHeadInst(commit_thread);
847
848        int tid = head_inst->threadNumber;
849
850        assert(tid == commit_thread);
851
852        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
853                head_inst->seqNum, tid);
854
855        // If the head instruction is squashed, it is ready to retire
856        // (be removed from the ROB) at any time.
857        if (head_inst->isSquashed()) {
858
859            DPRINTF(Commit, "Retiring squashed instruction from "
860                    "ROB.\n");
861
862            rob->retireHead(commit_thread);
863
864            ++commitSquashedInsts;
865
866            // Record that the number of ROB entries has changed.
867            changedROBNumEntries[tid] = true;
868        } else {
869            PC[tid] = head_inst->readPC();
870            nextPC[tid] = head_inst->readNextPC();
871            nextNPC[tid] = head_inst->readNextNPC();
872
873            // Increment the total number of non-speculative instructions
874            // executed.
875            // Hack for now: it really shouldn't happen until after the
876            // commit is deemed to be successful, but this count is needed
877            // for syscalls.
878            thread[tid]->funcExeInst++;
879
880            // Try to commit the head instruction.
881            bool commit_success = commitHead(head_inst, num_committed);
882
883            if (commit_success) {
884                ++num_committed;
885
886                changedROBNumEntries[tid] = true;
887
888                // Set the doneSeqNum to the youngest committed instruction.
889                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
890
891                ++commitCommittedInsts;
892
893                // To match the old model, don't count nops and instruction
894                // prefetches towards the total commit count.
895                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
896                    cpu->instDone(tid);
897                }
898
899                PC[tid] = nextPC[tid];
900#if ISA_HAS_DELAY_SLOT
901                nextPC[tid] = nextNPC[tid];
902                nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
903#else
904                nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
905#endif
906
907#if FULL_SYSTEM
908                int count = 0;
909                Addr oldpc;
910                do {
911                    // Debug statement.  Checks to make sure we're not
912                    // currently updating state while handling PC events.
913                    if (count == 0)
914                        assert(!thread[tid]->inSyscall &&
915                               !thread[tid]->trapPending);
916                    oldpc = PC[tid];
917                    cpu->system->pcEventQueue.service(
918                        thread[tid]->getTC());
919                    count++;
920                } while (oldpc != PC[tid]);
921                if (count > 1) {
922                    DPRINTF(Commit, "PC skip function event, stopping commit\n");
923                    break;
924                }
925#endif
926            } else {
927                DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
928                        "[tid:%i] [sn:%i].\n",
929                        head_inst->readPC(), tid ,head_inst->seqNum);
930                break;
931            }
932        }
933    }
934
935    DPRINTF(CommitRate, "%i\n", num_committed);
936    numCommittedDist.sample(num_committed);
937
938    if (num_committed == commitWidth) {
939        commitEligibleSamples++;
940    }
941}
942
943template <class Impl>
944bool
945DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
946{
947    assert(head_inst);
948
949    int tid = head_inst->threadNumber;
950
951    // If the instruction is not executed yet, then it will need extra
952    // handling.  Signal backwards that it should be executed.
953    if (!head_inst->isExecuted()) {
954        // Keep this number correct.  We have not yet actually executed
955        // and committed this instruction.
956        thread[tid]->funcExeInst--;
957
958        head_inst->setAtCommit();
959
960        if (head_inst->isNonSpeculative() ||
961            head_inst->isStoreConditional() ||
962            head_inst->isMemBarrier() ||
963            head_inst->isWriteBarrier()) {
964
965            DPRINTF(Commit, "Encountered a barrier or non-speculative "
966                    "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
967                    head_inst->seqNum, head_inst->readPC());
968
969#if !FULL_SYSTEM
970            // Hack to make sure syscalls/memory barriers/quiesces
971            // aren't executed until all stores write back their data.
972            // This direct communication shouldn't be used for
973            // anything other than this.
974            if (inst_num > 0 || iewStage->hasStoresToWB())
975#else
976            if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
977                    head_inst->isQuiesce()) &&
978                iewStage->hasStoresToWB())
979#endif
980            {
981                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
982                return false;
983            }
984
985            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
986
987            // Change the instruction so it won't try to commit again until
988            // it is executed.
989            head_inst->clearCanCommit();
990
991            ++commitNonSpecStalls;
992
993            return false;
994        } else if (head_inst->isLoad()) {
995            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
996                    head_inst->seqNum, head_inst->readPC());
997
998            // Send back the non-speculative instruction's sequence
999            // number.  Tell the lsq to re-execute the load.
1000            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1001            toIEW->commitInfo[tid].uncached = true;
1002            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1003
1004            head_inst->clearCanCommit();
1005
1006            return false;
1007        } else {
1008            panic("Trying to commit un-executed instruction "
1009                  "of unknown type!\n");
1010        }
1011    }
1012
1013    if (head_inst->isThreadSync()) {
1014        // Not handled for now.
1015        panic("Thread sync instructions are not handled yet.\n");
1016    }
1017
1018    // Stores mark themselves as completed.
1019    if (!head_inst->isStore()) {
1020        head_inst->setCompleted();
1021    }
1022
1023#if USE_CHECKER
1024    // Use checker prior to updating anything due to traps or PC
1025    // based events.
1026    if (cpu->checker) {
1027        cpu->checker->verify(head_inst);
1028    }
1029#endif
1030
1031    // Check if the instruction caused a fault.  If so, trap.
1032    Fault inst_fault = head_inst->getFault();
1033
1034    // DTB will sometimes need the machine instruction for when
1035    // faults happen.  So we will set it here, prior to the DTB
1036    // possibly needing it for its fault.
1037    thread[tid]->setInst(
1038        static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1039
1040    if (inst_fault != NoFault) {
1041        head_inst->setCompleted();
1042        DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1043                head_inst->seqNum, head_inst->readPC());
1044
1045        if (iewStage->hasStoresToWB() || inst_num > 0) {
1046            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1047            return false;
1048        }
1049
1050#if USE_CHECKER
1051        if (cpu->checker && head_inst->isStore()) {
1052            cpu->checker->verify(head_inst);
1053        }
1054#endif
1055
1056        assert(!thread[tid]->inSyscall);
1057
1058        // Mark that we're in state update mode so that the trap's
1059        // execution doesn't generate extra squashes.
1060        thread[tid]->inSyscall = true;
1061
1062        // Execute the trap.  Although it's slightly unrealistic in
1063        // terms of timing (as it doesn't wait for the full timing of
1064        // the trap event to complete before updating state), it's
1065        // needed to update the state as soon as possible.  This
1066        // prevents external agents from changing any specific state
1067        // that the trap need.
1068        cpu->trap(inst_fault, tid);
1069
1070        // Exit state update mode to avoid accidental updating.
1071        thread[tid]->inSyscall = false;
1072
1073        commitStatus[tid] = TrapPending;
1074
1075        // Generate trap squash event.
1076        generateTrapEvent(tid);
1077//        warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1078        return false;
1079    }
1080
1081    updateComInstStats(head_inst);
1082
1083#if FULL_SYSTEM
1084    if (thread[tid]->profile) {
1085//        bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1086//        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1087        thread[tid]->profilePC = head_inst->readPC();
1088        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1089                                                          head_inst->staticInst);
1090
1091        if (node)
1092            thread[tid]->profileNode = node;
1093    }
1094#endif
1095
1096    if (head_inst->traceData) {
1097        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1098        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1099        head_inst->traceData->finalize();
1100        head_inst->traceData = NULL;
1101    }
1102
1103    // Update the commit rename map
1104    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1105        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1106                                 head_inst->renamedDestRegIdx(i));
1107    }
1108
1109    if (head_inst->isCopy())
1110        panic("Should not commit any copy instructions!");
1111
1112    // Finally clear the head ROB entry.
1113    rob->retireHead(tid);
1114
1115    // Return true to indicate that we have committed an instruction.
1116    return true;
1117}
1118
1119template <class Impl>
1120void
1121DefaultCommit<Impl>::getInsts()
1122{
1123    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1124
1125#if ISA_HAS_DELAY_SLOT
1126    // Read any renamed instructions and place them into the ROB.
1127    int insts_to_process = std::min((int)renameWidth,
1128                               (int)(fromRename->size + skidBuffer.size()));
1129    int rename_idx = 0;
1130
1131    DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1132            "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1133            skidBuffer.size());
1134#else
1135    // Read any renamed instructions and place them into the ROB.
1136    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1137#endif
1138
1139
1140    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1141        DynInstPtr inst;
1142
1143#if ISA_HAS_DELAY_SLOT
1144        // Get insts from skidBuffer or from Rename
1145        if (skidBuffer.size() > 0) {
1146            DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1147            inst = skidBuffer.front();
1148            skidBuffer.pop();
1149        } else {
1150            DPRINTF(Commit, "Grabbing rename inst.\n");
1151            inst = fromRename->insts[rename_idx++];
1152        }
1153#else
1154        inst = fromRename->insts[inst_num];
1155#endif
1156        int tid = inst->threadNumber;
1157
1158        if (!inst->isSquashed() &&
1159            commitStatus[tid] != ROBSquashing) {
1160            changedROBNumEntries[tid] = true;
1161
1162            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1163                    inst->readPC(), inst->seqNum, tid);
1164
1165            rob->insertInst(inst);
1166
1167            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1168
1169            youngestSeqNum[tid] = inst->seqNum;
1170        } else {
1171            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1172                    "squashed, skipping.\n",
1173                    inst->readPC(), inst->seqNum, tid);
1174        }
1175    }
1176
1177#if ISA_HAS_DELAY_SLOT
1178    if (rename_idx < fromRename->size) {
1179        DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1180
1181        for (;
1182             rename_idx < fromRename->size;
1183             rename_idx++) {
1184            DynInstPtr inst = fromRename->insts[rename_idx];
1185
1186            if (!inst->isSquashed()) {
1187                DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1188                        "skidBuffer.\n", inst->readPC(), inst->seqNum,
1189                        inst->threadNumber);
1190                skidBuffer.push(inst);
1191            } else {
1192                DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1193                        "squashed, skipping.\n",
1194                        inst->readPC(), inst->seqNum, inst->threadNumber);
1195            }
1196        }
1197    }
1198#endif
1199
1200}
1201
1202template <class Impl>
1203void
1204DefaultCommit<Impl>::skidInsert()
1205{
1206    DPRINTF(Commit, "Attempting to any instructions from rename into "
1207            "skidBuffer.\n");
1208
1209    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1210        DynInstPtr inst = fromRename->insts[inst_num];
1211
1212        if (!inst->isSquashed()) {
1213            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1214                    "skidBuffer.\n", inst->readPC(), inst->seqNum,
1215                    inst->threadNumber);
1216            skidBuffer.push(inst);
1217        } else {
1218            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1219                    "squashed, skipping.\n",
1220                    inst->readPC(), inst->seqNum, inst->threadNumber);
1221        }
1222    }
1223}
1224
1225template <class Impl>
1226void
1227DefaultCommit<Impl>::markCompletedInsts()
1228{
1229    // Grab completed insts out of the IEW instruction queue, and mark
1230    // instructions completed within the ROB.
1231    for (int inst_num = 0;
1232         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1233         ++inst_num)
1234    {
1235        if (!fromIEW->insts[inst_num]->isSquashed()) {
1236            DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1237                    "within ROB.\n",
1238                    fromIEW->insts[inst_num]->threadNumber,
1239                    fromIEW->insts[inst_num]->readPC(),
1240                    fromIEW->insts[inst_num]->seqNum);
1241
1242            // Mark the instruction as ready to commit.
1243            fromIEW->insts[inst_num]->setCanCommit();
1244        }
1245    }
1246}
1247
1248template <class Impl>
1249bool
1250DefaultCommit<Impl>::robDoneSquashing()
1251{
1252    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1253
1254    while (threads != (*activeThreads).end()) {
1255        unsigned tid = *threads++;
1256
1257        if (!rob->isDoneSquashing(tid))
1258            return false;
1259    }
1260
1261    return true;
1262}
1263
1264template <class Impl>
1265void
1266DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1267{
1268    unsigned thread = inst->threadNumber;
1269
1270    //
1271    //  Pick off the software prefetches
1272    //
1273#ifdef TARGET_ALPHA
1274    if (inst->isDataPrefetch()) {
1275        statComSwp[thread]++;
1276    } else {
1277        statComInst[thread]++;
1278    }
1279#else
1280    statComInst[thread]++;
1281#endif
1282
1283    //
1284    //  Control Instructions
1285    //
1286    if (inst->isControl())
1287        statComBranches[thread]++;
1288
1289    //
1290    //  Memory references
1291    //
1292    if (inst->isMemRef()) {
1293        statComRefs[thread]++;
1294
1295        if (inst->isLoad()) {
1296            statComLoads[thread]++;
1297        }
1298    }
1299
1300    if (inst->isMemBarrier()) {
1301        statComMembars[thread]++;
1302    }
1303}
1304
1305////////////////////////////////////////
1306//                                    //
1307//  SMT COMMIT POLICY MAINTAINED HERE //
1308//                                    //
1309////////////////////////////////////////
1310template <class Impl>
1311int
1312DefaultCommit<Impl>::getCommittingThread()
1313{
1314    if (numThreads > 1) {
1315        switch (commitPolicy) {
1316
1317          case Aggressive:
1318            //If Policy is Aggressive, commit will call
1319            //this function multiple times per
1320            //cycle
1321            return oldestReady();
1322
1323          case RoundRobin:
1324            return roundRobin();
1325
1326          case OldestReady:
1327            return oldestReady();
1328
1329          default:
1330            return -1;
1331        }
1332    } else {
1333        int tid = (*activeThreads).front();
1334
1335        if (commitStatus[tid] == Running ||
1336            commitStatus[tid] == Idle ||
1337            commitStatus[tid] == FetchTrapPending) {
1338            return tid;
1339        } else {
1340            return -1;
1341        }
1342    }
1343}
1344
1345template<class Impl>
1346int
1347DefaultCommit<Impl>::roundRobin()
1348{
1349    std::list<unsigned>::iterator pri_iter = priority_list.begin();
1350    std::list<unsigned>::iterator end      = priority_list.end();
1351
1352    while (pri_iter != end) {
1353        unsigned tid = *pri_iter;
1354
1355        if (commitStatus[tid] == Running ||
1356            commitStatus[tid] == Idle ||
1357            commitStatus[tid] == FetchTrapPending) {
1358
1359            if (rob->isHeadReady(tid)) {
1360                priority_list.erase(pri_iter);
1361                priority_list.push_back(tid);
1362
1363                return tid;
1364            }
1365        }
1366
1367        pri_iter++;
1368    }
1369
1370    return -1;
1371}
1372
1373template<class Impl>
1374int
1375DefaultCommit<Impl>::oldestReady()
1376{
1377    unsigned oldest = 0;
1378    bool first = true;
1379
1380    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1381
1382    while (threads != (*activeThreads).end()) {
1383        unsigned tid = *threads++;
1384
1385        if (!rob->isEmpty(tid) &&
1386            (commitStatus[tid] == Running ||
1387             commitStatus[tid] == Idle ||
1388             commitStatus[tid] == FetchTrapPending)) {
1389
1390            if (rob->isHeadReady(tid)) {
1391
1392                DynInstPtr head_inst = rob->readHeadInst(tid);
1393
1394                if (first) {
1395                    oldest = tid;
1396                    first = false;
1397                } else if (head_inst->seqNum < oldest) {
1398                    oldest = tid;
1399                }
1400            }
1401        }
1402    }
1403
1404    if (!first) {
1405        return oldest;
1406    } else {
1407        return -1;
1408    }
1409}
1410