commit_impl.hh revision 3791:f1783bae1afe 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51                                          unsigned _tid)
52    : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54    this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61    // This will get reset by commit if it was switched out at the
62    // time of this event processing.
63    commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70    return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75    : squashCounter(0),
76      iewToCommitDelay(params->iewToCommitDelay),
77      commitToIEWDelay(params->commitToIEWDelay),
78      renameToROBDelay(params->renameToROBDelay),
79      fetchToCommitDelay(params->commitToFetchDelay),
80      renameWidth(params->renameWidth),
81      commitWidth(params->commitWidth),
82      numThreads(params->numberOfThreads),
83      drainPending(false),
84      switchedOut(false),
85      trapLatency(params->trapLatency)
86{
87    _status = Active;
88    _nextStatus = Inactive;
89    std::string policy = params->smtCommitPolicy;
90
91    //Convert string to lowercase
92    std::transform(policy.begin(), policy.end(), policy.begin(),
93                   (int(*)(int)) tolower);
94
95    //Assign commit policy
96    if (policy == "aggressive"){
97        commitPolicy = Aggressive;
98
99        DPRINTF(Commit,"Commit Policy set to Aggressive.");
100    } else if (policy == "roundrobin"){
101        commitPolicy = RoundRobin;
102
103        //Set-Up Priority List
104        for (int tid=0; tid < numThreads; tid++) {
105            priority_list.push_back(tid);
106        }
107
108        DPRINTF(Commit,"Commit Policy set to Round Robin.");
109    } else if (policy == "oldestready"){
110        commitPolicy = OldestReady;
111
112        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113    } else {
114        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115               "RoundRobin,OldestReady}");
116    }
117
118    for (int i=0; i < numThreads; i++) {
119        commitStatus[i] = Idle;
120        changedROBNumEntries[i] = false;
121        trapSquash[i] = false;
122        tcSquash[i] = false;
123        PC[i] = nextPC[i] = nextNPC[i] = 0;
124    }
125#if FULL_SYSTEM
126    interrupt = NoFault;
127#endif
128}
129
130template <class Impl>
131std::string
132DefaultCommit<Impl>::name() const
133{
134    return cpu->name() + ".commit";
135}
136
137template <class Impl>
138void
139DefaultCommit<Impl>::regStats()
140{
141    using namespace Stats;
142    commitCommittedInsts
143        .name(name() + ".commitCommittedInsts")
144        .desc("The number of committed instructions")
145        .prereq(commitCommittedInsts);
146    commitSquashedInsts
147        .name(name() + ".commitSquashedInsts")
148        .desc("The number of squashed insts skipped by commit")
149        .prereq(commitSquashedInsts);
150    commitSquashEvents
151        .name(name() + ".commitSquashEvents")
152        .desc("The number of times commit is told to squash")
153        .prereq(commitSquashEvents);
154    commitNonSpecStalls
155        .name(name() + ".commitNonSpecStalls")
156        .desc("The number of times commit has been forced to stall to "
157              "communicate backwards")
158        .prereq(commitNonSpecStalls);
159    branchMispredicts
160        .name(name() + ".branchMispredicts")
161        .desc("The number of times a branch was mispredicted")
162        .prereq(branchMispredicts);
163    numCommittedDist
164        .init(0,commitWidth,1)
165        .name(name() + ".COM:committed_per_cycle")
166        .desc("Number of insts commited each cycle")
167        .flags(Stats::pdf)
168        ;
169
170    statComInst
171        .init(cpu->number_of_threads)
172        .name(name() + ".COM:count")
173        .desc("Number of instructions committed")
174        .flags(total)
175        ;
176
177    statComSwp
178        .init(cpu->number_of_threads)
179        .name(name() + ".COM:swp_count")
180        .desc("Number of s/w prefetches committed")
181        .flags(total)
182        ;
183
184    statComRefs
185        .init(cpu->number_of_threads)
186        .name(name() +  ".COM:refs")
187        .desc("Number of memory references committed")
188        .flags(total)
189        ;
190
191    statComLoads
192        .init(cpu->number_of_threads)
193        .name(name() +  ".COM:loads")
194        .desc("Number of loads committed")
195        .flags(total)
196        ;
197
198    statComMembars
199        .init(cpu->number_of_threads)
200        .name(name() +  ".COM:membars")
201        .desc("Number of memory barriers committed")
202        .flags(total)
203        ;
204
205    statComBranches
206        .init(cpu->number_of_threads)
207        .name(name() + ".COM:branches")
208        .desc("Number of branches committed")
209        .flags(total)
210        ;
211
212    commitEligible
213        .init(cpu->number_of_threads)
214        .name(name() + ".COM:bw_limited")
215        .desc("number of insts not committed due to BW limits")
216        .flags(total)
217        ;
218
219    commitEligibleSamples
220        .name(name() + ".COM:bw_lim_events")
221        .desc("number cycles where commit BW limit reached")
222        ;
223}
224
225template <class Impl>
226void
227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
228{
229    DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
230    cpu = cpu_ptr;
231
232    // Commit must broadcast the number of free entries it has at the start of
233    // the simulation, so it starts as active.
234    cpu->activateStage(O3CPU::CommitIdx);
235
236    trapLatency = cpu->cycles(trapLatency);
237}
238
239template <class Impl>
240void
241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
242{
243    thread = threads;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
250    DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
251    timeBuffer = tb_ptr;
252
253    // Setup wire to send information back to IEW.
254    toIEW = timeBuffer->getWire(0);
255
256    // Setup wire to read data from IEW (for the ROB).
257    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
258}
259
260template <class Impl>
261void
262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
263{
264    DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
265    fetchQueue = fq_ptr;
266
267    // Setup wire to get instructions from rename (for the ROB).
268    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
274{
275    DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276    renameQueue = rq_ptr;
277
278    // Setup wire to get instructions from rename (for the ROB).
279    fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286    DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
287    iewQueue = iq_ptr;
288
289    // Setup wire to get instructions from IEW.
290    fromIEW = iewQueue->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
296{
297    iewStage = iew_stage;
298}
299
300template<class Impl>
301void
302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
303{
304    DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305    activeThreads = at_ptr;
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
311{
312    DPRINTF(Commit, "Setting rename map pointers.\n");
313
314    for (int i=0; i < numThreads; i++) {
315        renameMap[i] = &rm_ptr[i];
316    }
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setROB(ROB *rob_ptr)
322{
323    DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324    rob = rob_ptr;
325}
326
327template <class Impl>
328void
329DefaultCommit<Impl>::initStage()
330{
331    rob->setActiveThreads(activeThreads);
332    rob->resetEntries();
333
334    // Broadcast the number of free entries.
335    for (int i=0; i < numThreads; i++) {
336        toIEW->commitInfo[i].usedROB = true;
337        toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
338    }
339
340    cpu->activityThisCycle();
341}
342
343template <class Impl>
344bool
345DefaultCommit<Impl>::drain()
346{
347    drainPending = true;
348
349    return false;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::switchOut()
355{
356    switchedOut = true;
357    drainPending = false;
358    rob->switchOut();
359}
360
361template <class Impl>
362void
363DefaultCommit<Impl>::resume()
364{
365    drainPending = false;
366}
367
368template <class Impl>
369void
370DefaultCommit<Impl>::takeOverFrom()
371{
372    switchedOut = false;
373    _status = Active;
374    _nextStatus = Inactive;
375    for (int i=0; i < numThreads; i++) {
376        commitStatus[i] = Idle;
377        changedROBNumEntries[i] = false;
378        trapSquash[i] = false;
379        tcSquash[i] = false;
380    }
381    squashCounter = 0;
382    rob->takeOverFrom();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::updateStatus()
388{
389    // reset ROB changed variable
390    std::list<unsigned>::iterator threads = (*activeThreads).begin();
391    while (threads != (*activeThreads).end()) {
392        unsigned tid = *threads++;
393        changedROBNumEntries[tid] = false;
394
395        // Also check if any of the threads has a trap pending
396        if (commitStatus[tid] == TrapPending ||
397            commitStatus[tid] == FetchTrapPending) {
398            _nextStatus = Active;
399        }
400    }
401
402    if (_nextStatus == Inactive && _status == Active) {
403        DPRINTF(Activity, "Deactivating stage.\n");
404        cpu->deactivateStage(O3CPU::CommitIdx);
405    } else if (_nextStatus == Active && _status == Inactive) {
406        DPRINTF(Activity, "Activating stage.\n");
407        cpu->activateStage(O3CPU::CommitIdx);
408    }
409
410    _status = _nextStatus;
411}
412
413template <class Impl>
414void
415DefaultCommit<Impl>::setNextStatus()
416{
417    int squashes = 0;
418
419    std::list<unsigned>::iterator threads = (*activeThreads).begin();
420
421    while (threads != (*activeThreads).end()) {
422        unsigned tid = *threads++;
423
424        if (commitStatus[tid] == ROBSquashing) {
425            squashes++;
426        }
427    }
428
429    squashCounter = squashes;
430
431    // If commit is currently squashing, then it will have activity for the
432    // next cycle. Set its next status as active.
433    if (squashCounter) {
434        _nextStatus = Active;
435    }
436}
437
438template <class Impl>
439bool
440DefaultCommit<Impl>::changedROBEntries()
441{
442    std::list<unsigned>::iterator threads = (*activeThreads).begin();
443
444    while (threads != (*activeThreads).end()) {
445        unsigned tid = *threads++;
446
447        if (changedROBNumEntries[tid]) {
448            return true;
449        }
450    }
451
452    return false;
453}
454
455template <class Impl>
456unsigned
457DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
458{
459    return rob->numFreeEntries(tid);
460}
461
462template <class Impl>
463void
464DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
465{
466    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
467
468    TrapEvent *trap = new TrapEvent(this, tid);
469
470    trap->schedule(curTick + trapLatency);
471
472    thread[tid]->trapPending = true;
473}
474
475template <class Impl>
476void
477DefaultCommit<Impl>::generateTCEvent(unsigned tid)
478{
479    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
480
481    tcSquash[tid] = true;
482}
483
484template <class Impl>
485void
486DefaultCommit<Impl>::squashAll(unsigned tid)
487{
488    // If we want to include the squashing instruction in the squash,
489    // then use one older sequence number.
490    // Hopefully this doesn't mess things up.  Basically I want to squash
491    // all instructions of this thread.
492    InstSeqNum squashed_inst = rob->isEmpty() ?
493        0 : rob->readHeadInst(tid)->seqNum - 1;;
494
495    // All younger instructions will be squashed. Set the sequence
496    // number as the youngest instruction in the ROB (0 in this case.
497    // Hopefully nothing breaks.)
498    youngestSeqNum[tid] = 0;
499
500    rob->squash(squashed_inst, tid);
501    changedROBNumEntries[tid] = true;
502
503    // Send back the sequence number of the squashed instruction.
504    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
505
506    // Send back the squash signal to tell stages that they should
507    // squash.
508    toIEW->commitInfo[tid].squash = true;
509
510    // Send back the rob squashing signal so other stages know that
511    // the ROB is in the process of squashing.
512    toIEW->commitInfo[tid].robSquashing = true;
513
514    toIEW->commitInfo[tid].branchMispredict = false;
515
516    toIEW->commitInfo[tid].nextPC = PC[tid];
517}
518
519template <class Impl>
520void
521DefaultCommit<Impl>::squashFromTrap(unsigned tid)
522{
523    squashAll(tid);
524
525    DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
526
527    thread[tid]->trapPending = false;
528    thread[tid]->inSyscall = false;
529
530    trapSquash[tid] = false;
531
532    commitStatus[tid] = ROBSquashing;
533    cpu->activityThisCycle();
534}
535
536template <class Impl>
537void
538DefaultCommit<Impl>::squashFromTC(unsigned tid)
539{
540    squashAll(tid);
541
542    DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
543
544    thread[tid]->inSyscall = false;
545    assert(!thread[tid]->trapPending);
546
547    commitStatus[tid] = ROBSquashing;
548    cpu->activityThisCycle();
549
550    tcSquash[tid] = false;
551}
552
553template <class Impl>
554void
555DefaultCommit<Impl>::tick()
556{
557    wroteToTimeBuffer = false;
558    _nextStatus = Inactive;
559
560    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
561        cpu->signalDrained();
562        drainPending = false;
563        return;
564    }
565
566    if ((*activeThreads).size() <= 0)
567        return;
568
569    std::list<unsigned>::iterator threads = (*activeThreads).begin();
570
571    // Check if any of the threads are done squashing.  Change the
572    // status if they are done.
573    while (threads != (*activeThreads).end()) {
574        unsigned tid = *threads++;
575
576        if (commitStatus[tid] == ROBSquashing) {
577
578            if (rob->isDoneSquashing(tid)) {
579                commitStatus[tid] = Running;
580            } else {
581                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
582                        " insts this cycle.\n", tid);
583                rob->doSquash(tid);
584                toIEW->commitInfo[tid].robSquashing = true;
585                wroteToTimeBuffer = true;
586            }
587        }
588    }
589
590    commit();
591
592    markCompletedInsts();
593
594    threads = (*activeThreads).begin();
595
596    while (threads != (*activeThreads).end()) {
597        unsigned tid = *threads++;
598
599        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
600            // The ROB has more instructions it can commit. Its next status
601            // will be active.
602            _nextStatus = Active;
603
604            DynInstPtr inst = rob->readHeadInst(tid);
605
606            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
607                    " ROB and ready to commit\n",
608                    tid, inst->seqNum, inst->readPC());
609
610        } else if (!rob->isEmpty(tid)) {
611            DynInstPtr inst = rob->readHeadInst(tid);
612
613            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
614                    "%#x is head of ROB and not ready\n",
615                    tid, inst->seqNum, inst->readPC());
616        }
617
618        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
619                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
620    }
621
622
623    if (wroteToTimeBuffer) {
624        DPRINTF(Activity, "Activity This Cycle.\n");
625        cpu->activityThisCycle();
626    }
627
628    updateStatus();
629}
630
631template <class Impl>
632void
633DefaultCommit<Impl>::commit()
634{
635
636    //////////////////////////////////////
637    // Check for interrupts
638    //////////////////////////////////////
639
640#if FULL_SYSTEM
641    if (interrupt != NoFault) {
642        // Wait until the ROB is empty and all stores have drained in
643        // order to enter the interrupt.
644        if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
645            // Squash or record that I need to squash this cycle if
646            // an interrupt needed to be handled.
647            DPRINTF(Commit, "Interrupt detected.\n");
648
649            assert(!thread[0]->inSyscall);
650            thread[0]->inSyscall = true;
651
652            // CPU will handle interrupt.
653            cpu->processInterrupts(interrupt);
654
655            thread[0]->inSyscall = false;
656
657            commitStatus[0] = TrapPending;
658
659            // Generate trap squash event.
660            generateTrapEvent(0);
661
662            // Clear the interrupt now that it's been handled
663            toIEW->commitInfo[0].clearInterrupt = true;
664            interrupt = NoFault;
665        } else {
666            DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
667        }
668    } else if (cpu->checkInterrupts &&
669        cpu->check_interrupts(cpu->tcBase(0)) &&
670        commitStatus[0] != TrapPending &&
671        !trapSquash[0] &&
672        !tcSquash[0]) {
673        // Process interrupts if interrupts are enabled, not in PAL
674        // mode, and no other traps or external squashes are currently
675        // pending.
676        // @todo: Allow other threads to handle interrupts.
677
678        // Get any interrupt that happened
679        interrupt = cpu->getInterrupts();
680
681        if (interrupt != NoFault) {
682            // Tell fetch that there is an interrupt pending.  This
683            // will make fetch wait until it sees a non PAL-mode PC,
684            // at which point it stops fetching instructions.
685            toIEW->commitInfo[0].interruptPending = true;
686        }
687    }
688
689#endif // FULL_SYSTEM
690
691    ////////////////////////////////////
692    // Check for any possible squashes, handle them first
693    ////////////////////////////////////
694    std::list<unsigned>::iterator threads = (*activeThreads).begin();
695
696    while (threads != (*activeThreads).end()) {
697        unsigned tid = *threads++;
698
699        // Not sure which one takes priority.  I think if we have
700        // both, that's a bad sign.
701        if (trapSquash[tid] == true) {
702            assert(!tcSquash[tid]);
703            squashFromTrap(tid);
704        } else if (tcSquash[tid] == true) {
705            squashFromTC(tid);
706        }
707
708        // Squashed sequence number must be older than youngest valid
709        // instruction in the ROB. This prevents squashes from younger
710        // instructions overriding squashes from older instructions.
711        if (fromIEW->squash[tid] &&
712            commitStatus[tid] != TrapPending &&
713            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
714
715            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
716                    tid,
717                    fromIEW->mispredPC[tid],
718                    fromIEW->squashedSeqNum[tid]);
719
720            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
721                    tid,
722                    fromIEW->nextPC[tid]);
723
724            commitStatus[tid] = ROBSquashing;
725
726            // If we want to include the squashing instruction in the squash,
727            // then use one older sequence number.
728            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
729
730#if ISA_HAS_DELAY_SLOT
731            InstSeqNum bdelay_done_seq_num = squashed_inst;
732            bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
733
734            if (!squash_bdelay_slot)
735                bdelay_done_seq_num++;
736#endif
737
738            if (fromIEW->includeSquashInst[tid] == true) {
739                squashed_inst--;
740#if ISA_HAS_DELAY_SLOT
741                bdelay_done_seq_num--;
742#endif
743            }
744            // All younger instructions will be squashed. Set the sequence
745            // number as the youngest instruction in the ROB.
746            youngestSeqNum[tid] = squashed_inst;
747
748#if ISA_HAS_DELAY_SLOT
749            rob->squash(bdelay_done_seq_num, tid);
750            toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
751            toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
752#else
753            rob->squash(squashed_inst, tid);
754            toIEW->commitInfo[tid].squashDelaySlot = true;
755#endif
756            changedROBNumEntries[tid] = true;
757
758            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
759
760            toIEW->commitInfo[tid].squash = true;
761
762            // Send back the rob squashing signal so other stages know that
763            // the ROB is in the process of squashing.
764            toIEW->commitInfo[tid].robSquashing = true;
765
766            toIEW->commitInfo[tid].branchMispredict =
767                fromIEW->branchMispredict[tid];
768
769            toIEW->commitInfo[tid].branchTaken =
770                fromIEW->branchTaken[tid];
771
772            toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
773
774            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
775
776            if (toIEW->commitInfo[tid].branchMispredict) {
777                ++branchMispredicts;
778            }
779        }
780
781    }
782
783    setNextStatus();
784
785    if (squashCounter != numThreads) {
786        // If we're not currently squashing, then get instructions.
787        getInsts();
788
789        // Try to commit any instructions.
790        commitInsts();
791    } else {
792#if ISA_HAS_DELAY_SLOT
793        skidInsert();
794#endif
795    }
796
797    //Check for any activity
798    threads = (*activeThreads).begin();
799
800    while (threads != (*activeThreads).end()) {
801        unsigned tid = *threads++;
802
803        if (changedROBNumEntries[tid]) {
804            toIEW->commitInfo[tid].usedROB = true;
805            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
806
807            if (rob->isEmpty(tid)) {
808                toIEW->commitInfo[tid].emptyROB = true;
809            }
810
811            wroteToTimeBuffer = true;
812            changedROBNumEntries[tid] = false;
813        }
814    }
815}
816
817template <class Impl>
818void
819DefaultCommit<Impl>::commitInsts()
820{
821    ////////////////////////////////////
822    // Handle commit
823    // Note that commit will be handled prior to putting new
824    // instructions in the ROB so that the ROB only tries to commit
825    // instructions it has in this current cycle, and not instructions
826    // it is writing in during this cycle.  Can't commit and squash
827    // things at the same time...
828    ////////////////////////////////////
829
830    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
831
832    unsigned num_committed = 0;
833
834    DynInstPtr head_inst;
835
836    // Commit as many instructions as possible until the commit bandwidth
837    // limit is reached, or it becomes impossible to commit any more.
838    while (num_committed < commitWidth) {
839        int commit_thread = getCommittingThread();
840
841        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
842            break;
843
844        head_inst = rob->readHeadInst(commit_thread);
845
846        int tid = head_inst->threadNumber;
847
848        assert(tid == commit_thread);
849
850        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
851                head_inst->seqNum, tid);
852
853        // If the head instruction is squashed, it is ready to retire
854        // (be removed from the ROB) at any time.
855        if (head_inst->isSquashed()) {
856
857            DPRINTF(Commit, "Retiring squashed instruction from "
858                    "ROB.\n");
859
860            rob->retireHead(commit_thread);
861
862            ++commitSquashedInsts;
863
864            // Record that the number of ROB entries has changed.
865            changedROBNumEntries[tid] = true;
866        } else {
867            PC[tid] = head_inst->readPC();
868            nextPC[tid] = head_inst->readNextPC();
869            nextNPC[tid] = head_inst->readNextNPC();
870
871            // Increment the total number of non-speculative instructions
872            // executed.
873            // Hack for now: it really shouldn't happen until after the
874            // commit is deemed to be successful, but this count is needed
875            // for syscalls.
876            thread[tid]->funcExeInst++;
877
878            // Try to commit the head instruction.
879            bool commit_success = commitHead(head_inst, num_committed);
880
881            if (commit_success) {
882                ++num_committed;
883
884                changedROBNumEntries[tid] = true;
885
886                // Set the doneSeqNum to the youngest committed instruction.
887                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
888
889                ++commitCommittedInsts;
890
891                // To match the old model, don't count nops and instruction
892                // prefetches towards the total commit count.
893                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
894                    cpu->instDone(tid);
895                }
896
897                PC[tid] = nextPC[tid];
898#if ISA_HAS_DELAY_SLOT
899                nextPC[tid] = nextNPC[tid];
900                nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
901#else
902                nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
903#endif
904
905#if FULL_SYSTEM
906                int count = 0;
907                Addr oldpc;
908                do {
909                    // Debug statement.  Checks to make sure we're not
910                    // currently updating state while handling PC events.
911                    if (count == 0)
912                        assert(!thread[tid]->inSyscall &&
913                               !thread[tid]->trapPending);
914                    oldpc = PC[tid];
915                    cpu->system->pcEventQueue.service(
916                        thread[tid]->getTC());
917                    count++;
918                } while (oldpc != PC[tid]);
919                if (count > 1) {
920                    DPRINTF(Commit, "PC skip function event, stopping commit\n");
921                    break;
922                }
923#endif
924            } else {
925                DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
926                        "[tid:%i] [sn:%i].\n",
927                        head_inst->readPC(), tid ,head_inst->seqNum);
928                break;
929            }
930        }
931    }
932
933    DPRINTF(CommitRate, "%i\n", num_committed);
934    numCommittedDist.sample(num_committed);
935
936    if (num_committed == commitWidth) {
937        commitEligibleSamples++;
938    }
939}
940
941template <class Impl>
942bool
943DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
944{
945    assert(head_inst);
946
947    int tid = head_inst->threadNumber;
948
949    // If the instruction is not executed yet, then it will need extra
950    // handling.  Signal backwards that it should be executed.
951    if (!head_inst->isExecuted()) {
952        // Keep this number correct.  We have not yet actually executed
953        // and committed this instruction.
954        thread[tid]->funcExeInst--;
955
956        head_inst->setAtCommit();
957
958        if (head_inst->isNonSpeculative() ||
959            head_inst->isStoreConditional() ||
960            head_inst->isMemBarrier() ||
961            head_inst->isWriteBarrier()) {
962
963            DPRINTF(Commit, "Encountered a barrier or non-speculative "
964                    "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
965                    head_inst->seqNum, head_inst->readPC());
966
967#if !FULL_SYSTEM
968            // Hack to make sure syscalls/memory barriers/quiesces
969            // aren't executed until all stores write back their data.
970            // This direct communication shouldn't be used for
971            // anything other than this.
972            if (inst_num > 0 || iewStage->hasStoresToWB())
973#else
974            if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
975                    head_inst->isQuiesce()) &&
976                iewStage->hasStoresToWB())
977#endif
978            {
979                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
980                return false;
981            }
982
983            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
984
985            // Change the instruction so it won't try to commit again until
986            // it is executed.
987            head_inst->clearCanCommit();
988
989            ++commitNonSpecStalls;
990
991            return false;
992        } else if (head_inst->isLoad()) {
993            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
994                    head_inst->seqNum, head_inst->readPC());
995
996            // Send back the non-speculative instruction's sequence
997            // number.  Tell the lsq to re-execute the load.
998            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
999            toIEW->commitInfo[tid].uncached = true;
1000            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1001
1002            head_inst->clearCanCommit();
1003
1004            return false;
1005        } else {
1006            panic("Trying to commit un-executed instruction "
1007                  "of unknown type!\n");
1008        }
1009    }
1010
1011    if (head_inst->isThreadSync()) {
1012        // Not handled for now.
1013        panic("Thread sync instructions are not handled yet.\n");
1014    }
1015
1016    // Stores mark themselves as completed.
1017    if (!head_inst->isStore()) {
1018        head_inst->setCompleted();
1019    }
1020
1021#if USE_CHECKER
1022    // Use checker prior to updating anything due to traps or PC
1023    // based events.
1024    if (cpu->checker) {
1025        cpu->checker->verify(head_inst);
1026    }
1027#endif
1028
1029    // Check if the instruction caused a fault.  If so, trap.
1030    Fault inst_fault = head_inst->getFault();
1031
1032    // DTB will sometimes need the machine instruction for when
1033    // faults happen.  So we will set it here, prior to the DTB
1034    // possibly needing it for its fault.
1035    thread[tid]->setInst(
1036        static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1037
1038    if (inst_fault != NoFault) {
1039        head_inst->setCompleted();
1040        DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1041                head_inst->seqNum, head_inst->readPC());
1042
1043        if (iewStage->hasStoresToWB() || inst_num > 0) {
1044            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1045            return false;
1046        }
1047
1048#if USE_CHECKER
1049        if (cpu->checker && head_inst->isStore()) {
1050            cpu->checker->verify(head_inst);
1051        }
1052#endif
1053
1054        assert(!thread[tid]->inSyscall);
1055
1056        // Mark that we're in state update mode so that the trap's
1057        // execution doesn't generate extra squashes.
1058        thread[tid]->inSyscall = true;
1059
1060        // Execute the trap.  Although it's slightly unrealistic in
1061        // terms of timing (as it doesn't wait for the full timing of
1062        // the trap event to complete before updating state), it's
1063        // needed to update the state as soon as possible.  This
1064        // prevents external agents from changing any specific state
1065        // that the trap need.
1066        cpu->trap(inst_fault, tid);
1067
1068        // Exit state update mode to avoid accidental updating.
1069        thread[tid]->inSyscall = false;
1070
1071        commitStatus[tid] = TrapPending;
1072
1073        // Generate trap squash event.
1074        generateTrapEvent(tid);
1075//        warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1076        return false;
1077    }
1078
1079    updateComInstStats(head_inst);
1080
1081#if FULL_SYSTEM
1082    if (thread[tid]->profile) {
1083//        bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1084//        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1085        thread[tid]->profilePC = head_inst->readPC();
1086        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1087                                                          head_inst->staticInst);
1088
1089        if (node)
1090            thread[tid]->profileNode = node;
1091    }
1092#endif
1093
1094    if (head_inst->traceData) {
1095        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1096        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1097        head_inst->traceData->finalize();
1098        head_inst->traceData = NULL;
1099    }
1100
1101    // Update the commit rename map
1102    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1103        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1104                                 head_inst->renamedDestRegIdx(i));
1105    }
1106
1107    if (head_inst->isCopy())
1108        panic("Should not commit any copy instructions!");
1109
1110    // Finally clear the head ROB entry.
1111    rob->retireHead(tid);
1112
1113    // Return true to indicate that we have committed an instruction.
1114    return true;
1115}
1116
1117template <class Impl>
1118void
1119DefaultCommit<Impl>::getInsts()
1120{
1121    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1122
1123#if ISA_HAS_DELAY_SLOT
1124    // Read any renamed instructions and place them into the ROB.
1125    int insts_to_process = std::min((int)renameWidth,
1126                               (int)(fromRename->size + skidBuffer.size()));
1127    int rename_idx = 0;
1128
1129    DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1130            "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1131            skidBuffer.size());
1132#else
1133    // Read any renamed instructions and place them into the ROB.
1134    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1135#endif
1136
1137
1138    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1139        DynInstPtr inst;
1140
1141#if ISA_HAS_DELAY_SLOT
1142        // Get insts from skidBuffer or from Rename
1143        if (skidBuffer.size() > 0) {
1144            DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1145            inst = skidBuffer.front();
1146            skidBuffer.pop();
1147        } else {
1148            DPRINTF(Commit, "Grabbing rename inst.\n");
1149            inst = fromRename->insts[rename_idx++];
1150        }
1151#else
1152        inst = fromRename->insts[inst_num];
1153#endif
1154        int tid = inst->threadNumber;
1155
1156        if (!inst->isSquashed() &&
1157            commitStatus[tid] != ROBSquashing) {
1158            changedROBNumEntries[tid] = true;
1159
1160            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1161                    inst->readPC(), inst->seqNum, tid);
1162
1163            rob->insertInst(inst);
1164
1165            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1166
1167            youngestSeqNum[tid] = inst->seqNum;
1168        } else {
1169            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1170                    "squashed, skipping.\n",
1171                    inst->readPC(), inst->seqNum, tid);
1172        }
1173    }
1174
1175#if ISA_HAS_DELAY_SLOT
1176    if (rename_idx < fromRename->size) {
1177        DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1178
1179        for (;
1180             rename_idx < fromRename->size;
1181             rename_idx++) {
1182            DynInstPtr inst = fromRename->insts[rename_idx];
1183
1184            if (!inst->isSquashed()) {
1185                DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1186                        "skidBuffer.\n", inst->readPC(), inst->seqNum,
1187                        inst->threadNumber);
1188                skidBuffer.push(inst);
1189            } else {
1190                DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1191                        "squashed, skipping.\n",
1192                        inst->readPC(), inst->seqNum, inst->threadNumber);
1193            }
1194        }
1195    }
1196#endif
1197
1198}
1199
1200template <class Impl>
1201void
1202DefaultCommit<Impl>::skidInsert()
1203{
1204    DPRINTF(Commit, "Attempting to any instructions from rename into "
1205            "skidBuffer.\n");
1206
1207    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1208        DynInstPtr inst = fromRename->insts[inst_num];
1209
1210        if (!inst->isSquashed()) {
1211            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1212                    "skidBuffer.\n", inst->readPC(), inst->seqNum,
1213                    inst->threadNumber);
1214            skidBuffer.push(inst);
1215        } else {
1216            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1217                    "squashed, skipping.\n",
1218                    inst->readPC(), inst->seqNum, inst->threadNumber);
1219        }
1220    }
1221}
1222
1223template <class Impl>
1224void
1225DefaultCommit<Impl>::markCompletedInsts()
1226{
1227    // Grab completed insts out of the IEW instruction queue, and mark
1228    // instructions completed within the ROB.
1229    for (int inst_num = 0;
1230         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1231         ++inst_num)
1232    {
1233        if (!fromIEW->insts[inst_num]->isSquashed()) {
1234            DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1235                    "within ROB.\n",
1236                    fromIEW->insts[inst_num]->threadNumber,
1237                    fromIEW->insts[inst_num]->readPC(),
1238                    fromIEW->insts[inst_num]->seqNum);
1239
1240            // Mark the instruction as ready to commit.
1241            fromIEW->insts[inst_num]->setCanCommit();
1242        }
1243    }
1244}
1245
1246template <class Impl>
1247bool
1248DefaultCommit<Impl>::robDoneSquashing()
1249{
1250    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1251
1252    while (threads != (*activeThreads).end()) {
1253        unsigned tid = *threads++;
1254
1255        if (!rob->isDoneSquashing(tid))
1256            return false;
1257    }
1258
1259    return true;
1260}
1261
1262template <class Impl>
1263void
1264DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1265{
1266    unsigned thread = inst->threadNumber;
1267
1268    //
1269    //  Pick off the software prefetches
1270    //
1271#ifdef TARGET_ALPHA
1272    if (inst->isDataPrefetch()) {
1273        statComSwp[thread]++;
1274    } else {
1275        statComInst[thread]++;
1276    }
1277#else
1278    statComInst[thread]++;
1279#endif
1280
1281    //
1282    //  Control Instructions
1283    //
1284    if (inst->isControl())
1285        statComBranches[thread]++;
1286
1287    //
1288    //  Memory references
1289    //
1290    if (inst->isMemRef()) {
1291        statComRefs[thread]++;
1292
1293        if (inst->isLoad()) {
1294            statComLoads[thread]++;
1295        }
1296    }
1297
1298    if (inst->isMemBarrier()) {
1299        statComMembars[thread]++;
1300    }
1301}
1302
1303////////////////////////////////////////
1304//                                    //
1305//  SMT COMMIT POLICY MAINTAINED HERE //
1306//                                    //
1307////////////////////////////////////////
1308template <class Impl>
1309int
1310DefaultCommit<Impl>::getCommittingThread()
1311{
1312    if (numThreads > 1) {
1313        switch (commitPolicy) {
1314
1315          case Aggressive:
1316            //If Policy is Aggressive, commit will call
1317            //this function multiple times per
1318            //cycle
1319            return oldestReady();
1320
1321          case RoundRobin:
1322            return roundRobin();
1323
1324          case OldestReady:
1325            return oldestReady();
1326
1327          default:
1328            return -1;
1329        }
1330    } else {
1331        int tid = (*activeThreads).front();
1332
1333        if (commitStatus[tid] == Running ||
1334            commitStatus[tid] == Idle ||
1335            commitStatus[tid] == FetchTrapPending) {
1336            return tid;
1337        } else {
1338            return -1;
1339        }
1340    }
1341}
1342
1343template<class Impl>
1344int
1345DefaultCommit<Impl>::roundRobin()
1346{
1347    std::list<unsigned>::iterator pri_iter = priority_list.begin();
1348    std::list<unsigned>::iterator end      = priority_list.end();
1349
1350    while (pri_iter != end) {
1351        unsigned tid = *pri_iter;
1352
1353        if (commitStatus[tid] == Running ||
1354            commitStatus[tid] == Idle ||
1355            commitStatus[tid] == FetchTrapPending) {
1356
1357            if (rob->isHeadReady(tid)) {
1358                priority_list.erase(pri_iter);
1359                priority_list.push_back(tid);
1360
1361                return tid;
1362            }
1363        }
1364
1365        pri_iter++;
1366    }
1367
1368    return -1;
1369}
1370
1371template<class Impl>
1372int
1373DefaultCommit<Impl>::oldestReady()
1374{
1375    unsigned oldest = 0;
1376    bool first = true;
1377
1378    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1379
1380    while (threads != (*activeThreads).end()) {
1381        unsigned tid = *threads++;
1382
1383        if (!rob->isEmpty(tid) &&
1384            (commitStatus[tid] == Running ||
1385             commitStatus[tid] == Idle ||
1386             commitStatus[tid] == FetchTrapPending)) {
1387
1388            if (rob->isHeadReady(tid)) {
1389
1390                DynInstPtr head_inst = rob->readHeadInst(tid);
1391
1392                if (first) {
1393                    oldest = tid;
1394                    first = false;
1395                } else if (head_inst->seqNum < oldest) {
1396                    oldest = tid;
1397                }
1398            }
1399        }
1400    }
1401
1402    if (!first) {
1403        return oldest;
1404    } else {
1405        return -1;
1406    }
1407}
1408