commit_impl.hh revision 3640:3a2f7b451641
12889Sbinkertn@umich.edu/* 22889Sbinkertn@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32889Sbinkertn@umich.edu * All rights reserved. 42889Sbinkertn@umich.edu * 52889Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 62889Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 72889Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 82889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 92889Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 102889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 112889Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 122889Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 132889Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 142889Sbinkertn@umich.edu * this software without specific prior written permission. 152889Sbinkertn@umich.edu * 162889Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172889Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182889Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192889Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202889Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212889Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222889Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232889Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242889Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252889Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262889Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272889Sbinkertn@umich.edu * 282889Sbinkertn@umich.edu * Authors: Kevin Lim 292889Sbinkertn@umich.edu * Korey Sewell 302889Sbinkertn@umich.edu */ 312889Sbinkertn@umich.edu 324053Sbinkertn@umich.edu#include "config/full_system.hh" 332889Sbinkertn@umich.edu#include "config/use_checker.hh" 342889Sbinkertn@umich.edu 352889Sbinkertn@umich.edu#include <algorithm> 362889Sbinkertn@umich.edu#include <string> 372889Sbinkertn@umich.edu 382889Sbinkertn@umich.edu#include "arch/utility.hh" 392889Sbinkertn@umich.edu#include "base/loader/symtab.hh" 402889Sbinkertn@umich.edu#include "base/timebuf.hh" 412889Sbinkertn@umich.edu#include "cpu/exetrace.hh" 422889Sbinkertn@umich.edu#include "cpu/o3/commit.hh" 432889Sbinkertn@umich.edu#include "cpu/o3/thread_state.hh" 444053Sbinkertn@umich.edu 454053Sbinkertn@umich.edu#if USE_CHECKER 464053Sbinkertn@umich.edu#include "cpu/checker/cpu.hh" 474053Sbinkertn@umich.edu#endif 484053Sbinkertn@umich.edu 494053Sbinkertn@umich.edutemplate <class Impl> 504053Sbinkertn@umich.eduDefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 514053Sbinkertn@umich.edu unsigned _tid) 524053Sbinkertn@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 534053Sbinkertn@umich.edu{ 544053Sbinkertn@umich.edu this->setFlags(Event::AutoDelete); 554053Sbinkertn@umich.edu} 564053Sbinkertn@umich.edu 572889Sbinkertn@umich.edutemplate <class Impl> 582889Sbinkertn@umich.eduvoid 592889Sbinkertn@umich.eduDefaultCommit<Impl>::TrapEvent::process() 602889Sbinkertn@umich.edu{ 612889Sbinkertn@umich.edu // This will get reset by commit if it was switched out at the 622890Sbinkertn@umich.edu // time of this event processing. 632889Sbinkertn@umich.edu commit->trapSquash[tid] = true; 642889Sbinkertn@umich.edu} 652889Sbinkertn@umich.edu 662889Sbinkertn@umich.edutemplate <class Impl> 672889Sbinkertn@umich.educonst char * 682889Sbinkertn@umich.eduDefaultCommit<Impl>::TrapEvent::description() 692889Sbinkertn@umich.edu{ 702889Sbinkertn@umich.edu return "Trap event"; 712889Sbinkertn@umich.edu} 722889Sbinkertn@umich.edu 732889Sbinkertn@umich.edutemplate <class Impl> 742889Sbinkertn@umich.eduDefaultCommit<Impl>::DefaultCommit(Params *params) 752889Sbinkertn@umich.edu : squashCounter(0), 762889Sbinkertn@umich.edu iewToCommitDelay(params->iewToCommitDelay), 772889Sbinkertn@umich.edu commitToIEWDelay(params->commitToIEWDelay), 782889Sbinkertn@umich.edu renameToROBDelay(params->renameToROBDelay), 792889Sbinkertn@umich.edu fetchToCommitDelay(params->commitToFetchDelay), 802889Sbinkertn@umich.edu renameWidth(params->renameWidth), 812889Sbinkertn@umich.edu commitWidth(params->commitWidth), 822889Sbinkertn@umich.edu numThreads(params->numberOfThreads), 832889Sbinkertn@umich.edu drainPending(false), 842889Sbinkertn@umich.edu switchedOut(false), 852889Sbinkertn@umich.edu trapLatency(params->trapLatency) 862889Sbinkertn@umich.edu{ 872889Sbinkertn@umich.edu _status = Active; 882889Sbinkertn@umich.edu _nextStatus = Inactive; 892889Sbinkertn@umich.edu std::string policy = params->smtCommitPolicy; 902889Sbinkertn@umich.edu 912889Sbinkertn@umich.edu //Convert string to lowercase 922889Sbinkertn@umich.edu std::transform(policy.begin(), policy.end(), policy.begin(), 932889Sbinkertn@umich.edu (int(*)(int)) tolower); 942889Sbinkertn@umich.edu 952889Sbinkertn@umich.edu //Assign commit policy 962889Sbinkertn@umich.edu if (policy == "aggressive"){ 972889Sbinkertn@umich.edu commitPolicy = Aggressive; 982889Sbinkertn@umich.edu 992889Sbinkertn@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1002889Sbinkertn@umich.edu } else if (policy == "roundrobin"){ 1012889Sbinkertn@umich.edu commitPolicy = RoundRobin; 1022889Sbinkertn@umich.edu 1032889Sbinkertn@umich.edu //Set-Up Priority List 1042889Sbinkertn@umich.edu for (int tid=0; tid < numThreads; tid++) { 1052889Sbinkertn@umich.edu priority_list.push_back(tid); 1062889Sbinkertn@umich.edu } 1072889Sbinkertn@umich.edu 1082889Sbinkertn@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1092889Sbinkertn@umich.edu } else if (policy == "oldestready"){ 1102889Sbinkertn@umich.edu commitPolicy = OldestReady; 1112889Sbinkertn@umich.edu 1122889Sbinkertn@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1132889Sbinkertn@umich.edu } else { 1142889Sbinkertn@umich.edu assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1152889Sbinkertn@umich.edu "RoundRobin,OldestReady}"); 1162889Sbinkertn@umich.edu } 1172889Sbinkertn@umich.edu 1182889Sbinkertn@umich.edu for (int i=0; i < numThreads; i++) { 1192889Sbinkertn@umich.edu commitStatus[i] = Idle; 1202889Sbinkertn@umich.edu changedROBNumEntries[i] = false; 1212889Sbinkertn@umich.edu trapSquash[i] = false; 1222889Sbinkertn@umich.edu tcSquash[i] = false; 1232889Sbinkertn@umich.edu PC[i] = nextPC[i] = nextNPC[i] = 0; 1242889Sbinkertn@umich.edu } 1252889Sbinkertn@umich.edu#if FULL_SYSTEM 1262889Sbinkertn@umich.edu interrupt = NoFault; 1272889Sbinkertn@umich.edu#endif 1282889Sbinkertn@umich.edu} 1292889Sbinkertn@umich.edu 1302889Sbinkertn@umich.edutemplate <class Impl> 1312899Sbinkertn@umich.edustd::string 1322899Sbinkertn@umich.eduDefaultCommit<Impl>::name() const 1332889Sbinkertn@umich.edu{ 1342889Sbinkertn@umich.edu return cpu->name() + ".commit"; 1352889Sbinkertn@umich.edu} 1362889Sbinkertn@umich.edu 1372889Sbinkertn@umich.edutemplate <class Impl> 1382889Sbinkertn@umich.eduvoid 1392889Sbinkertn@umich.eduDefaultCommit<Impl>::regStats() 1402889Sbinkertn@umich.edu{ 1412889Sbinkertn@umich.edu using namespace Stats; 1422889Sbinkertn@umich.edu commitCommittedInsts 1432889Sbinkertn@umich.edu .name(name() + ".commitCommittedInsts") 1442889Sbinkertn@umich.edu .desc("The number of committed instructions") 1452889Sbinkertn@umich.edu .prereq(commitCommittedInsts); 1462889Sbinkertn@umich.edu commitSquashedInsts 1472889Sbinkertn@umich.edu .name(name() + ".commitSquashedInsts") 1482889Sbinkertn@umich.edu .desc("The number of squashed insts skipped by commit") 1492889Sbinkertn@umich.edu .prereq(commitSquashedInsts); 1502889Sbinkertn@umich.edu commitSquashEvents 1512889Sbinkertn@umich.edu .name(name() + ".commitSquashEvents") 1524053Sbinkertn@umich.edu .desc("The number of times commit is told to squash") 1534053Sbinkertn@umich.edu .prereq(commitSquashEvents); 1542889Sbinkertn@umich.edu commitNonSpecStalls 1554053Sbinkertn@umich.edu .name(name() + ".commitNonSpecStalls") 1564044Sbinkertn@umich.edu .desc("The number of times commit has been forced to stall to " 1574044Sbinkertn@umich.edu "communicate backwards") 1582889Sbinkertn@umich.edu .prereq(commitNonSpecStalls); 1592889Sbinkertn@umich.edu branchMispredicts 1602889Sbinkertn@umich.edu .name(name() + ".branchMispredicts") 1612889Sbinkertn@umich.edu .desc("The number of times a branch was mispredicted") 1622889Sbinkertn@umich.edu .prereq(branchMispredicts); 1632889Sbinkertn@umich.edu numCommittedDist 1642889Sbinkertn@umich.edu .init(0,commitWidth,1) 1652889Sbinkertn@umich.edu .name(name() + ".COM:committed_per_cycle") 1662889Sbinkertn@umich.edu .desc("Number of insts commited each cycle") 1672903Ssaidi@eecs.umich.edu .flags(Stats::pdf) 1682889Sbinkertn@umich.edu ; 1692889Sbinkertn@umich.edu 1702889Sbinkertn@umich.edu statComInst 1712889Sbinkertn@umich.edu .init(cpu->number_of_threads) 1722889Sbinkertn@umich.edu .name(name() + ".COM:count") 1732889Sbinkertn@umich.edu .desc("Number of instructions committed") 1742889Sbinkertn@umich.edu .flags(total) 1752889Sbinkertn@umich.edu ; 1762889Sbinkertn@umich.edu 1772889Sbinkertn@umich.edu statComSwp 1782889Sbinkertn@umich.edu .init(cpu->number_of_threads) 1792889Sbinkertn@umich.edu .name(name() + ".COM:swp_count") 1802889Sbinkertn@umich.edu .desc("Number of s/w prefetches committed") 1812889Sbinkertn@umich.edu .flags(total) 1822889Sbinkertn@umich.edu ; 1832889Sbinkertn@umich.edu 1842889Sbinkertn@umich.edu statComRefs 1852889Sbinkertn@umich.edu .init(cpu->number_of_threads) 1862889Sbinkertn@umich.edu .name(name() + ".COM:refs") 1872889Sbinkertn@umich.edu .desc("Number of memory references committed") 1882889Sbinkertn@umich.edu .flags(total) 1892889Sbinkertn@umich.edu ; 1904042Sbinkertn@umich.edu 1914042Sbinkertn@umich.edu statComLoads 1923624Sbinkertn@umich.edu .init(cpu->number_of_threads) 1932889Sbinkertn@umich.edu .name(name() + ".COM:loads") 1942889Sbinkertn@umich.edu .desc("Number of loads committed") 1952889Sbinkertn@umich.edu .flags(total) 1962889Sbinkertn@umich.edu ; 1972889Sbinkertn@umich.edu 1982889Sbinkertn@umich.edu statComMembars 1992889Sbinkertn@umich.edu .init(cpu->number_of_threads) 2002889Sbinkertn@umich.edu .name(name() + ".COM:membars") 2012889Sbinkertn@umich.edu .desc("Number of memory barriers committed") 2022889Sbinkertn@umich.edu .flags(total) 2032889Sbinkertn@umich.edu ; 2042889Sbinkertn@umich.edu 2052889Sbinkertn@umich.edu statComBranches 2062889Sbinkertn@umich.edu .init(cpu->number_of_threads) 2072889Sbinkertn@umich.edu .name(name() + ".COM:branches") 2082889Sbinkertn@umich.edu .desc("Number of branches committed") 2092889Sbinkertn@umich.edu .flags(total) 2102889Sbinkertn@umich.edu ; 2112889Sbinkertn@umich.edu 2122889Sbinkertn@umich.edu commitEligible 2132889Sbinkertn@umich.edu .init(cpu->number_of_threads) 2142889Sbinkertn@umich.edu .name(name() + ".COM:bw_limited") 2152889Sbinkertn@umich.edu .desc("number of insts not committed due to BW limits") 2162889Sbinkertn@umich.edu .flags(total) 2172889Sbinkertn@umich.edu ; 2182889Sbinkertn@umich.edu 2192889Sbinkertn@umich.edu commitEligibleSamples 2202889Sbinkertn@umich.edu .name(name() + ".COM:bw_lim_events") 2212889Sbinkertn@umich.edu .desc("number cycles where commit BW limit reached") 2222889Sbinkertn@umich.edu ; 2234053Sbinkertn@umich.edu} 2244053Sbinkertn@umich.edu 2254053Sbinkertn@umich.edutemplate <class Impl> 2264053Sbinkertn@umich.eduvoid 2274053Sbinkertn@umich.eduDefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 2284053Sbinkertn@umich.edu{ 2294053Sbinkertn@umich.edu DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2304053Sbinkertn@umich.edu cpu = cpu_ptr; 2314053Sbinkertn@umich.edu 2324053Sbinkertn@umich.edu // Commit must broadcast the number of free entries it has at the start of 2334053Sbinkertn@umich.edu // the simulation, so it starts as active. 2344053Sbinkertn@umich.edu cpu->activateStage(O3CPU::CommitIdx); 2354053Sbinkertn@umich.edu 2362889Sbinkertn@umich.edu trapLatency = cpu->cycles(trapLatency); 2372889Sbinkertn@umich.edu} 2382889Sbinkertn@umich.edu 2392889Sbinkertn@umich.edutemplate <class Impl> 2402889Sbinkertn@umich.eduvoid 2412889Sbinkertn@umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2422889Sbinkertn@umich.edu{ 2433624Sbinkertn@umich.edu thread = threads; 2442889Sbinkertn@umich.edu} 2452889Sbinkertn@umich.edu 2462967Sktlim@umich.edutemplate <class Impl> 2472967Sktlim@umich.eduvoid 2482967Sktlim@umich.eduDefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2492967Sktlim@umich.edu{ 2502889Sbinkertn@umich.edu DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2512889Sbinkertn@umich.edu timeBuffer = tb_ptr; 2522889Sbinkertn@umich.edu 2532922Sktlim@umich.edu // Setup wire to send information back to IEW. 2542922Sktlim@umich.edu toIEW = timeBuffer->getWire(0); 2554053Sbinkertn@umich.edu 2562889Sbinkertn@umich.edu // Setup wire to read data from IEW (for the ROB). 2572889Sbinkertn@umich.edu robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2582889Sbinkertn@umich.edu} 2593624Sbinkertn@umich.edu 2602889Sbinkertn@umich.edutemplate <class Impl> 2612889Sbinkertn@umich.eduvoid 2622889Sbinkertn@umich.eduDefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2632889Sbinkertn@umich.edu{ 2642889Sbinkertn@umich.edu DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2652889Sbinkertn@umich.edu fetchQueue = fq_ptr; 2662889Sbinkertn@umich.edu 2674078Sbinkertn@umich.edu // Setup wire to get instructions from rename (for the ROB). 2682889Sbinkertn@umich.edu fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2692889Sbinkertn@umich.edu} 2703645Sbinkertn@umich.edu 2713645Sbinkertn@umich.edutemplate <class Impl> 2722889Sbinkertn@umich.eduvoid 2734053Sbinkertn@umich.eduDefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2744053Sbinkertn@umich.edu{ 2754042Sbinkertn@umich.edu DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2764053Sbinkertn@umich.edu renameQueue = rq_ptr; 2774053Sbinkertn@umich.edu 2784053Sbinkertn@umich.edu // Setup wire to get instructions from rename (for the ROB). 2794053Sbinkertn@umich.edu fromRename = renameQueue->getWire(-renameToROBDelay); 2804053Sbinkertn@umich.edu} 2814053Sbinkertn@umich.edu 2824053Sbinkertn@umich.edutemplate <class Impl> 2834053Sbinkertn@umich.eduvoid 2844053Sbinkertn@umich.eduDefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2854053Sbinkertn@umich.edu{ 2864053Sbinkertn@umich.edu DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2874053Sbinkertn@umich.edu iewQueue = iq_ptr; 2884053Sbinkertn@umich.edu 2894053Sbinkertn@umich.edu // Setup wire to get instructions from IEW. 2904046Sbinkertn@umich.edu fromIEW = iewQueue->getWire(-iewToCommitDelay); 2914042Sbinkertn@umich.edu} 2924053Sbinkertn@umich.edu 2934053Sbinkertn@umich.edutemplate <class Impl> 2944053Sbinkertn@umich.eduvoid 2954074Sbinkertn@umich.eduDefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2964042Sbinkertn@umich.edu{ 2974074Sbinkertn@umich.edu iewStage = iew_stage; 2984074Sbinkertn@umich.edu} 2994074Sbinkertn@umich.edu 3004074Sbinkertn@umich.edutemplate<class Impl> 3014042Sbinkertn@umich.eduvoid 3024046Sbinkertn@umich.eduDefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3034042Sbinkertn@umich.edu{ 3044042Sbinkertn@umich.edu DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3054042Sbinkertn@umich.edu activeThreads = at_ptr; 3062889Sbinkertn@umich.edu} 3072889Sbinkertn@umich.edu 3082889Sbinkertn@umich.edutemplate <class Impl> 3092891Sbinkertn@umich.eduvoid 3103887Sbinkertn@umich.eduDefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3113887Sbinkertn@umich.edu{ 3122899Sbinkertn@umich.edu DPRINTF(Commit, "Setting rename map pointers.\n"); 3132899Sbinkertn@umich.edu 3142899Sbinkertn@umich.edu for (int i=0; i < numThreads; i++) { 3154042Sbinkertn@umich.edu renameMap[i] = &rm_ptr[i]; 3162899Sbinkertn@umich.edu } 3172899Sbinkertn@umich.edu} 3182899Sbinkertn@umich.edu 3192899Sbinkertn@umich.edutemplate <class Impl> 3202899Sbinkertn@umich.eduvoid 3212899Sbinkertn@umich.eduDefaultCommit<Impl>::setROB(ROB *rob_ptr) 3222899Sbinkertn@umich.edu{ 3232899Sbinkertn@umich.edu DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3242899Sbinkertn@umich.edu rob = rob_ptr; 3252889Sbinkertn@umich.edu} 3262889Sbinkertn@umich.edu 3272889Sbinkertn@umich.edutemplate <class Impl> 3282889Sbinkertn@umich.eduvoid 3292889Sbinkertn@umich.eduDefaultCommit<Impl>::initStage() 3302889Sbinkertn@umich.edu{ 3312889Sbinkertn@umich.edu rob->setActiveThreads(activeThreads); 3322889Sbinkertn@umich.edu rob->resetEntries(); 3332889Sbinkertn@umich.edu 3342889Sbinkertn@umich.edu // Broadcast the number of free entries. 3352889Sbinkertn@umich.edu for (int i=0; i < numThreads; i++) { 3362889Sbinkertn@umich.edu toIEW->commitInfo[i].usedROB = true; 3372889Sbinkertn@umich.edu toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3382889Sbinkertn@umich.edu } 3392889Sbinkertn@umich.edu 3402889Sbinkertn@umich.edu cpu->activityThisCycle(); 3412889Sbinkertn@umich.edu} 342 343template <class Impl> 344bool 345DefaultCommit<Impl>::drain() 346{ 347 drainPending = true; 348 349 return false; 350} 351 352template <class Impl> 353void 354DefaultCommit<Impl>::switchOut() 355{ 356 switchedOut = true; 357 drainPending = false; 358 rob->switchOut(); 359} 360 361template <class Impl> 362void 363DefaultCommit<Impl>::resume() 364{ 365 drainPending = false; 366} 367 368template <class Impl> 369void 370DefaultCommit<Impl>::takeOverFrom() 371{ 372 switchedOut = false; 373 _status = Active; 374 _nextStatus = Inactive; 375 for (int i=0; i < numThreads; i++) { 376 commitStatus[i] = Idle; 377 changedROBNumEntries[i] = false; 378 trapSquash[i] = false; 379 tcSquash[i] = false; 380 } 381 squashCounter = 0; 382 rob->takeOverFrom(); 383} 384 385template <class Impl> 386void 387DefaultCommit<Impl>::updateStatus() 388{ 389 // reset ROB changed variable 390 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 391 while (threads != (*activeThreads).end()) { 392 unsigned tid = *threads++; 393 changedROBNumEntries[tid] = false; 394 395 // Also check if any of the threads has a trap pending 396 if (commitStatus[tid] == TrapPending || 397 commitStatus[tid] == FetchTrapPending) { 398 _nextStatus = Active; 399 } 400 } 401 402 if (_nextStatus == Inactive && _status == Active) { 403 DPRINTF(Activity, "Deactivating stage.\n"); 404 cpu->deactivateStage(O3CPU::CommitIdx); 405 } else if (_nextStatus == Active && _status == Inactive) { 406 DPRINTF(Activity, "Activating stage.\n"); 407 cpu->activateStage(O3CPU::CommitIdx); 408 } 409 410 _status = _nextStatus; 411} 412 413template <class Impl> 414void 415DefaultCommit<Impl>::setNextStatus() 416{ 417 int squashes = 0; 418 419 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 420 421 while (threads != (*activeThreads).end()) { 422 unsigned tid = *threads++; 423 424 if (commitStatus[tid] == ROBSquashing) { 425 squashes++; 426 } 427 } 428 429 squashCounter = squashes; 430 431 // If commit is currently squashing, then it will have activity for the 432 // next cycle. Set its next status as active. 433 if (squashCounter) { 434 _nextStatus = Active; 435 } 436} 437 438template <class Impl> 439bool 440DefaultCommit<Impl>::changedROBEntries() 441{ 442 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 443 444 while (threads != (*activeThreads).end()) { 445 unsigned tid = *threads++; 446 447 if (changedROBNumEntries[tid]) { 448 return true; 449 } 450 } 451 452 return false; 453} 454 455template <class Impl> 456unsigned 457DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 458{ 459 return rob->numFreeEntries(tid); 460} 461 462template <class Impl> 463void 464DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 465{ 466 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 467 468 TrapEvent *trap = new TrapEvent(this, tid); 469 470 trap->schedule(curTick + trapLatency); 471 472 thread[tid]->trapPending = true; 473} 474 475template <class Impl> 476void 477DefaultCommit<Impl>::generateTCEvent(unsigned tid) 478{ 479 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 480 481 tcSquash[tid] = true; 482} 483 484template <class Impl> 485void 486DefaultCommit<Impl>::squashAll(unsigned tid) 487{ 488 // If we want to include the squashing instruction in the squash, 489 // then use one older sequence number. 490 // Hopefully this doesn't mess things up. Basically I want to squash 491 // all instructions of this thread. 492 InstSeqNum squashed_inst = rob->isEmpty() ? 493 0 : rob->readHeadInst(tid)->seqNum - 1;; 494 495 // All younger instructions will be squashed. Set the sequence 496 // number as the youngest instruction in the ROB (0 in this case. 497 // Hopefully nothing breaks.) 498 youngestSeqNum[tid] = 0; 499 500 rob->squash(squashed_inst, tid); 501 changedROBNumEntries[tid] = true; 502 503 // Send back the sequence number of the squashed instruction. 504 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 505 506 // Send back the squash signal to tell stages that they should 507 // squash. 508 toIEW->commitInfo[tid].squash = true; 509 510 // Send back the rob squashing signal so other stages know that 511 // the ROB is in the process of squashing. 512 toIEW->commitInfo[tid].robSquashing = true; 513 514 toIEW->commitInfo[tid].branchMispredict = false; 515 516 toIEW->commitInfo[tid].nextPC = PC[tid]; 517} 518 519template <class Impl> 520void 521DefaultCommit<Impl>::squashFromTrap(unsigned tid) 522{ 523 squashAll(tid); 524 525 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 526 527 thread[tid]->trapPending = false; 528 thread[tid]->inSyscall = false; 529 530 trapSquash[tid] = false; 531 532 commitStatus[tid] = ROBSquashing; 533 cpu->activityThisCycle(); 534} 535 536template <class Impl> 537void 538DefaultCommit<Impl>::squashFromTC(unsigned tid) 539{ 540 squashAll(tid); 541 542 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 543 544 thread[tid]->inSyscall = false; 545 assert(!thread[tid]->trapPending); 546 547 commitStatus[tid] = ROBSquashing; 548 cpu->activityThisCycle(); 549 550 tcSquash[tid] = false; 551} 552 553template <class Impl> 554void 555DefaultCommit<Impl>::tick() 556{ 557 wroteToTimeBuffer = false; 558 _nextStatus = Inactive; 559 560 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 561 cpu->signalDrained(); 562 drainPending = false; 563 return; 564 } 565 566 if ((*activeThreads).size() <= 0) 567 return; 568 569 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 570 571 // Check if any of the threads are done squashing. Change the 572 // status if they are done. 573 while (threads != (*activeThreads).end()) { 574 unsigned tid = *threads++; 575 576 if (commitStatus[tid] == ROBSquashing) { 577 578 if (rob->isDoneSquashing(tid)) { 579 commitStatus[tid] = Running; 580 } else { 581 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 582 " insts this cycle.\n", tid); 583 rob->doSquash(tid); 584 toIEW->commitInfo[tid].robSquashing = true; 585 wroteToTimeBuffer = true; 586 } 587 } 588 } 589 590 commit(); 591 592 markCompletedInsts(); 593 594 threads = (*activeThreads).begin(); 595 596 while (threads != (*activeThreads).end()) { 597 unsigned tid = *threads++; 598 599 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 600 // The ROB has more instructions it can commit. Its next status 601 // will be active. 602 _nextStatus = Active; 603 604 DynInstPtr inst = rob->readHeadInst(tid); 605 606 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 607 " ROB and ready to commit\n", 608 tid, inst->seqNum, inst->readPC()); 609 610 } else if (!rob->isEmpty(tid)) { 611 DynInstPtr inst = rob->readHeadInst(tid); 612 613 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 614 "%#x is head of ROB and not ready\n", 615 tid, inst->seqNum, inst->readPC()); 616 } 617 618 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 619 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 620 } 621 622 623 if (wroteToTimeBuffer) { 624 DPRINTF(Activity, "Activity This Cycle.\n"); 625 cpu->activityThisCycle(); 626 } 627 628 updateStatus(); 629} 630 631template <class Impl> 632void 633DefaultCommit<Impl>::commit() 634{ 635 636 ////////////////////////////////////// 637 // Check for interrupts 638 ////////////////////////////////////// 639 640#if FULL_SYSTEM 641 if (interrupt != NoFault) { 642 // Wait until the ROB is empty and all stores have drained in 643 // order to enter the interrupt. 644 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 645 // Squash or record that I need to squash this cycle if 646 // an interrupt needed to be handled. 647 DPRINTF(Commit, "Interrupt detected.\n"); 648 649 assert(!thread[0]->inSyscall); 650 thread[0]->inSyscall = true; 651 652 // CPU will handle interrupt. 653 cpu->processInterrupts(interrupt); 654 655 thread[0]->inSyscall = false; 656 657 commitStatus[0] = TrapPending; 658 659 // Generate trap squash event. 660 generateTrapEvent(0); 661 662 // Clear the interrupt now that it's been handled 663 toIEW->commitInfo[0].clearInterrupt = true; 664 interrupt = NoFault; 665 } else { 666 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 667 } 668 } else if (cpu->checkInterrupts && 669 cpu->check_interrupts(cpu->tcBase(0)) && 670 commitStatus[0] != TrapPending && 671 !trapSquash[0] && 672 !tcSquash[0]) { 673 // Process interrupts if interrupts are enabled, not in PAL 674 // mode, and no other traps or external squashes are currently 675 // pending. 676 // @todo: Allow other threads to handle interrupts. 677 678 // Get any interrupt that happened 679 interrupt = cpu->getInterrupts(); 680 681 if (interrupt != NoFault) { 682 // Tell fetch that there is an interrupt pending. This 683 // will make fetch wait until it sees a non PAL-mode PC, 684 // at which point it stops fetching instructions. 685 toIEW->commitInfo[0].interruptPending = true; 686 } 687 } 688 689#endif // FULL_SYSTEM 690 691 //////////////////////////////////// 692 // Check for any possible squashes, handle them first 693 //////////////////////////////////// 694 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 695 696 while (threads != (*activeThreads).end()) { 697 unsigned tid = *threads++; 698 699 // Not sure which one takes priority. I think if we have 700 // both, that's a bad sign. 701 if (trapSquash[tid] == true) { 702 assert(!tcSquash[tid]); 703 squashFromTrap(tid); 704 } else if (tcSquash[tid] == true) { 705 squashFromTC(tid); 706 } 707 708 // Squashed sequence number must be older than youngest valid 709 // instruction in the ROB. This prevents squashes from younger 710 // instructions overriding squashes from older instructions. 711 if (fromIEW->squash[tid] && 712 commitStatus[tid] != TrapPending && 713 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 714 715 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 716 tid, 717 fromIEW->mispredPC[tid], 718 fromIEW->squashedSeqNum[tid]); 719 720 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 721 tid, 722 fromIEW->nextPC[tid]); 723 724 commitStatus[tid] = ROBSquashing; 725 726 // If we want to include the squashing instruction in the squash, 727 // then use one older sequence number. 728 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 729 730#if ISA_HAS_DELAY_SLOT 731 InstSeqNum bdelay_done_seq_num; 732 bool squash_bdelay_slot; 733 734 if (fromIEW->branchMispredict[tid]) { 735 if (fromIEW->branchTaken[tid] && 736 fromIEW->condDelaySlotBranch[tid]) { 737 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch" 738 "mispredicted as taken. Squashing after previous " 739 "inst, [sn:%i]\n", 740 tid, squashed_inst); 741 bdelay_done_seq_num = squashed_inst; 742 squash_bdelay_slot = true; 743 } else { 744 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing " 745 "after delay slot [sn:%i]\n", tid, squashed_inst+1); 746 bdelay_done_seq_num = squashed_inst + 1; 747 squash_bdelay_slot = false; 748 } 749 } else { 750 bdelay_done_seq_num = squashed_inst; 751 } 752#endif 753 754 if (fromIEW->includeSquashInst[tid] == true) { 755 squashed_inst--; 756#if ISA_HAS_DELAY_SLOT 757 bdelay_done_seq_num--; 758#endif 759 } 760 // All younger instructions will be squashed. Set the sequence 761 // number as the youngest instruction in the ROB. 762 youngestSeqNum[tid] = squashed_inst; 763 764#if ISA_HAS_DELAY_SLOT 765 rob->squash(bdelay_done_seq_num, tid); 766 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 767 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 768#else 769 rob->squash(squashed_inst, tid); 770 toIEW->commitInfo[tid].squashDelaySlot = true; 771#endif 772 changedROBNumEntries[tid] = true; 773 774 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 775 776 toIEW->commitInfo[tid].squash = true; 777 778 // Send back the rob squashing signal so other stages know that 779 // the ROB is in the process of squashing. 780 toIEW->commitInfo[tid].robSquashing = true; 781 782 toIEW->commitInfo[tid].branchMispredict = 783 fromIEW->branchMispredict[tid]; 784 785 toIEW->commitInfo[tid].branchTaken = 786 fromIEW->branchTaken[tid]; 787 788 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 789 790 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 791 792 if (toIEW->commitInfo[tid].branchMispredict) { 793 ++branchMispredicts; 794 } 795 } 796 797 } 798 799 setNextStatus(); 800 801 if (squashCounter != numThreads) { 802 // If we're not currently squashing, then get instructions. 803 getInsts(); 804 805 // Try to commit any instructions. 806 commitInsts(); 807 } else { 808#if ISA_HAS_DELAY_SLOT 809 skidInsert(); 810#endif 811 } 812 813 //Check for any activity 814 threads = (*activeThreads).begin(); 815 816 while (threads != (*activeThreads).end()) { 817 unsigned tid = *threads++; 818 819 if (changedROBNumEntries[tid]) { 820 toIEW->commitInfo[tid].usedROB = true; 821 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 822 823 if (rob->isEmpty(tid)) { 824 toIEW->commitInfo[tid].emptyROB = true; 825 } 826 827 wroteToTimeBuffer = true; 828 changedROBNumEntries[tid] = false; 829 } 830 } 831} 832 833template <class Impl> 834void 835DefaultCommit<Impl>::commitInsts() 836{ 837 //////////////////////////////////// 838 // Handle commit 839 // Note that commit will be handled prior to putting new 840 // instructions in the ROB so that the ROB only tries to commit 841 // instructions it has in this current cycle, and not instructions 842 // it is writing in during this cycle. Can't commit and squash 843 // things at the same time... 844 //////////////////////////////////// 845 846 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 847 848 unsigned num_committed = 0; 849 850 DynInstPtr head_inst; 851 852 // Commit as many instructions as possible until the commit bandwidth 853 // limit is reached, or it becomes impossible to commit any more. 854 while (num_committed < commitWidth) { 855 int commit_thread = getCommittingThread(); 856 857 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 858 break; 859 860 head_inst = rob->readHeadInst(commit_thread); 861 862 int tid = head_inst->threadNumber; 863 864 assert(tid == commit_thread); 865 866 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 867 head_inst->seqNum, tid); 868 869 // If the head instruction is squashed, it is ready to retire 870 // (be removed from the ROB) at any time. 871 if (head_inst->isSquashed()) { 872 873 DPRINTF(Commit, "Retiring squashed instruction from " 874 "ROB.\n"); 875 876 rob->retireHead(commit_thread); 877 878 ++commitSquashedInsts; 879 880 // Record that the number of ROB entries has changed. 881 changedROBNumEntries[tid] = true; 882 } else { 883 PC[tid] = head_inst->readPC(); 884 nextPC[tid] = head_inst->readNextPC(); 885 nextNPC[tid] = head_inst->readNextNPC(); 886 887 // Increment the total number of non-speculative instructions 888 // executed. 889 // Hack for now: it really shouldn't happen until after the 890 // commit is deemed to be successful, but this count is needed 891 // for syscalls. 892 thread[tid]->funcExeInst++; 893 894 // Try to commit the head instruction. 895 bool commit_success = commitHead(head_inst, num_committed); 896 897 if (commit_success) { 898 ++num_committed; 899 900 changedROBNumEntries[tid] = true; 901 902 // Set the doneSeqNum to the youngest committed instruction. 903 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 904 905 ++commitCommittedInsts; 906 907 // To match the old model, don't count nops and instruction 908 // prefetches towards the total commit count. 909 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 910 cpu->instDone(tid); 911 } 912 913 PC[tid] = nextPC[tid]; 914#if ISA_HAS_DELAY_SLOT 915 nextPC[tid] = nextNPC[tid]; 916 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 917#else 918 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 919#endif 920 921#if FULL_SYSTEM 922 int count = 0; 923 Addr oldpc; 924 do { 925 // Debug statement. Checks to make sure we're not 926 // currently updating state while handling PC events. 927 if (count == 0) 928 assert(!thread[tid]->inSyscall && 929 !thread[tid]->trapPending); 930 oldpc = PC[tid]; 931 cpu->system->pcEventQueue.service( 932 thread[tid]->getTC()); 933 count++; 934 } while (oldpc != PC[tid]); 935 if (count > 1) { 936 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 937 break; 938 } 939#endif 940 } else { 941 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 942 "[tid:%i] [sn:%i].\n", 943 head_inst->readPC(), tid ,head_inst->seqNum); 944 break; 945 } 946 } 947 } 948 949 DPRINTF(CommitRate, "%i\n", num_committed); 950 numCommittedDist.sample(num_committed); 951 952 if (num_committed == commitWidth) { 953 commitEligibleSamples++; 954 } 955} 956 957template <class Impl> 958bool 959DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 960{ 961 assert(head_inst); 962 963 int tid = head_inst->threadNumber; 964 965 // If the instruction is not executed yet, then it will need extra 966 // handling. Signal backwards that it should be executed. 967 if (!head_inst->isExecuted()) { 968 // Keep this number correct. We have not yet actually executed 969 // and committed this instruction. 970 thread[tid]->funcExeInst--; 971 972 head_inst->setAtCommit(); 973 974 if (head_inst->isNonSpeculative() || 975 head_inst->isStoreConditional() || 976 head_inst->isMemBarrier() || 977 head_inst->isWriteBarrier()) { 978 979 DPRINTF(Commit, "Encountered a barrier or non-speculative " 980 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 981 head_inst->seqNum, head_inst->readPC()); 982 983#if !FULL_SYSTEM 984 // Hack to make sure syscalls/memory barriers/quiesces 985 // aren't executed until all stores write back their data. 986 // This direct communication shouldn't be used for 987 // anything other than this. 988 if (inst_num > 0 || iewStage->hasStoresToWB()) 989#else 990 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 991 head_inst->isQuiesce()) && 992 iewStage->hasStoresToWB()) 993#endif 994 { 995 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 996 return false; 997 } 998 999 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1000 1001 // Change the instruction so it won't try to commit again until 1002 // it is executed. 1003 head_inst->clearCanCommit(); 1004 1005 ++commitNonSpecStalls; 1006 1007 return false; 1008 } else if (head_inst->isLoad()) { 1009 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 1010 head_inst->seqNum, head_inst->readPC()); 1011 1012 // Send back the non-speculative instruction's sequence 1013 // number. Tell the lsq to re-execute the load. 1014 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1015 toIEW->commitInfo[tid].uncached = true; 1016 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1017 1018 head_inst->clearCanCommit(); 1019 1020 return false; 1021 } else { 1022 panic("Trying to commit un-executed instruction " 1023 "of unknown type!\n"); 1024 } 1025 } 1026 1027 if (head_inst->isThreadSync()) { 1028 // Not handled for now. 1029 panic("Thread sync instructions are not handled yet.\n"); 1030 } 1031 1032 // Stores mark themselves as completed. 1033 if (!head_inst->isStore()) { 1034 head_inst->setCompleted(); 1035 } 1036 1037#if USE_CHECKER 1038 // Use checker prior to updating anything due to traps or PC 1039 // based events. 1040 if (cpu->checker) { 1041 cpu->checker->verify(head_inst); 1042 } 1043#endif 1044 1045 // Check if the instruction caused a fault. If so, trap. 1046 Fault inst_fault = head_inst->getFault(); 1047 1048 // DTB will sometimes need the machine instruction for when 1049 // faults happen. So we will set it here, prior to the DTB 1050 // possibly needing it for its fault. 1051 thread[tid]->setInst( 1052 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1053 1054 if (inst_fault != NoFault) { 1055 head_inst->setCompleted(); 1056 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1057 head_inst->seqNum, head_inst->readPC()); 1058 1059 if (iewStage->hasStoresToWB() || inst_num > 0) { 1060 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1061 return false; 1062 } 1063 1064#if USE_CHECKER 1065 if (cpu->checker && head_inst->isStore()) { 1066 cpu->checker->verify(head_inst); 1067 } 1068#endif 1069 1070 assert(!thread[tid]->inSyscall); 1071 1072 // Mark that we're in state update mode so that the trap's 1073 // execution doesn't generate extra squashes. 1074 thread[tid]->inSyscall = true; 1075 1076 // Execute the trap. Although it's slightly unrealistic in 1077 // terms of timing (as it doesn't wait for the full timing of 1078 // the trap event to complete before updating state), it's 1079 // needed to update the state as soon as possible. This 1080 // prevents external agents from changing any specific state 1081 // that the trap need. 1082 cpu->trap(inst_fault, tid); 1083 1084 // Exit state update mode to avoid accidental updating. 1085 thread[tid]->inSyscall = false; 1086 1087 commitStatus[tid] = TrapPending; 1088 1089 // Generate trap squash event. 1090 generateTrapEvent(tid); 1091// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 1092 return false; 1093 } 1094 1095 updateComInstStats(head_inst); 1096 1097#if FULL_SYSTEM 1098 if (thread[tid]->profile) { 1099// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 1100// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 1101 thread[tid]->profilePC = head_inst->readPC(); 1102 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1103 head_inst->staticInst); 1104 1105 if (node) 1106 thread[tid]->profileNode = node; 1107 } 1108#endif 1109 1110 if (head_inst->traceData) { 1111 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1112 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1113 head_inst->traceData->finalize(); 1114 head_inst->traceData = NULL; 1115 } 1116 1117 // Update the commit rename map 1118 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1119 renameMap[tid]->setEntry(head_inst->destRegIdx(i), 1120 head_inst->renamedDestRegIdx(i)); 1121 } 1122 1123 if (head_inst->isCopy()) 1124 panic("Should not commit any copy instructions!"); 1125 1126 // Finally clear the head ROB entry. 1127 rob->retireHead(tid); 1128 1129 // Return true to indicate that we have committed an instruction. 1130 return true; 1131} 1132 1133template <class Impl> 1134void 1135DefaultCommit<Impl>::getInsts() 1136{ 1137 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1138 1139#if ISA_HAS_DELAY_SLOT 1140 // Read any renamed instructions and place them into the ROB. 1141 int insts_to_process = std::min((int)renameWidth, 1142 (int)(fromRename->size + skidBuffer.size())); 1143 int rename_idx = 0; 1144 1145 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 1146 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 1147 skidBuffer.size()); 1148#else 1149 // Read any renamed instructions and place them into the ROB. 1150 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1151#endif 1152 1153 1154 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1155 DynInstPtr inst; 1156 1157#if ISA_HAS_DELAY_SLOT 1158 // Get insts from skidBuffer or from Rename 1159 if (skidBuffer.size() > 0) { 1160 DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 1161 inst = skidBuffer.front(); 1162 skidBuffer.pop(); 1163 } else { 1164 DPRINTF(Commit, "Grabbing rename inst.\n"); 1165 inst = fromRename->insts[rename_idx++]; 1166 } 1167#else 1168 inst = fromRename->insts[inst_num]; 1169#endif 1170 int tid = inst->threadNumber; 1171 1172 if (!inst->isSquashed() && 1173 commitStatus[tid] != ROBSquashing) { 1174 changedROBNumEntries[tid] = true; 1175 1176 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1177 inst->readPC(), inst->seqNum, tid); 1178 1179 rob->insertInst(inst); 1180 1181 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1182 1183 youngestSeqNum[tid] = inst->seqNum; 1184 } else { 1185 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1186 "squashed, skipping.\n", 1187 inst->readPC(), inst->seqNum, tid); 1188 } 1189 } 1190 1191#if ISA_HAS_DELAY_SLOT 1192 if (rename_idx < fromRename->size) { 1193 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 1194 1195 for (; 1196 rename_idx < fromRename->size; 1197 rename_idx++) { 1198 DynInstPtr inst = fromRename->insts[rename_idx]; 1199 int tid = inst->threadNumber; 1200 1201 if (!inst->isSquashed()) { 1202 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1203 "skidBuffer.\n", inst->readPC(), inst->seqNum, tid); 1204 skidBuffer.push(inst); 1205 } else { 1206 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1207 "squashed, skipping.\n", 1208 inst->readPC(), inst->seqNum, tid); 1209 } 1210 } 1211 } 1212#endif 1213 1214} 1215 1216template <class Impl> 1217void 1218DefaultCommit<Impl>::skidInsert() 1219{ 1220 DPRINTF(Commit, "Attempting to any instructions from rename into " 1221 "skidBuffer.\n"); 1222 1223 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1224 DynInstPtr inst = fromRename->insts[inst_num]; 1225 1226 if (!inst->isSquashed()) { 1227 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1228 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1229 inst->threadNumber); 1230 skidBuffer.push(inst); 1231 } else { 1232 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1233 "squashed, skipping.\n", 1234 inst->readPC(), inst->seqNum, inst->threadNumber); 1235 } 1236 } 1237} 1238 1239template <class Impl> 1240void 1241DefaultCommit<Impl>::markCompletedInsts() 1242{ 1243 // Grab completed insts out of the IEW instruction queue, and mark 1244 // instructions completed within the ROB. 1245 for (int inst_num = 0; 1246 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1247 ++inst_num) 1248 { 1249 if (!fromIEW->insts[inst_num]->isSquashed()) { 1250 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1251 "within ROB.\n", 1252 fromIEW->insts[inst_num]->threadNumber, 1253 fromIEW->insts[inst_num]->readPC(), 1254 fromIEW->insts[inst_num]->seqNum); 1255 1256 // Mark the instruction as ready to commit. 1257 fromIEW->insts[inst_num]->setCanCommit(); 1258 } 1259 } 1260} 1261 1262template <class Impl> 1263bool 1264DefaultCommit<Impl>::robDoneSquashing() 1265{ 1266 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1267 1268 while (threads != (*activeThreads).end()) { 1269 unsigned tid = *threads++; 1270 1271 if (!rob->isDoneSquashing(tid)) 1272 return false; 1273 } 1274 1275 return true; 1276} 1277 1278template <class Impl> 1279void 1280DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1281{ 1282 unsigned thread = inst->threadNumber; 1283 1284 // 1285 // Pick off the software prefetches 1286 // 1287#ifdef TARGET_ALPHA 1288 if (inst->isDataPrefetch()) { 1289 statComSwp[thread]++; 1290 } else { 1291 statComInst[thread]++; 1292 } 1293#else 1294 statComInst[thread]++; 1295#endif 1296 1297 // 1298 // Control Instructions 1299 // 1300 if (inst->isControl()) 1301 statComBranches[thread]++; 1302 1303 // 1304 // Memory references 1305 // 1306 if (inst->isMemRef()) { 1307 statComRefs[thread]++; 1308 1309 if (inst->isLoad()) { 1310 statComLoads[thread]++; 1311 } 1312 } 1313 1314 if (inst->isMemBarrier()) { 1315 statComMembars[thread]++; 1316 } 1317} 1318 1319//////////////////////////////////////// 1320// // 1321// SMT COMMIT POLICY MAINTAINED HERE // 1322// // 1323//////////////////////////////////////// 1324template <class Impl> 1325int 1326DefaultCommit<Impl>::getCommittingThread() 1327{ 1328 if (numThreads > 1) { 1329 switch (commitPolicy) { 1330 1331 case Aggressive: 1332 //If Policy is Aggressive, commit will call 1333 //this function multiple times per 1334 //cycle 1335 return oldestReady(); 1336 1337 case RoundRobin: 1338 return roundRobin(); 1339 1340 case OldestReady: 1341 return oldestReady(); 1342 1343 default: 1344 return -1; 1345 } 1346 } else { 1347 int tid = (*activeThreads).front(); 1348 1349 if (commitStatus[tid] == Running || 1350 commitStatus[tid] == Idle || 1351 commitStatus[tid] == FetchTrapPending) { 1352 return tid; 1353 } else { 1354 return -1; 1355 } 1356 } 1357} 1358 1359template<class Impl> 1360int 1361DefaultCommit<Impl>::roundRobin() 1362{ 1363 std::list<unsigned>::iterator pri_iter = priority_list.begin(); 1364 std::list<unsigned>::iterator end = priority_list.end(); 1365 1366 while (pri_iter != end) { 1367 unsigned tid = *pri_iter; 1368 1369 if (commitStatus[tid] == Running || 1370 commitStatus[tid] == Idle || 1371 commitStatus[tid] == FetchTrapPending) { 1372 1373 if (rob->isHeadReady(tid)) { 1374 priority_list.erase(pri_iter); 1375 priority_list.push_back(tid); 1376 1377 return tid; 1378 } 1379 } 1380 1381 pri_iter++; 1382 } 1383 1384 return -1; 1385} 1386 1387template<class Impl> 1388int 1389DefaultCommit<Impl>::oldestReady() 1390{ 1391 unsigned oldest = 0; 1392 bool first = true; 1393 1394 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1395 1396 while (threads != (*activeThreads).end()) { 1397 unsigned tid = *threads++; 1398 1399 if (!rob->isEmpty(tid) && 1400 (commitStatus[tid] == Running || 1401 commitStatus[tid] == Idle || 1402 commitStatus[tid] == FetchTrapPending)) { 1403 1404 if (rob->isHeadReady(tid)) { 1405 1406 DynInstPtr head_inst = rob->readHeadInst(tid); 1407 1408 if (first) { 1409 oldest = tid; 1410 first = false; 1411 } else if (head_inst->seqNum < oldest) { 1412 oldest = tid; 1413 } 1414 } 1415 } 1416 } 1417 1418 if (!first) { 1419 return oldest; 1420 } else { 1421 return -1; 1422 } 1423} 1424