commit_impl.hh revision 2918:20cdaf201249
12SN/A/* 21762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292SN/A */ 302SN/A 312439SN/A#include "config/full_system.hh" 322984Sgblack@eecs.umich.edu#include "config/use_checker.hh" 33146SN/A 34146SN/A#include <algorithm> 35146SN/A#include <string> 36146SN/A 37146SN/A#include "base/loader/symtab.hh" 38146SN/A#include "base/timebuf.hh" 391717SN/A#include "cpu/exetrace.hh" 40146SN/A#include "cpu/o3/commit.hh" 411717SN/A#include "cpu/o3/thread_state.hh" 42146SN/A 431977SN/A#if USE_CHECKER 442623SN/A#include "cpu/checker/cpu.hh" 452683Sktlim@umich.edu#endif 461717SN/A 47146SN/Ausing namespace std; 482683Sktlim@umich.edu 493348Sbinkertn@umich.edutemplate <class Impl> 502036SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 51146SN/A unsigned _tid) 5256SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 5356SN/A{ 5456SN/A this->setFlags(Event::AutoDelete); 55695SN/A} 562901Ssaidi@eecs.umich.edu 572SN/Atemplate <class Impl> 581858SN/Avoid 593565Sgblack@eecs.umich.eduDefaultCommit<Impl>::TrapEvent::process() 603565Sgblack@eecs.umich.edu{ 612171SN/A // This will get reset by commit if it was switched out at the 622170SN/A // time of this event processing. 633562Sgblack@eecs.umich.edu commit->trapSquash[tid] = true; 64146SN/A} 652462SN/A 66146SN/Atemplate <class Impl> 672SN/Aconst char * 682SN/ADefaultCommit<Impl>::TrapEvent::description() 692449SN/A{ 701355SN/A return "Trap event"; 712623SN/A} 724495Sacolyte@umich.edu 73224SN/Atemplate <class Impl> 741858SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 752683Sktlim@umich.edu : squashCounter(0), 762420SN/A iewToCommitDelay(params->iewToCommitDelay), 772683Sktlim@umich.edu commitToIEWDelay(params->commitToIEWDelay), 784997Sgblack@eecs.umich.edu renameToROBDelay(params->renameToROBDelay), 792420SN/A fetchToCommitDelay(params->commitToFetchDelay), 802SN/A renameWidth(params->renameWidth), 814400Srdreslin@umich.edu commitWidth(params->commitWidth), 822672Sktlim@umich.edu numThreads(params->numberOfThreads), 832683Sktlim@umich.edu drainPending(false), 842SN/A switchedOut(false), 852SN/A trapLatency(params->trapLatency) 86334SN/A{ 87140SN/A _status = Active; 88334SN/A _nextStatus = Inactive; 892SN/A string policy = params->smtCommitPolicy; 902SN/A 912SN/A //Convert string to lowercase 922680Sktlim@umich.edu std::transform(policy.begin(), policy.end(), policy.begin(), 934377Sgblack@eecs.umich.edu (int(*)(int)) tolower); 945169Ssaidi@eecs.umich.edu 955169Ssaidi@eecs.umich.edu //Assign commit policy 964377Sgblack@eecs.umich.edu if (policy == "aggressive"){ 974377Sgblack@eecs.umich.edu commitPolicy = Aggressive; 982SN/A 992SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 1002623SN/A } else if (policy == "roundrobin"){ 1012SN/A commitPolicy = RoundRobin; 1022SN/A 1032SN/A //Set-Up Priority List 104180SN/A for (int tid=0; tid < numThreads; tid++) { 1052623SN/A priority_list.push_back(tid); 106393SN/A } 107393SN/A 108393SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 109393SN/A } else if (policy == "oldestready"){ 110384SN/A commitPolicy = OldestReady; 111384SN/A 112393SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1132623SN/A } else { 114393SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 115393SN/A "RoundRobin,OldestReady}"); 116393SN/A } 117393SN/A 118384SN/A for (int i=0; i < numThreads; i++) { 119189SN/A commitStatus[i] = Idle; 120189SN/A changedROBNumEntries[i] = false; 1212623SN/A trapSquash[i] = false; 1222SN/A tcSquash[i] = false; 123729SN/A PC[i] = nextPC[i] = 0; 124334SN/A } 1252SN/A} 1262SN/A 1272SN/Atemplate <class Impl> 1282SN/Astd::string 1292SN/ADefaultCommit<Impl>::name() const 1302SN/A{ 1312SN/A return cpu->name() + ".commit"; 1322SN/A} 1332SN/A 1342SN/Atemplate <class Impl> 1352SN/Avoid 1362SN/ADefaultCommit<Impl>::regStats() 1371001SN/A{ 1381001SN/A using namespace Stats; 1391001SN/A commitCommittedInsts 1401001SN/A .name(name() + ".commitCommittedInsts") 1411001SN/A .desc("The number of committed instructions") 1422SN/A .prereq(commitCommittedInsts); 1432SN/A commitSquashedInsts 1442SN/A .name(name() + ".commitSquashedInsts") 1452SN/A .desc("The number of squashed insts skipped by commit") 1462SN/A .prereq(commitSquashedInsts); 1472SN/A commitSquashEvents 1482SN/A .name(name() + ".commitSquashEvents") 1492SN/A .desc("The number of times commit is told to squash") 1502SN/A .prereq(commitSquashEvents); 1512SN/A commitNonSpecStalls 1522SN/A .name(name() + ".commitNonSpecStalls") 1532SN/A .desc("The number of times commit has been forced to stall to " 1542SN/A "communicate backwards") 1552SN/A .prereq(commitNonSpecStalls); 1562SN/A branchMispredicts 1572SN/A .name(name() + ".branchMispredicts") 1582SN/A .desc("The number of times a branch was mispredicted") 1592390SN/A .prereq(branchMispredicts); 1602390SN/A numCommittedDist 1612390SN/A .init(0,commitWidth,1) 1622390SN/A .name(name() + ".COM:committed_per_cycle") 1632390SN/A .desc("Number of insts commited each cycle") 1642390SN/A .flags(Stats::pdf) 1652390SN/A ; 1662390SN/A 1672390SN/A statComInst 1682390SN/A .init(cpu->number_of_threads) 1692390SN/A .name(name() + ".COM:count") 1702390SN/A .desc("Number of instructions committed") 171385SN/A .flags(total) 1722SN/A ; 1732SN/A 1742SN/A statComSwp 1752623SN/A .init(cpu->number_of_threads) 176334SN/A .name(name() + ".COM:swp_count") 1772361SN/A .desc("Number of s/w prefetches committed") 1782623SN/A .flags(total) 179334SN/A ; 180334SN/A 181334SN/A statComRefs 1822623SN/A .init(cpu->number_of_threads) 1832SN/A .name(name() + ".COM:refs") 184921SN/A .desc("Number of memory references committed") 1852915Sktlim@umich.edu .flags(total) 1862915Sktlim@umich.edu ; 1872683Sktlim@umich.edu 1882SN/A statComLoads 1892SN/A .init(cpu->number_of_threads) 1902SN/A .name(name() + ".COM:loads") 1912623SN/A .desc("Number of loads committed") 1922SN/A .flags(total) 193921SN/A ; 1942915Sktlim@umich.edu 1952915Sktlim@umich.edu statComMembars 1962SN/A .init(cpu->number_of_threads) 1972SN/A .name(name() + ".COM:membars") 1982SN/A .desc("Number of memory barriers committed") 1992SN/A .flags(total) 2002SN/A ; 2012SN/A 2022SN/A statComBranches 203595SN/A .init(cpu->number_of_threads) 2042623SN/A .name(name() + ".COM:branches") 205595SN/A .desc("Number of branches committed") 2062390SN/A .flags(total) 2071080SN/A ; 2081080SN/A 2091080SN/A commitEligible 2101080SN/A .init(cpu->number_of_threads) 2111080SN/A .name(name() + ".COM:bw_limited") 2121080SN/A .desc("number of insts not committed due to BW limits") 2131080SN/A .flags(total) 2141121SN/A ; 2152107SN/A 2161089SN/A commitEligibleSamples 2171089SN/A .name(name() + ".COM:bw_lim_events") 2181080SN/A .desc("number cycles where commit BW limit reached") 2191080SN/A ; 2201080SN/A} 2211080SN/A 222595SN/Atemplate <class Impl> 2232623SN/Avoid 2242683Sktlim@umich.eduDefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 225595SN/A{ 2262090SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2272683Sktlim@umich.edu cpu = cpu_ptr; 2282683Sktlim@umich.edu 229595SN/A // Commit must broadcast the number of free entries it has at the start of 2302205SN/A // the simulation, so it starts as active. 2312205SN/A cpu->activateStage(O3CPU::CommitIdx); 2322683Sktlim@umich.edu 2332683Sktlim@umich.edu trapLatency = cpu->cycles(trapLatency); 234595SN/A} 235595SN/A 2362390SN/Atemplate <class Impl> 2372423SN/Avoid 2382390SN/ADefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 239595SN/A{ 240595SN/A thread = threads; 241595SN/A} 2422623SN/A 243595SN/Atemplate <class Impl> 2442390SN/Avoid 2451080SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 246595SN/A{ 2471080SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2481080SN/A timeBuffer = tb_ptr; 249595SN/A 2502683Sktlim@umich.edu // Setup wire to send information back to IEW. 2511080SN/A toIEW = timeBuffer->getWire(0); 2521080SN/A 2531080SN/A // Setup wire to read data from IEW (for the ROB). 2541121SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2552107SN/A} 2561089SN/A 2571080SN/Atemplate <class Impl> 2581089SN/Avoid 2591080SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2601080SN/A{ 2611080SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 262595SN/A fetchQueue = fq_ptr; 2632683Sktlim@umich.edu 2641080SN/A // Setup wire to get instructions from rename (for the ROB). 2652090SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2661080SN/A} 267595SN/A 2682683Sktlim@umich.edutemplate <class Impl> 2692683Sktlim@umich.eduvoid 270595SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2712683Sktlim@umich.edu{ 2721098SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2731098SN/A renameQueue = rq_ptr; 2741098SN/A 2752683Sktlim@umich.edu // Setup wire to get instructions from rename (for the ROB). 2761098SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2771098SN/A} 2781098SN/A 2792012SN/Atemplate <class Impl> 2801098SN/Avoid 2811098SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 282595SN/A{ 2832205SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2842205SN/A iewQueue = iq_ptr; 2852205SN/A 286595SN/A // Setup wire to get instructions from IEW. 2872390SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2882420SN/A} 2892423SN/A 2902390SN/Atemplate <class Impl> 291595SN/Avoid 292595SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2931858SN/A{ 2942SN/A iewStage = iew_stage; 2952623SN/A} 2962SN/A 2972680Sktlim@umich.edutemplate<class Impl> 2982SN/Avoid 2992SN/ADefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3002SN/A{ 3011858SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3022SN/A activeThreads = at_ptr; 3032623SN/A} 3042SN/A 3052SN/Atemplate <class Impl> 3062SN/Avoid 3072683Sktlim@umich.eduDefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3084216Ssaidi@eecs.umich.edu{ 3092683Sktlim@umich.edu DPRINTF(Commit, "Setting rename map pointers.\n"); 3102SN/A 3112SN/A for (int i=0; i < numThreads; i++) { 3122SN/A renameMap[i] = &rm_ptr[i]; 3132SN/A } 3142SN/A} 3152623SN/A 3162SN/Atemplate <class Impl> 3171858SN/Avoid 3183923Shsul@eecs.umich.eduDefaultCommit<Impl>::setROB(ROB *rob_ptr) 3193520Sgblack@eecs.umich.edu{ 3202SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3213520Sgblack@eecs.umich.edu rob = rob_ptr; 3223633Sktlim@umich.edu} 3233520Sgblack@eecs.umich.edu 3242SN/Atemplate <class Impl> 3252SN/Avoid 3262SN/ADefaultCommit<Impl>::initStage() 3272623SN/A{ 3282SN/A rob->setActiveThreads(activeThreads); 3292623SN/A rob->resetEntries(); 3302623SN/A 3312662Sstever@eecs.umich.edu // Broadcast the number of free entries. 3322623SN/A for (int i=0; i < numThreads; i++) { 3334514Ssaidi@eecs.umich.edu toIEW->commitInfo[i].usedROB = true; 3344495Sacolyte@umich.edu toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3352623SN/A } 3363093Sksewell@umich.edu 3374495Sacolyte@umich.edu cpu->activityThisCycle(); 3383093Sksewell@umich.edu} 3393093Sksewell@umich.edu 3404564Sgblack@eecs.umich.edutemplate <class Impl> 3412741Sksewell@umich.edubool 3422741Sksewell@umich.eduDefaultCommit<Impl>::drain() 3432623SN/A{ 3444564Sgblack@eecs.umich.edu drainPending = true; 3454564Sgblack@eecs.umich.edu 3462623SN/A // If it's already drained, return true. 3472683Sktlim@umich.edu if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 3482623SN/A cpu->signalDrained(); 3492623SN/A return true; 3502623SN/A } 3512623SN/A 3522623SN/A return false; 3532623SN/A} 3542623SN/A 3552623SN/Atemplate <class Impl> 3562SN/Avoid 3572683Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3582427SN/A{ 3592683Sktlim@umich.edu switchedOut = true; 3602427SN/A drainPending = false; 3612SN/A rob->switchOut(); 3622623SN/A} 3632623SN/A 3642SN/Atemplate <class Impl> 3652623SN/Avoid 3662623SN/ADefaultCommit<Impl>::resume() 3674377Sgblack@eecs.umich.edu{ 3683276Sgblack@eecs.umich.edu drainPending = false; 3693276Sgblack@eecs.umich.edu} 3704377Sgblack@eecs.umich.edu 3714181Sgblack@eecs.umich.edutemplate <class Impl> 3724181Sgblack@eecs.umich.eduvoid 3734181Sgblack@eecs.umich.eduDefaultCommit<Impl>::takeOverFrom() 3744182Sgblack@eecs.umich.edu{ 3754182Sgblack@eecs.umich.edu switchedOut = false; 3764182Sgblack@eecs.umich.edu _status = Active; 3774593Sgblack@eecs.umich.edu _nextStatus = Inactive; 3784593Sgblack@eecs.umich.edu for (int i=0; i < numThreads; i++) { 3794593Sgblack@eecs.umich.edu commitStatus[i] = Idle; 3804593Sgblack@eecs.umich.edu changedROBNumEntries[i] = false; 3814593Sgblack@eecs.umich.edu trapSquash[i] = false; 3824377Sgblack@eecs.umich.edu tcSquash[i] = false; 3834377Sgblack@eecs.umich.edu } 3844377Sgblack@eecs.umich.edu squashCounter = 0; 3854377Sgblack@eecs.umich.edu rob->takeOverFrom(); 3864377Sgblack@eecs.umich.edu} 3874377Sgblack@eecs.umich.edu 3884377Sgblack@eecs.umich.edutemplate <class Impl> 3894377Sgblack@eecs.umich.eduvoid 3904572Sacolyte@umich.eduDefaultCommit<Impl>::updateStatus() 3914572Sacolyte@umich.edu{ 3924377Sgblack@eecs.umich.edu // reset ROB changed variable 3934377Sgblack@eecs.umich.edu list<unsigned>::iterator threads = (*activeThreads).begin(); 3944377Sgblack@eecs.umich.edu while (threads != (*activeThreads).end()) { 3954377Sgblack@eecs.umich.edu unsigned tid = *threads++; 3964181Sgblack@eecs.umich.edu changedROBNumEntries[tid] = false; 3974181Sgblack@eecs.umich.edu 3984181Sgblack@eecs.umich.edu // Also check if any of the threads has a trap pending 3994539Sgblack@eecs.umich.edu if (commitStatus[tid] == TrapPending || 4003276Sgblack@eecs.umich.edu commitStatus[tid] == FetchTrapPending) { 4013442Sgblack@eecs.umich.edu _nextStatus = Active; 4024539Sgblack@eecs.umich.edu } 4033280Sgblack@eecs.umich.edu } 4043280Sgblack@eecs.umich.edu 4053276Sgblack@eecs.umich.edu if (_nextStatus == Inactive && _status == Active) { 4063276Sgblack@eecs.umich.edu DPRINTF(Activity, "Deactivating stage.\n"); 4073276Sgblack@eecs.umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4083442Sgblack@eecs.umich.edu } else if (_nextStatus == Active && _status == Inactive) { 4094539Sgblack@eecs.umich.edu DPRINTF(Activity, "Activating stage.\n"); 4103276Sgblack@eecs.umich.edu cpu->activateStage(O3CPU::CommitIdx); 4113276Sgblack@eecs.umich.edu } 4124181Sgblack@eecs.umich.edu 4134181Sgblack@eecs.umich.edu _status = _nextStatus; 4144181Sgblack@eecs.umich.edu} 4154522Ssaidi@eecs.umich.edu 4164776Sgblack@eecs.umich.edutemplate <class Impl> 4174181Sgblack@eecs.umich.eduvoid 4182470SN/ADefaultCommit<Impl>::setNextStatus() 4194181Sgblack@eecs.umich.edu{ 4204181Sgblack@eecs.umich.edu int squashes = 0; 4214522Ssaidi@eecs.umich.edu 4222623SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4232623SN/A 4244181Sgblack@eecs.umich.edu while (threads != (*activeThreads).end()) { 4252623SN/A unsigned tid = *threads++; 4264181Sgblack@eecs.umich.edu 4272623SN/A if (commitStatus[tid] == ROBSquashing) { 4282623SN/A squashes++; 4292623SN/A } 4302623SN/A } 4312623SN/A 4322623SN/A squashCounter = squashes; 4335086Sgblack@eecs.umich.edu 4343577Sgblack@eecs.umich.edu // If commit is currently squashing, then it will have activity for the 4352683Sktlim@umich.edu // next cycle. Set its next status as active. 4365086Sgblack@eecs.umich.edu if (squashCounter) { 4372623SN/A _nextStatus = Active; 4382683Sktlim@umich.edu } 4392623SN/A} 4402420SN/A 4412SN/Atemplate <class Impl> 4422623SN/Abool 4432623SN/ADefaultCommit<Impl>::changedROBEntries() 4442SN/A{ 4452SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4462623SN/A 4472623SN/A while (threads != (*activeThreads).end()) { 4482623SN/A unsigned tid = *threads++; 4492623SN/A 4502SN/A if (changedROBNumEntries[tid]) { 4512683Sktlim@umich.edu return true; 4522644Sstever@eecs.umich.edu } 4532644Sstever@eecs.umich.edu } 4544046Sbinkertn@umich.edu 4554046Sbinkertn@umich.edu return false; 4564046Sbinkertn@umich.edu} 4572644Sstever@eecs.umich.edu 4582623SN/Atemplate <class Impl> 4592SN/Aunsigned 4602SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4612623SN/A{ 4622623SN/A return rob->numFreeEntries(tid); 4632623SN/A} 4644377Sgblack@eecs.umich.edu 4654377Sgblack@eecs.umich.edutemplate <class Impl> 4662090SN/Avoid 4673905Ssaidi@eecs.umich.eduDefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4685120Sgblack@eecs.umich.edu{ 4692680Sktlim@umich.edu DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4703929Ssaidi@eecs.umich.edu 4713929Ssaidi@eecs.umich.edu TrapEvent *trap = new TrapEvent(this, tid); 4724377Sgblack@eecs.umich.edu 4733276Sgblack@eecs.umich.edu trap->schedule(curTick + trapLatency); 4744539Sgblack@eecs.umich.edu 4753276Sgblack@eecs.umich.edu thread[tid]->trapPending = true; 4763276Sgblack@eecs.umich.edu} 4773276Sgblack@eecs.umich.edu 4783276Sgblack@eecs.umich.edutemplate <class Impl> 4793280Sgblack@eecs.umich.eduvoid 4803276Sgblack@eecs.umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4813280Sgblack@eecs.umich.edu{ 4823276Sgblack@eecs.umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4833276Sgblack@eecs.umich.edu 4843276Sgblack@eecs.umich.edu tcSquash[tid] = true; 4853276Sgblack@eecs.umich.edu} 4863280Sgblack@eecs.umich.edu 4873276Sgblack@eecs.umich.edutemplate <class Impl> 4883276Sgblack@eecs.umich.eduvoid 4893280Sgblack@eecs.umich.eduDefaultCommit<Impl>::squashAll(unsigned tid) 4903276Sgblack@eecs.umich.edu{ 4913276Sgblack@eecs.umich.edu // If we want to include the squashing instruction in the squash, 4923276Sgblack@eecs.umich.edu // then use one older sequence number. 4933276Sgblack@eecs.umich.edu // Hopefully this doesn't mess things up. Basically I want to squash 4943276Sgblack@eecs.umich.edu // all instructions of this thread. 4953276Sgblack@eecs.umich.edu InstSeqNum squashed_inst = rob->isEmpty() ? 4963276Sgblack@eecs.umich.edu 0 : rob->readHeadInst(tid)->seqNum - 1;; 4972SN/A 4982SN/A // All younger instructions will be squashed. Set the sequence 4992SN/A // number as the youngest instruction in the ROB (0 in this case. 5002SN/A // Hopefully nothing breaks.) 5012683Sktlim@umich.edu youngestSeqNum[tid] = 0; 5022680Sktlim@umich.edu 5032683Sktlim@umich.edu rob->squash(squashed_inst, tid); 5042SN/A changedROBNumEntries[tid] = true; 5052SN/A 506 // Send back the sequence number of the squashed instruction. 507 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 508 509 // Send back the squash signal to tell stages that they should 510 // squash. 511 toIEW->commitInfo[tid].squash = true; 512 513 // Send back the rob squashing signal so other stages know that 514 // the ROB is in the process of squashing. 515 toIEW->commitInfo[tid].robSquashing = true; 516 517 toIEW->commitInfo[tid].branchMispredict = false; 518 519 toIEW->commitInfo[tid].nextPC = PC[tid]; 520} 521 522template <class Impl> 523void 524DefaultCommit<Impl>::squashFromTrap(unsigned tid) 525{ 526 squashAll(tid); 527 528 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 529 530 thread[tid]->trapPending = false; 531 thread[tid]->inSyscall = false; 532 533 trapSquash[tid] = false; 534 535 commitStatus[tid] = ROBSquashing; 536 cpu->activityThisCycle(); 537} 538 539template <class Impl> 540void 541DefaultCommit<Impl>::squashFromTC(unsigned tid) 542{ 543 squashAll(tid); 544 545 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 546 547 thread[tid]->inSyscall = false; 548 assert(!thread[tid]->trapPending); 549 550 commitStatus[tid] = ROBSquashing; 551 cpu->activityThisCycle(); 552 553 tcSquash[tid] = false; 554} 555 556template <class Impl> 557void 558DefaultCommit<Impl>::tick() 559{ 560 wroteToTimeBuffer = false; 561 _nextStatus = Inactive; 562 563 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 564 cpu->signalDrained(); 565 drainPending = false; 566 return; 567 } 568 569 if ((*activeThreads).size() <= 0) 570 return; 571 572 list<unsigned>::iterator threads = (*activeThreads).begin(); 573 574 // Check if any of the threads are done squashing. Change the 575 // status if they are done. 576 while (threads != (*activeThreads).end()) { 577 unsigned tid = *threads++; 578 579 if (commitStatus[tid] == ROBSquashing) { 580 581 if (rob->isDoneSquashing(tid)) { 582 commitStatus[tid] = Running; 583 } else { 584 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 585 " insts this cycle.\n", tid); 586 rob->doSquash(tid); 587 toIEW->commitInfo[tid].robSquashing = true; 588 wroteToTimeBuffer = true; 589 } 590 } 591 } 592 593 commit(); 594 595 markCompletedInsts(); 596 597 threads = (*activeThreads).begin(); 598 599 while (threads != (*activeThreads).end()) { 600 unsigned tid = *threads++; 601 602 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 603 // The ROB has more instructions it can commit. Its next status 604 // will be active. 605 _nextStatus = Active; 606 607 DynInstPtr inst = rob->readHeadInst(tid); 608 609 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 610 " ROB and ready to commit\n", 611 tid, inst->seqNum, inst->readPC()); 612 613 } else if (!rob->isEmpty(tid)) { 614 DynInstPtr inst = rob->readHeadInst(tid); 615 616 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 617 "%#x is head of ROB and not ready\n", 618 tid, inst->seqNum, inst->readPC()); 619 } 620 621 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 622 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 623 } 624 625 626 if (wroteToTimeBuffer) { 627 DPRINTF(Activity, "Activity This Cycle.\n"); 628 cpu->activityThisCycle(); 629 } 630 631 updateStatus(); 632} 633 634template <class Impl> 635void 636DefaultCommit<Impl>::commit() 637{ 638 639 ////////////////////////////////////// 640 // Check for interrupts 641 ////////////////////////////////////// 642 643#if FULL_SYSTEM 644 // Process interrupts if interrupts are enabled, not in PAL mode, 645 // and no other traps or external squashes are currently pending. 646 // @todo: Allow other threads to handle interrupts. 647 if (cpu->checkInterrupts && 648 cpu->check_interrupts() && 649 !cpu->inPalMode(readPC()) && 650 !trapSquash[0] && 651 !tcSquash[0]) { 652 // Tell fetch that there is an interrupt pending. This will 653 // make fetch wait until it sees a non PAL-mode PC, at which 654 // point it stops fetching instructions. 655 toIEW->commitInfo[0].interruptPending = true; 656 657 // Wait until the ROB is empty and all stores have drained in 658 // order to enter the interrupt. 659 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 660 // Not sure which thread should be the one to interrupt. For now 661 // always do thread 0. 662 assert(!thread[0]->inSyscall); 663 thread[0]->inSyscall = true; 664 665 // CPU will handle implementation of the interrupt. 666 cpu->processInterrupts(); 667 668 // Now squash or record that I need to squash this cycle. 669 commitStatus[0] = TrapPending; 670 671 // Exit state update mode to avoid accidental updating. 672 thread[0]->inSyscall = false; 673 674 // Generate trap squash event. 675 generateTrapEvent(0); 676 677 toIEW->commitInfo[0].clearInterrupt = true; 678 679 DPRINTF(Commit, "Interrupt detected.\n"); 680 } else { 681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 682 } 683 } 684#endif // FULL_SYSTEM 685 686 //////////////////////////////////// 687 // Check for any possible squashes, handle them first 688 //////////////////////////////////// 689 690 list<unsigned>::iterator threads = (*activeThreads).begin(); 691 692 while (threads != (*activeThreads).end()) { 693 unsigned tid = *threads++; 694 695 // Not sure which one takes priority. I think if we have 696 // both, that's a bad sign. 697 if (trapSquash[tid] == true) { 698 assert(!tcSquash[tid]); 699 squashFromTrap(tid); 700 } else if (tcSquash[tid] == true) { 701 squashFromTC(tid); 702 } 703 704 // Squashed sequence number must be older than youngest valid 705 // instruction in the ROB. This prevents squashes from younger 706 // instructions overriding squashes from older instructions. 707 if (fromIEW->squash[tid] && 708 commitStatus[tid] != TrapPending && 709 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 710 711 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 712 tid, 713 fromIEW->mispredPC[tid], 714 fromIEW->squashedSeqNum[tid]); 715 716 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 717 tid, 718 fromIEW->nextPC[tid]); 719 720 commitStatus[tid] = ROBSquashing; 721 722 // If we want to include the squashing instruction in the squash, 723 // then use one older sequence number. 724 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 725 726 if (fromIEW->includeSquashInst[tid] == true) 727 squashed_inst--; 728 729 // All younger instructions will be squashed. Set the sequence 730 // number as the youngest instruction in the ROB. 731 youngestSeqNum[tid] = squashed_inst; 732 733 rob->squash(squashed_inst, tid); 734 changedROBNumEntries[tid] = true; 735 736 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 737 738 toIEW->commitInfo[tid].squash = true; 739 740 // Send back the rob squashing signal so other stages know that 741 // the ROB is in the process of squashing. 742 toIEW->commitInfo[tid].robSquashing = true; 743 744 toIEW->commitInfo[tid].branchMispredict = 745 fromIEW->branchMispredict[tid]; 746 747 toIEW->commitInfo[tid].branchTaken = 748 fromIEW->branchTaken[tid]; 749 750 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 751 752 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 753 754 if (toIEW->commitInfo[tid].branchMispredict) { 755 ++branchMispredicts; 756 } 757 } 758 759 } 760 761 setNextStatus(); 762 763 if (squashCounter != numThreads) { 764 // If we're not currently squashing, then get instructions. 765 getInsts(); 766 767 // Try to commit any instructions. 768 commitInsts(); 769 } 770 771 //Check for any activity 772 threads = (*activeThreads).begin(); 773 774 while (threads != (*activeThreads).end()) { 775 unsigned tid = *threads++; 776 777 if (changedROBNumEntries[tid]) { 778 toIEW->commitInfo[tid].usedROB = true; 779 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 780 781 if (rob->isEmpty(tid)) { 782 toIEW->commitInfo[tid].emptyROB = true; 783 } 784 785 wroteToTimeBuffer = true; 786 changedROBNumEntries[tid] = false; 787 } 788 } 789} 790 791template <class Impl> 792void 793DefaultCommit<Impl>::commitInsts() 794{ 795 //////////////////////////////////// 796 // Handle commit 797 // Note that commit will be handled prior to putting new 798 // instructions in the ROB so that the ROB only tries to commit 799 // instructions it has in this current cycle, and not instructions 800 // it is writing in during this cycle. Can't commit and squash 801 // things at the same time... 802 //////////////////////////////////// 803 804 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 805 806 unsigned num_committed = 0; 807 808 DynInstPtr head_inst; 809 810 // Commit as many instructions as possible until the commit bandwidth 811 // limit is reached, or it becomes impossible to commit any more. 812 while (num_committed < commitWidth) { 813 int commit_thread = getCommittingThread(); 814 815 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 816 break; 817 818 head_inst = rob->readHeadInst(commit_thread); 819 820 int tid = head_inst->threadNumber; 821 822 assert(tid == commit_thread); 823 824 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 825 head_inst->seqNum, tid); 826 827 // If the head instruction is squashed, it is ready to retire 828 // (be removed from the ROB) at any time. 829 if (head_inst->isSquashed()) { 830 831 DPRINTF(Commit, "Retiring squashed instruction from " 832 "ROB.\n"); 833 834 rob->retireHead(commit_thread); 835 836 ++commitSquashedInsts; 837 838 // Record that the number of ROB entries has changed. 839 changedROBNumEntries[tid] = true; 840 } else { 841 PC[tid] = head_inst->readPC(); 842 nextPC[tid] = head_inst->readNextPC(); 843 844 // Increment the total number of non-speculative instructions 845 // executed. 846 // Hack for now: it really shouldn't happen until after the 847 // commit is deemed to be successful, but this count is needed 848 // for syscalls. 849 thread[tid]->funcExeInst++; 850 851 // Try to commit the head instruction. 852 bool commit_success = commitHead(head_inst, num_committed); 853 854 if (commit_success) { 855 ++num_committed; 856 857 changedROBNumEntries[tid] = true; 858 859 // Set the doneSeqNum to the youngest committed instruction. 860 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 861 862 ++commitCommittedInsts; 863 864 // To match the old model, don't count nops and instruction 865 // prefetches towards the total commit count. 866 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 867 cpu->instDone(tid); 868 } 869 870 PC[tid] = nextPC[tid]; 871 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 872#if FULL_SYSTEM 873 int count = 0; 874 Addr oldpc; 875 do { 876 // Debug statement. Checks to make sure we're not 877 // currently updating state while handling PC events. 878 if (count == 0) 879 assert(!thread[tid]->inSyscall && 880 !thread[tid]->trapPending); 881 oldpc = PC[tid]; 882 cpu->system->pcEventQueue.service( 883 thread[tid]->getTC()); 884 count++; 885 } while (oldpc != PC[tid]); 886 if (count > 1) { 887 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 888 break; 889 } 890#endif 891 } else { 892 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 893 "[tid:%i] [sn:%i].\n", 894 head_inst->readPC(), tid ,head_inst->seqNum); 895 break; 896 } 897 } 898 } 899 900 DPRINTF(CommitRate, "%i\n", num_committed); 901 numCommittedDist.sample(num_committed); 902 903 if (num_committed == commitWidth) { 904 commitEligibleSamples++; 905 } 906} 907 908template <class Impl> 909bool 910DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 911{ 912 assert(head_inst); 913 914 int tid = head_inst->threadNumber; 915 916 // If the instruction is not executed yet, then it will need extra 917 // handling. Signal backwards that it should be executed. 918 if (!head_inst->isExecuted()) { 919 // Keep this number correct. We have not yet actually executed 920 // and committed this instruction. 921 thread[tid]->funcExeInst--; 922 923 head_inst->setAtCommit(); 924 925 if (head_inst->isNonSpeculative() || 926 head_inst->isStoreConditional() || 927 head_inst->isMemBarrier() || 928 head_inst->isWriteBarrier()) { 929 930 DPRINTF(Commit, "Encountered a barrier or non-speculative " 931 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 932 head_inst->seqNum, head_inst->readPC()); 933 934#if !FULL_SYSTEM 935 // Hack to make sure syscalls/memory barriers/quiesces 936 // aren't executed until all stores write back their data. 937 // This direct communication shouldn't be used for 938 // anything other than this. 939 if (inst_num > 0 || iewStage->hasStoresToWB()) 940#else 941 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 942 head_inst->isQuiesce()) && 943 iewStage->hasStoresToWB()) 944#endif 945 { 946 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 947 return false; 948 } 949 950 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 951 952 // Change the instruction so it won't try to commit again until 953 // it is executed. 954 head_inst->clearCanCommit(); 955 956 ++commitNonSpecStalls; 957 958 return false; 959 } else if (head_inst->isLoad()) { 960 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 961 head_inst->seqNum, head_inst->readPC()); 962 963 // Send back the non-speculative instruction's sequence 964 // number. Tell the lsq to re-execute the load. 965 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 966 toIEW->commitInfo[tid].uncached = true; 967 toIEW->commitInfo[tid].uncachedLoad = head_inst; 968 969 head_inst->clearCanCommit(); 970 971 return false; 972 } else { 973 panic("Trying to commit un-executed instruction " 974 "of unknown type!\n"); 975 } 976 } 977 978 if (head_inst->isThreadSync()) { 979 // Not handled for now. 980 panic("Thread sync instructions are not handled yet.\n"); 981 } 982 983 // Stores mark themselves as completed. 984 if (!head_inst->isStore()) { 985 head_inst->setCompleted(); 986 } 987 988#if USE_CHECKER 989 // Use checker prior to updating anything due to traps or PC 990 // based events. 991 if (cpu->checker) { 992 cpu->checker->verify(head_inst); 993 } 994#endif 995 996 // Check if the instruction caused a fault. If so, trap. 997 Fault inst_fault = head_inst->getFault(); 998 999 // DTB will sometimes need the machine instruction for when 1000 // faults happen. So we will set it here, prior to the DTB 1001 // possibly needing it for its fault. 1002 thread[tid]->setInst( 1003 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1004 1005 if (inst_fault != NoFault) { 1006 head_inst->setCompleted(); 1007 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1008 head_inst->seqNum, head_inst->readPC()); 1009 1010 if (iewStage->hasStoresToWB() || inst_num > 0) { 1011 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1012 return false; 1013 } 1014 1015#if USE_CHECKER 1016 if (cpu->checker && head_inst->isStore()) { 1017 cpu->checker->verify(head_inst); 1018 } 1019#endif 1020 1021 assert(!thread[tid]->inSyscall); 1022 1023 // Mark that we're in state update mode so that the trap's 1024 // execution doesn't generate extra squashes. 1025 thread[tid]->inSyscall = true; 1026 1027 // Execute the trap. Although it's slightly unrealistic in 1028 // terms of timing (as it doesn't wait for the full timing of 1029 // the trap event to complete before updating state), it's 1030 // needed to update the state as soon as possible. This 1031 // prevents external agents from changing any specific state 1032 // that the trap need. 1033 cpu->trap(inst_fault, tid); 1034 1035 // Exit state update mode to avoid accidental updating. 1036 thread[tid]->inSyscall = false; 1037 1038 commitStatus[tid] = TrapPending; 1039 1040 // Generate trap squash event. 1041 generateTrapEvent(tid); 1042 1043 return false; 1044 } 1045 1046 updateComInstStats(head_inst); 1047 1048 if (head_inst->traceData) { 1049 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1050 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1051 head_inst->traceData->finalize(); 1052 head_inst->traceData = NULL; 1053 } 1054 1055 // Update the commit rename map 1056 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1057 renameMap[tid]->setEntry(head_inst->destRegIdx(i), 1058 head_inst->renamedDestRegIdx(i)); 1059 } 1060 1061 // Finally clear the head ROB entry. 1062 rob->retireHead(tid); 1063 1064 // Return true to indicate that we have committed an instruction. 1065 return true; 1066} 1067 1068template <class Impl> 1069void 1070DefaultCommit<Impl>::getInsts() 1071{ 1072 // Read any renamed instructions and place them into the ROB. 1073 int insts_to_process = min((int)renameWidth, fromRename->size); 1074 1075 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 1076 { 1077 DynInstPtr inst = fromRename->insts[inst_num]; 1078 int tid = inst->threadNumber; 1079 1080 if (!inst->isSquashed() && 1081 commitStatus[tid] != ROBSquashing) { 1082 changedROBNumEntries[tid] = true; 1083 1084 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1085 inst->readPC(), inst->seqNum, tid); 1086 1087 rob->insertInst(inst); 1088 1089 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1090 1091 youngestSeqNum[tid] = inst->seqNum; 1092 } else { 1093 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1094 "squashed, skipping.\n", 1095 inst->readPC(), inst->seqNum, tid); 1096 } 1097 } 1098} 1099 1100template <class Impl> 1101void 1102DefaultCommit<Impl>::markCompletedInsts() 1103{ 1104 // Grab completed insts out of the IEW instruction queue, and mark 1105 // instructions completed within the ROB. 1106 for (int inst_num = 0; 1107 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1108 ++inst_num) 1109 { 1110 if (!fromIEW->insts[inst_num]->isSquashed()) { 1111 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1112 "within ROB.\n", 1113 fromIEW->insts[inst_num]->threadNumber, 1114 fromIEW->insts[inst_num]->readPC(), 1115 fromIEW->insts[inst_num]->seqNum); 1116 1117 // Mark the instruction as ready to commit. 1118 fromIEW->insts[inst_num]->setCanCommit(); 1119 } 1120 } 1121} 1122 1123template <class Impl> 1124bool 1125DefaultCommit<Impl>::robDoneSquashing() 1126{ 1127 list<unsigned>::iterator threads = (*activeThreads).begin(); 1128 1129 while (threads != (*activeThreads).end()) { 1130 unsigned tid = *threads++; 1131 1132 if (!rob->isDoneSquashing(tid)) 1133 return false; 1134 } 1135 1136 return true; 1137} 1138 1139template <class Impl> 1140void 1141DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1142{ 1143 unsigned thread = inst->threadNumber; 1144 1145 // 1146 // Pick off the software prefetches 1147 // 1148#ifdef TARGET_ALPHA 1149 if (inst->isDataPrefetch()) { 1150 statComSwp[thread]++; 1151 } else { 1152 statComInst[thread]++; 1153 } 1154#else 1155 statComInst[thread]++; 1156#endif 1157 1158 // 1159 // Control Instructions 1160 // 1161 if (inst->isControl()) 1162 statComBranches[thread]++; 1163 1164 // 1165 // Memory references 1166 // 1167 if (inst->isMemRef()) { 1168 statComRefs[thread]++; 1169 1170 if (inst->isLoad()) { 1171 statComLoads[thread]++; 1172 } 1173 } 1174 1175 if (inst->isMemBarrier()) { 1176 statComMembars[thread]++; 1177 } 1178} 1179 1180//////////////////////////////////////// 1181// // 1182// SMT COMMIT POLICY MAINTAINED HERE // 1183// // 1184//////////////////////////////////////// 1185template <class Impl> 1186int 1187DefaultCommit<Impl>::getCommittingThread() 1188{ 1189 if (numThreads > 1) { 1190 switch (commitPolicy) { 1191 1192 case Aggressive: 1193 //If Policy is Aggressive, commit will call 1194 //this function multiple times per 1195 //cycle 1196 return oldestReady(); 1197 1198 case RoundRobin: 1199 return roundRobin(); 1200 1201 case OldestReady: 1202 return oldestReady(); 1203 1204 default: 1205 return -1; 1206 } 1207 } else { 1208 int tid = (*activeThreads).front(); 1209 1210 if (commitStatus[tid] == Running || 1211 commitStatus[tid] == Idle || 1212 commitStatus[tid] == FetchTrapPending) { 1213 return tid; 1214 } else { 1215 return -1; 1216 } 1217 } 1218} 1219 1220template<class Impl> 1221int 1222DefaultCommit<Impl>::roundRobin() 1223{ 1224 list<unsigned>::iterator pri_iter = priority_list.begin(); 1225 list<unsigned>::iterator end = priority_list.end(); 1226 1227 while (pri_iter != end) { 1228 unsigned tid = *pri_iter; 1229 1230 if (commitStatus[tid] == Running || 1231 commitStatus[tid] == Idle || 1232 commitStatus[tid] == FetchTrapPending) { 1233 1234 if (rob->isHeadReady(tid)) { 1235 priority_list.erase(pri_iter); 1236 priority_list.push_back(tid); 1237 1238 return tid; 1239 } 1240 } 1241 1242 pri_iter++; 1243 } 1244 1245 return -1; 1246} 1247 1248template<class Impl> 1249int 1250DefaultCommit<Impl>::oldestReady() 1251{ 1252 unsigned oldest = 0; 1253 bool first = true; 1254 1255 list<unsigned>::iterator threads = (*activeThreads).begin(); 1256 1257 while (threads != (*activeThreads).end()) { 1258 unsigned tid = *threads++; 1259 1260 if (!rob->isEmpty(tid) && 1261 (commitStatus[tid] == Running || 1262 commitStatus[tid] == Idle || 1263 commitStatus[tid] == FetchTrapPending)) { 1264 1265 if (rob->isHeadReady(tid)) { 1266 1267 DynInstPtr head_inst = rob->readHeadInst(tid); 1268 1269 if (first) { 1270 oldest = tid; 1271 first = false; 1272 } else if (head_inst->seqNum < oldest) { 1273 oldest = tid; 1274 } 1275 } 1276 } 1277 } 1278 1279 if (!first) { 1280 return oldest; 1281 } else { 1282 return -1; 1283 } 1284} 1285