commit_impl.hh revision 2831:0a42b294727c
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "config/full_system.hh" 32#include "config/use_checker.hh" 33 34#include <algorithm> 35#include <string> 36 37#include "base/loader/symtab.hh" 38#include "base/timebuf.hh" 39#include "cpu/exetrace.hh" 40#include "cpu/o3/commit.hh" 41#include "cpu/o3/thread_state.hh" 42 43#if USE_CHECKER 44#include "cpu/checker/cpu.hh" 45#endif 46 47using namespace std; 48 49template <class Impl> 50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 51 unsigned _tid) 52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 53{ 54 this->setFlags(Event::AutoDelete); 55} 56 57template <class Impl> 58void 59DefaultCommit<Impl>::TrapEvent::process() 60{ 61 // This will get reset by commit if it was switched out at the 62 // time of this event processing. 63 commit->trapSquash[tid] = true; 64} 65 66template <class Impl> 67const char * 68DefaultCommit<Impl>::TrapEvent::description() 69{ 70 return "Trap event"; 71} 72 73template <class Impl> 74DefaultCommit<Impl>::DefaultCommit(Params *params) 75 : squashCounter(0), 76 iewToCommitDelay(params->iewToCommitDelay), 77 commitToIEWDelay(params->commitToIEWDelay), 78 renameToROBDelay(params->renameToROBDelay), 79 fetchToCommitDelay(params->commitToFetchDelay), 80 renameWidth(params->renameWidth), 81 commitWidth(params->commitWidth), 82 numThreads(params->numberOfThreads), 83 switchPending(false), 84 switchedOut(false), 85 trapLatency(params->trapLatency), 86 fetchTrapLatency(params->fetchTrapLatency) 87{ 88 _status = Active; 89 _nextStatus = Inactive; 90 string policy = params->smtCommitPolicy; 91 92 //Convert string to lowercase 93 std::transform(policy.begin(), policy.end(), policy.begin(), 94 (int(*)(int)) tolower); 95 96 //Assign commit policy 97 if (policy == "aggressive"){ 98 commitPolicy = Aggressive; 99 100 DPRINTF(Commit,"Commit Policy set to Aggressive."); 101 } else if (policy == "roundrobin"){ 102 commitPolicy = RoundRobin; 103 104 //Set-Up Priority List 105 for (int tid=0; tid < numThreads; tid++) { 106 priority_list.push_back(tid); 107 } 108 109 DPRINTF(Commit,"Commit Policy set to Round Robin."); 110 } else if (policy == "oldestready"){ 111 commitPolicy = OldestReady; 112 113 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 114 } else { 115 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 116 "RoundRobin,OldestReady}"); 117 } 118 119 for (int i=0; i < numThreads; i++) { 120 commitStatus[i] = Idle; 121 changedROBNumEntries[i] = false; 122 trapSquash[i] = false; 123 tcSquash[i] = false; 124 PC[i] = nextPC[i] = 0; 125 } 126 127 fetchFaultTick = 0; 128 fetchTrapWait = 0; 129} 130 131template <class Impl> 132std::string 133DefaultCommit<Impl>::name() const 134{ 135 return cpu->name() + ".commit"; 136} 137 138template <class Impl> 139void 140DefaultCommit<Impl>::regStats() 141{ 142 using namespace Stats; 143 commitCommittedInsts 144 .name(name() + ".commitCommittedInsts") 145 .desc("The number of committed instructions") 146 .prereq(commitCommittedInsts); 147 commitSquashedInsts 148 .name(name() + ".commitSquashedInsts") 149 .desc("The number of squashed insts skipped by commit") 150 .prereq(commitSquashedInsts); 151 commitSquashEvents 152 .name(name() + ".commitSquashEvents") 153 .desc("The number of times commit is told to squash") 154 .prereq(commitSquashEvents); 155 commitNonSpecStalls 156 .name(name() + ".commitNonSpecStalls") 157 .desc("The number of times commit has been forced to stall to " 158 "communicate backwards") 159 .prereq(commitNonSpecStalls); 160 branchMispredicts 161 .name(name() + ".branchMispredicts") 162 .desc("The number of times a branch was mispredicted") 163 .prereq(branchMispredicts); 164 numCommittedDist 165 .init(0,commitWidth,1) 166 .name(name() + ".COM:committed_per_cycle") 167 .desc("Number of insts commited each cycle") 168 .flags(Stats::pdf) 169 ; 170 171 statComInst 172 .init(cpu->number_of_threads) 173 .name(name() + ".COM:count") 174 .desc("Number of instructions committed") 175 .flags(total) 176 ; 177 178 statComSwp 179 .init(cpu->number_of_threads) 180 .name(name() + ".COM:swp_count") 181 .desc("Number of s/w prefetches committed") 182 .flags(total) 183 ; 184 185 statComRefs 186 .init(cpu->number_of_threads) 187 .name(name() + ".COM:refs") 188 .desc("Number of memory references committed") 189 .flags(total) 190 ; 191 192 statComLoads 193 .init(cpu->number_of_threads) 194 .name(name() + ".COM:loads") 195 .desc("Number of loads committed") 196 .flags(total) 197 ; 198 199 statComMembars 200 .init(cpu->number_of_threads) 201 .name(name() + ".COM:membars") 202 .desc("Number of memory barriers committed") 203 .flags(total) 204 ; 205 206 statComBranches 207 .init(cpu->number_of_threads) 208 .name(name() + ".COM:branches") 209 .desc("Number of branches committed") 210 .flags(total) 211 ; 212 213 commitEligible 214 .init(cpu->number_of_threads) 215 .name(name() + ".COM:bw_limited") 216 .desc("number of insts not committed due to BW limits") 217 .flags(total) 218 ; 219 220 commitEligibleSamples 221 .name(name() + ".COM:bw_lim_events") 222 .desc("number cycles where commit BW limit reached") 223 ; 224} 225 226template <class Impl> 227void 228DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 229{ 230 DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 231 cpu = cpu_ptr; 232 233 // Commit must broadcast the number of free entries it has at the start of 234 // the simulation, so it starts as active. 235 cpu->activateStage(O3CPU::CommitIdx); 236 237 trapLatency = cpu->cycles(trapLatency); 238 fetchTrapLatency = cpu->cycles(fetchTrapLatency); 239} 240 241template <class Impl> 242void 243DefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 244{ 245 thread = threads; 246} 247 248template <class Impl> 249void 250DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 251{ 252 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 253 timeBuffer = tb_ptr; 254 255 // Setup wire to send information back to IEW. 256 toIEW = timeBuffer->getWire(0); 257 258 // Setup wire to read data from IEW (for the ROB). 259 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 260} 261 262template <class Impl> 263void 264DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 265{ 266 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 267 fetchQueue = fq_ptr; 268 269 // Setup wire to get instructions from rename (for the ROB). 270 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 271} 272 273template <class Impl> 274void 275DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 276{ 277 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 278 renameQueue = rq_ptr; 279 280 // Setup wire to get instructions from rename (for the ROB). 281 fromRename = renameQueue->getWire(-renameToROBDelay); 282} 283 284template <class Impl> 285void 286DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 287{ 288 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 289 iewQueue = iq_ptr; 290 291 // Setup wire to get instructions from IEW. 292 fromIEW = iewQueue->getWire(-iewToCommitDelay); 293} 294 295template <class Impl> 296void 297DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 298{ 299 fetchStage = fetch_stage; 300} 301 302template <class Impl> 303void 304DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 305{ 306 iewStage = iew_stage; 307} 308 309template<class Impl> 310void 311DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 312{ 313 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 314 activeThreads = at_ptr; 315} 316 317template <class Impl> 318void 319DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 320{ 321 DPRINTF(Commit, "Setting rename map pointers.\n"); 322 323 for (int i=0; i < numThreads; i++) { 324 renameMap[i] = &rm_ptr[i]; 325 } 326} 327 328template <class Impl> 329void 330DefaultCommit<Impl>::setROB(ROB *rob_ptr) 331{ 332 DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 333 rob = rob_ptr; 334} 335 336template <class Impl> 337void 338DefaultCommit<Impl>::initStage() 339{ 340 rob->setActiveThreads(activeThreads); 341 rob->resetEntries(); 342 343 // Broadcast the number of free entries. 344 for (int i=0; i < numThreads; i++) { 345 toIEW->commitInfo[i].usedROB = true; 346 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 347 } 348 349 cpu->activityThisCycle(); 350} 351 352template <class Impl> 353void 354DefaultCommit<Impl>::switchOut() 355{ 356 switchPending = true; 357} 358 359template <class Impl> 360void 361DefaultCommit<Impl>::doSwitchOut() 362{ 363 switchedOut = true; 364 switchPending = false; 365 rob->switchOut(); 366} 367 368template <class Impl> 369void 370DefaultCommit<Impl>::takeOverFrom() 371{ 372 switchedOut = false; 373 _status = Active; 374 _nextStatus = Inactive; 375 for (int i=0; i < numThreads; i++) { 376 commitStatus[i] = Idle; 377 changedROBNumEntries[i] = false; 378 trapSquash[i] = false; 379 tcSquash[i] = false; 380 } 381 squashCounter = 0; 382 rob->takeOverFrom(); 383} 384 385template <class Impl> 386void 387DefaultCommit<Impl>::updateStatus() 388{ 389 // reset ROB changed variable 390 list<unsigned>::iterator threads = (*activeThreads).begin(); 391 while (threads != (*activeThreads).end()) { 392 unsigned tid = *threads++; 393 changedROBNumEntries[tid] = false; 394 395 // Also check if any of the threads has a trap pending 396 if (commitStatus[tid] == TrapPending || 397 commitStatus[tid] == FetchTrapPending) { 398 _nextStatus = Active; 399 } 400 } 401 402 if (_nextStatus == Inactive && _status == Active) { 403 DPRINTF(Activity, "Deactivating stage.\n"); 404 cpu->deactivateStage(O3CPU::CommitIdx); 405 } else if (_nextStatus == Active && _status == Inactive) { 406 DPRINTF(Activity, "Activating stage.\n"); 407 cpu->activateStage(O3CPU::CommitIdx); 408 } 409 410 _status = _nextStatus; 411} 412 413template <class Impl> 414void 415DefaultCommit<Impl>::setNextStatus() 416{ 417 int squashes = 0; 418 419 list<unsigned>::iterator threads = (*activeThreads).begin(); 420 421 while (threads != (*activeThreads).end()) { 422 unsigned tid = *threads++; 423 424 if (commitStatus[tid] == ROBSquashing) { 425 squashes++; 426 } 427 } 428 429 squashCounter = squashes; 430 431 // If commit is currently squashing, then it will have activity for the 432 // next cycle. Set its next status as active. 433 if (squashCounter) { 434 _nextStatus = Active; 435 } 436} 437 438template <class Impl> 439bool 440DefaultCommit<Impl>::changedROBEntries() 441{ 442 list<unsigned>::iterator threads = (*activeThreads).begin(); 443 444 while (threads != (*activeThreads).end()) { 445 unsigned tid = *threads++; 446 447 if (changedROBNumEntries[tid]) { 448 return true; 449 } 450 } 451 452 return false; 453} 454 455template <class Impl> 456unsigned 457DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 458{ 459 return rob->numFreeEntries(tid); 460} 461 462template <class Impl> 463void 464DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 465{ 466 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 467 468 TrapEvent *trap = new TrapEvent(this, tid); 469 470 trap->schedule(curTick + trapLatency); 471 472 thread[tid]->trapPending = true; 473} 474 475template <class Impl> 476void 477DefaultCommit<Impl>::generateTCEvent(unsigned tid) 478{ 479 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 480 481 tcSquash[tid] = true; 482} 483 484template <class Impl> 485void 486DefaultCommit<Impl>::squashAll(unsigned tid) 487{ 488 // If we want to include the squashing instruction in the squash, 489 // then use one older sequence number. 490 // Hopefully this doesn't mess things up. Basically I want to squash 491 // all instructions of this thread. 492 InstSeqNum squashed_inst = rob->isEmpty() ? 493 0 : rob->readHeadInst(tid)->seqNum - 1;; 494 495 // All younger instructions will be squashed. Set the sequence 496 // number as the youngest instruction in the ROB (0 in this case. 497 // Hopefully nothing breaks.) 498 youngestSeqNum[tid] = 0; 499 500 rob->squash(squashed_inst, tid); 501 changedROBNumEntries[tid] = true; 502 503 // Send back the sequence number of the squashed instruction. 504 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 505 506 // Send back the squash signal to tell stages that they should 507 // squash. 508 toIEW->commitInfo[tid].squash = true; 509 510 // Send back the rob squashing signal so other stages know that 511 // the ROB is in the process of squashing. 512 toIEW->commitInfo[tid].robSquashing = true; 513 514 toIEW->commitInfo[tid].branchMispredict = false; 515 516 toIEW->commitInfo[tid].nextPC = PC[tid]; 517} 518 519template <class Impl> 520void 521DefaultCommit<Impl>::squashFromTrap(unsigned tid) 522{ 523 squashAll(tid); 524 525 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 526 527 thread[tid]->trapPending = false; 528 thread[tid]->inSyscall = false; 529 530 trapSquash[tid] = false; 531 532 commitStatus[tid] = ROBSquashing; 533 cpu->activityThisCycle(); 534} 535 536template <class Impl> 537void 538DefaultCommit<Impl>::squashFromTC(unsigned tid) 539{ 540 squashAll(tid); 541 542 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 543 544 thread[tid]->inSyscall = false; 545 assert(!thread[tid]->trapPending); 546 547 commitStatus[tid] = ROBSquashing; 548 cpu->activityThisCycle(); 549 550 tcSquash[tid] = false; 551} 552 553template <class Impl> 554void 555DefaultCommit<Impl>::tick() 556{ 557 wroteToTimeBuffer = false; 558 _nextStatus = Inactive; 559 560 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 561 cpu->signalSwitched(); 562 return; 563 } 564 565 list<unsigned>::iterator threads = (*activeThreads).begin(); 566 567 // Check if any of the threads are done squashing. Change the 568 // status if they are done. 569 while (threads != (*activeThreads).end()) { 570 unsigned tid = *threads++; 571 572 if (commitStatus[tid] == ROBSquashing) { 573 574 if (rob->isDoneSquashing(tid)) { 575 commitStatus[tid] = Running; 576 } else { 577 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 578 "insts this cycle.\n", tid); 579 rob->doSquash(tid); 580 toIEW->commitInfo[tid].robSquashing = true; 581 wroteToTimeBuffer = true; 582 } 583 } 584 } 585 586 commit(); 587 588 markCompletedInsts(); 589 590 threads = (*activeThreads).begin(); 591 592 while (threads != (*activeThreads).end()) { 593 unsigned tid = *threads++; 594 595 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 596 // The ROB has more instructions it can commit. Its next status 597 // will be active. 598 _nextStatus = Active; 599 600 DynInstPtr inst = rob->readHeadInst(tid); 601 602 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 603 " ROB and ready to commit\n", 604 tid, inst->seqNum, inst->readPC()); 605 606 } else if (!rob->isEmpty(tid)) { 607 DynInstPtr inst = rob->readHeadInst(tid); 608 609 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 610 "%#x is head of ROB and not ready\n", 611 tid, inst->seqNum, inst->readPC()); 612 } 613 614 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 615 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 616 } 617 618 619 if (wroteToTimeBuffer) { 620 DPRINTF(Activity, "Activity This Cycle.\n"); 621 cpu->activityThisCycle(); 622 } 623 624 updateStatus(); 625} 626 627template <class Impl> 628void 629DefaultCommit<Impl>::commit() 630{ 631 632 ////////////////////////////////////// 633 // Check for interrupts 634 ////////////////////////////////////// 635 636#if FULL_SYSTEM 637 // Process interrupts if interrupts are enabled, not in PAL mode, 638 // and no other traps or external squashes are currently pending. 639 // @todo: Allow other threads to handle interrupts. 640 if (cpu->checkInterrupts && 641 cpu->check_interrupts() && 642 !cpu->inPalMode(readPC()) && 643 !trapSquash[0] && 644 !tcSquash[0]) { 645 // Tell fetch that there is an interrupt pending. This will 646 // make fetch wait until it sees a non PAL-mode PC, at which 647 // point it stops fetching instructions. 648 toIEW->commitInfo[0].interruptPending = true; 649 650 // Wait until the ROB is empty and all stores have drained in 651 // order to enter the interrupt. 652 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 653 // Not sure which thread should be the one to interrupt. For now 654 // always do thread 0. 655 assert(!thread[0]->inSyscall); 656 thread[0]->inSyscall = true; 657 658 // CPU will handle implementation of the interrupt. 659 cpu->processInterrupts(); 660 661 // Now squash or record that I need to squash this cycle. 662 commitStatus[0] = TrapPending; 663 664 // Exit state update mode to avoid accidental updating. 665 thread[0]->inSyscall = false; 666 667 // Generate trap squash event. 668 generateTrapEvent(0); 669 670 toIEW->commitInfo[0].clearInterrupt = true; 671 672 DPRINTF(Commit, "Interrupt detected.\n"); 673 } else { 674 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 675 } 676 } 677#endif // FULL_SYSTEM 678 679 //////////////////////////////////// 680 // Check for any possible squashes, handle them first 681 //////////////////////////////////// 682 683 list<unsigned>::iterator threads = (*activeThreads).begin(); 684 685 while (threads != (*activeThreads).end()) { 686 unsigned tid = *threads++; 687 688 // Not sure which one takes priority. I think if we have 689 // both, that's a bad sign. 690 if (trapSquash[tid] == true) { 691 assert(!tcSquash[tid]); 692 squashFromTrap(tid); 693 } else if (tcSquash[tid] == true) { 694 squashFromTC(tid); 695 } 696 697 // Squashed sequence number must be older than youngest valid 698 // instruction in the ROB. This prevents squashes from younger 699 // instructions overriding squashes from older instructions. 700 if (fromIEW->squash[tid] && 701 commitStatus[tid] != TrapPending && 702 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 703 704 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 705 tid, 706 fromIEW->mispredPC[tid], 707 fromIEW->squashedSeqNum[tid]); 708 709 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 710 tid, 711 fromIEW->nextPC[tid]); 712 713 commitStatus[tid] = ROBSquashing; 714 715 // If we want to include the squashing instruction in the squash, 716 // then use one older sequence number. 717 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 718 719 if (fromIEW->includeSquashInst[tid] == true) 720 squashed_inst--; 721 722 // All younger instructions will be squashed. Set the sequence 723 // number as the youngest instruction in the ROB. 724 youngestSeqNum[tid] = squashed_inst; 725 726 rob->squash(squashed_inst, tid); 727 changedROBNumEntries[tid] = true; 728 729 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 730 731 toIEW->commitInfo[tid].squash = true; 732 733 // Send back the rob squashing signal so other stages know that 734 // the ROB is in the process of squashing. 735 toIEW->commitInfo[tid].robSquashing = true; 736 737 toIEW->commitInfo[tid].branchMispredict = 738 fromIEW->branchMispredict[tid]; 739 740 toIEW->commitInfo[tid].branchTaken = 741 fromIEW->branchTaken[tid]; 742 743 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 744 745 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 746 747 if (toIEW->commitInfo[tid].branchMispredict) { 748 ++branchMispredicts; 749 } 750 } 751 752 } 753 754 setNextStatus(); 755 756 if (squashCounter != numThreads) { 757 // If we're not currently squashing, then get instructions. 758 getInsts(); 759 760 // Try to commit any instructions. 761 commitInsts(); 762 } 763 764 //Check for any activity 765 threads = (*activeThreads).begin(); 766 767 while (threads != (*activeThreads).end()) { 768 unsigned tid = *threads++; 769 770 if (changedROBNumEntries[tid]) { 771 toIEW->commitInfo[tid].usedROB = true; 772 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 773 774 if (rob->isEmpty(tid)) { 775 toIEW->commitInfo[tid].emptyROB = true; 776 } 777 778 wroteToTimeBuffer = true; 779 changedROBNumEntries[tid] = false; 780 } 781 } 782} 783 784template <class Impl> 785void 786DefaultCommit<Impl>::commitInsts() 787{ 788 //////////////////////////////////// 789 // Handle commit 790 // Note that commit will be handled prior to putting new 791 // instructions in the ROB so that the ROB only tries to commit 792 // instructions it has in this current cycle, and not instructions 793 // it is writing in during this cycle. Can't commit and squash 794 // things at the same time... 795 //////////////////////////////////// 796 797 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 798 799 unsigned num_committed = 0; 800 801 DynInstPtr head_inst; 802 803 // Commit as many instructions as possible until the commit bandwidth 804 // limit is reached, or it becomes impossible to commit any more. 805 while (num_committed < commitWidth) { 806 int commit_thread = getCommittingThread(); 807 808 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 809 break; 810 811 head_inst = rob->readHeadInst(commit_thread); 812 813 int tid = head_inst->threadNumber; 814 815 assert(tid == commit_thread); 816 817 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 818 head_inst->seqNum, tid); 819 820 // If the head instruction is squashed, it is ready to retire 821 // (be removed from the ROB) at any time. 822 if (head_inst->isSquashed()) { 823 824 DPRINTF(Commit, "Retiring squashed instruction from " 825 "ROB.\n"); 826 827 rob->retireHead(commit_thread); 828 829 ++commitSquashedInsts; 830 831 // Record that the number of ROB entries has changed. 832 changedROBNumEntries[tid] = true; 833 } else { 834 PC[tid] = head_inst->readPC(); 835 nextPC[tid] = head_inst->readNextPC(); 836 837 // Increment the total number of non-speculative instructions 838 // executed. 839 // Hack for now: it really shouldn't happen until after the 840 // commit is deemed to be successful, but this count is needed 841 // for syscalls. 842 thread[tid]->funcExeInst++; 843 844 // Try to commit the head instruction. 845 bool commit_success = commitHead(head_inst, num_committed); 846 847 if (commit_success) { 848 ++num_committed; 849 850 changedROBNumEntries[tid] = true; 851 852 // Set the doneSeqNum to the youngest committed instruction. 853 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 854 855 ++commitCommittedInsts; 856 857 // To match the old model, don't count nops and instruction 858 // prefetches towards the total commit count. 859 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 860 cpu->instDone(tid); 861 } 862 863 PC[tid] = nextPC[tid]; 864 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 865#if FULL_SYSTEM 866 int count = 0; 867 Addr oldpc; 868 do { 869 // Debug statement. Checks to make sure we're not 870 // currently updating state while handling PC events. 871 if (count == 0) 872 assert(!thread[tid]->inSyscall && 873 !thread[tid]->trapPending); 874 oldpc = PC[tid]; 875 cpu->system->pcEventQueue.service( 876 thread[tid]->getTC()); 877 count++; 878 } while (oldpc != PC[tid]); 879 if (count > 1) { 880 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 881 break; 882 } 883#endif 884 } else { 885 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 886 "[tid:%i] [sn:%i].\n", 887 head_inst->readPC(), tid ,head_inst->seqNum); 888 break; 889 } 890 } 891 } 892 893 DPRINTF(CommitRate, "%i\n", num_committed); 894 numCommittedDist.sample(num_committed); 895 896 if (num_committed == commitWidth) { 897 commitEligibleSamples++; 898 } 899} 900 901template <class Impl> 902bool 903DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 904{ 905 assert(head_inst); 906 907 int tid = head_inst->threadNumber; 908 909 // If the instruction is not executed yet, then it will need extra 910 // handling. Signal backwards that it should be executed. 911 if (!head_inst->isExecuted()) { 912 // Keep this number correct. We have not yet actually executed 913 // and committed this instruction. 914 thread[tid]->funcExeInst--; 915 916 head_inst->setAtCommit(); 917 918 if (head_inst->isNonSpeculative() || 919 head_inst->isStoreConditional() || 920 head_inst->isMemBarrier() || 921 head_inst->isWriteBarrier()) { 922 923 DPRINTF(Commit, "Encountered a barrier or non-speculative " 924 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 925 head_inst->seqNum, head_inst->readPC()); 926 927#if !FULL_SYSTEM 928 // Hack to make sure syscalls/memory barriers/quiesces 929 // aren't executed until all stores write back their data. 930 // This direct communication shouldn't be used for 931 // anything other than this. 932 if (inst_num > 0 || iewStage->hasStoresToWB()) 933#else 934 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 935 head_inst->isQuiesce()) && 936 iewStage->hasStoresToWB()) 937#endif 938 { 939 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 940 return false; 941 } 942 943 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 944 945 // Change the instruction so it won't try to commit again until 946 // it is executed. 947 head_inst->clearCanCommit(); 948 949 ++commitNonSpecStalls; 950 951 return false; 952 } else if (head_inst->isLoad()) { 953 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 954 head_inst->seqNum, head_inst->readPC()); 955 956 // Send back the non-speculative instruction's sequence 957 // number. Tell the lsq to re-execute the load. 958 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 959 toIEW->commitInfo[tid].uncached = true; 960 toIEW->commitInfo[tid].uncachedLoad = head_inst; 961 962 head_inst->clearCanCommit(); 963 964 return false; 965 } else { 966 panic("Trying to commit un-executed instruction " 967 "of unknown type!\n"); 968 } 969 } 970 971 if (head_inst->isThreadSync()) { 972 // Not handled for now. 973 panic("Thread sync instructions are not handled yet.\n"); 974 } 975 976 // Stores mark themselves as completed. 977 if (!head_inst->isStore()) { 978 head_inst->setCompleted(); 979 } 980 981#if USE_CHECKER 982 // Use checker prior to updating anything due to traps or PC 983 // based events. 984 if (cpu->checker) { 985 cpu->checker->verify(head_inst); 986 } 987#endif 988 989 // Check if the instruction caused a fault. If so, trap. 990 Fault inst_fault = head_inst->getFault(); 991 992 if (inst_fault != NoFault) { 993 head_inst->setCompleted(); 994 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 995 head_inst->seqNum, head_inst->readPC()); 996 997 if (iewStage->hasStoresToWB() || inst_num > 0) { 998 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 999 return false; 1000 } 1001 1002#if USE_CHECKER 1003 if (cpu->checker && head_inst->isStore()) { 1004 cpu->checker->verify(head_inst); 1005 } 1006#endif 1007 1008 assert(!thread[tid]->inSyscall); 1009 1010 // Mark that we're in state update mode so that the trap's 1011 // execution doesn't generate extra squashes. 1012 thread[tid]->inSyscall = true; 1013 1014 // DTB will sometimes need the machine instruction for when 1015 // faults happen. So we will set it here, prior to the DTB 1016 // possibly needing it for its fault. 1017 thread[tid]->setInst( 1018 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1019 1020 // Execute the trap. Although it's slightly unrealistic in 1021 // terms of timing (as it doesn't wait for the full timing of 1022 // the trap event to complete before updating state), it's 1023 // needed to update the state as soon as possible. This 1024 // prevents external agents from changing any specific state 1025 // that the trap need. 1026 cpu->trap(inst_fault, tid); 1027 1028 // Exit state update mode to avoid accidental updating. 1029 thread[tid]->inSyscall = false; 1030 1031 commitStatus[tid] = TrapPending; 1032 1033 // Generate trap squash event. 1034 generateTrapEvent(tid); 1035 1036 return false; 1037 } 1038 1039 updateComInstStats(head_inst); 1040 1041 if (head_inst->traceData) { 1042 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1043 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1044 head_inst->traceData->finalize(); 1045 head_inst->traceData = NULL; 1046 } 1047 1048 // Update the commit rename map 1049 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1050 renameMap[tid]->setEntry(head_inst->destRegIdx(i), 1051 head_inst->renamedDestRegIdx(i)); 1052 } 1053 1054 // Finally clear the head ROB entry. 1055 rob->retireHead(tid); 1056 1057 // Return true to indicate that we have committed an instruction. 1058 return true; 1059} 1060 1061template <class Impl> 1062void 1063DefaultCommit<Impl>::getInsts() 1064{ 1065 // Read any renamed instructions and place them into the ROB. 1066 int insts_to_process = min((int)renameWidth, fromRename->size); 1067 1068 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 1069 { 1070 DynInstPtr inst = fromRename->insts[inst_num]; 1071 int tid = inst->threadNumber; 1072 1073 if (!inst->isSquashed() && 1074 commitStatus[tid] != ROBSquashing) { 1075 changedROBNumEntries[tid] = true; 1076 1077 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1078 inst->readPC(), inst->seqNum, tid); 1079 1080 rob->insertInst(inst); 1081 1082 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1083 1084 youngestSeqNum[tid] = inst->seqNum; 1085 } else { 1086 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1087 "squashed, skipping.\n", 1088 inst->readPC(), inst->seqNum, tid); 1089 } 1090 } 1091} 1092 1093template <class Impl> 1094void 1095DefaultCommit<Impl>::markCompletedInsts() 1096{ 1097 // Grab completed insts out of the IEW instruction queue, and mark 1098 // instructions completed within the ROB. 1099 for (int inst_num = 0; 1100 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1101 ++inst_num) 1102 { 1103 if (!fromIEW->insts[inst_num]->isSquashed()) { 1104 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1105 "within ROB.\n", 1106 fromIEW->insts[inst_num]->threadNumber, 1107 fromIEW->insts[inst_num]->readPC(), 1108 fromIEW->insts[inst_num]->seqNum); 1109 1110 // Mark the instruction as ready to commit. 1111 fromIEW->insts[inst_num]->setCanCommit(); 1112 } 1113 } 1114} 1115 1116template <class Impl> 1117bool 1118DefaultCommit<Impl>::robDoneSquashing() 1119{ 1120 list<unsigned>::iterator threads = (*activeThreads).begin(); 1121 1122 while (threads != (*activeThreads).end()) { 1123 unsigned tid = *threads++; 1124 1125 if (!rob->isDoneSquashing(tid)) 1126 return false; 1127 } 1128 1129 return true; 1130} 1131 1132template <class Impl> 1133void 1134DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1135{ 1136 unsigned thread = inst->threadNumber; 1137 1138 // 1139 // Pick off the software prefetches 1140 // 1141#ifdef TARGET_ALPHA 1142 if (inst->isDataPrefetch()) { 1143 statComSwp[thread]++; 1144 } else { 1145 statComInst[thread]++; 1146 } 1147#else 1148 statComInst[thread]++; 1149#endif 1150 1151 // 1152 // Control Instructions 1153 // 1154 if (inst->isControl()) 1155 statComBranches[thread]++; 1156 1157 // 1158 // Memory references 1159 // 1160 if (inst->isMemRef()) { 1161 statComRefs[thread]++; 1162 1163 if (inst->isLoad()) { 1164 statComLoads[thread]++; 1165 } 1166 } 1167 1168 if (inst->isMemBarrier()) { 1169 statComMembars[thread]++; 1170 } 1171} 1172 1173//////////////////////////////////////// 1174// // 1175// SMT COMMIT POLICY MAINTAINED HERE // 1176// // 1177//////////////////////////////////////// 1178template <class Impl> 1179int 1180DefaultCommit<Impl>::getCommittingThread() 1181{ 1182 if (numThreads > 1) { 1183 switch (commitPolicy) { 1184 1185 case Aggressive: 1186 //If Policy is Aggressive, commit will call 1187 //this function multiple times per 1188 //cycle 1189 return oldestReady(); 1190 1191 case RoundRobin: 1192 return roundRobin(); 1193 1194 case OldestReady: 1195 return oldestReady(); 1196 1197 default: 1198 return -1; 1199 } 1200 } else { 1201 int tid = (*activeThreads).front(); 1202 1203 if (commitStatus[tid] == Running || 1204 commitStatus[tid] == Idle || 1205 commitStatus[tid] == FetchTrapPending) { 1206 return tid; 1207 } else { 1208 return -1; 1209 } 1210 } 1211} 1212 1213template<class Impl> 1214int 1215DefaultCommit<Impl>::roundRobin() 1216{ 1217 list<unsigned>::iterator pri_iter = priority_list.begin(); 1218 list<unsigned>::iterator end = priority_list.end(); 1219 1220 while (pri_iter != end) { 1221 unsigned tid = *pri_iter; 1222 1223 if (commitStatus[tid] == Running || 1224 commitStatus[tid] == Idle || 1225 commitStatus[tid] == FetchTrapPending) { 1226 1227 if (rob->isHeadReady(tid)) { 1228 priority_list.erase(pri_iter); 1229 priority_list.push_back(tid); 1230 1231 return tid; 1232 } 1233 } 1234 1235 pri_iter++; 1236 } 1237 1238 return -1; 1239} 1240 1241template<class Impl> 1242int 1243DefaultCommit<Impl>::oldestReady() 1244{ 1245 unsigned oldest = 0; 1246 bool first = true; 1247 1248 list<unsigned>::iterator threads = (*activeThreads).begin(); 1249 1250 while (threads != (*activeThreads).end()) { 1251 unsigned tid = *threads++; 1252 1253 if (!rob->isEmpty(tid) && 1254 (commitStatus[tid] == Running || 1255 commitStatus[tid] == Idle || 1256 commitStatus[tid] == FetchTrapPending)) { 1257 1258 if (rob->isHeadReady(tid)) { 1259 1260 DynInstPtr head_inst = rob->readHeadInst(tid); 1261 1262 if (first) { 1263 oldest = tid; 1264 first = false; 1265 } else if (head_inst->seqNum < oldest) { 1266 oldest = tid; 1267 } 1268 } 1269 } 1270 } 1271 1272 if (!first) { 1273 return oldest; 1274 } else { 1275 return -1; 1276 } 1277} 1278