commit_impl.hh revision 2654:9559cfa91b9d
113481Sgiacomo.travaglini@arm.com/* 213481Sgiacomo.travaglini@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 313481Sgiacomo.travaglini@arm.com * All rights reserved. 413481Sgiacomo.travaglini@arm.com * 513481Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 613481Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 713481Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 813481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 913481Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1013481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1113481Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1213481Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1313481Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1413481Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1513481Sgiacomo.travaglini@arm.com * 1613481Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713481Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813481Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913481Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013481Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113481Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213481Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313481Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413481Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513481Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613481Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713481Sgiacomo.travaglini@arm.com */ 2813481Sgiacomo.travaglini@arm.com 2913481Sgiacomo.travaglini@arm.com#include <algorithm> 3013481Sgiacomo.travaglini@arm.com#include <string> 3113481Sgiacomo.travaglini@arm.com 3213481Sgiacomo.travaglini@arm.com#include "base/loader/symtab.hh" 3313481Sgiacomo.travaglini@arm.com#include "base/timebuf.hh" 3413481Sgiacomo.travaglini@arm.com#include "cpu/checker/cpu.hh" 3513481Sgiacomo.travaglini@arm.com#include "cpu/exetrace.hh" 3613481Sgiacomo.travaglini@arm.com#include "cpu/o3/commit.hh" 3713481Sgiacomo.travaglini@arm.com#include "cpu/o3/thread_state.hh" 3813481Sgiacomo.travaglini@arm.com 3913481Sgiacomo.travaglini@arm.comusing namespace std; 4013481Sgiacomo.travaglini@arm.com 4113481Sgiacomo.travaglini@arm.comtemplate <class Impl> 4213481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 4313481Sgiacomo.travaglini@arm.com unsigned _tid) 4413481Sgiacomo.travaglini@arm.com : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 4513481Sgiacomo.travaglini@arm.com{ 4613481Sgiacomo.travaglini@arm.com this->setFlags(Event::AutoDelete); 4713481Sgiacomo.travaglini@arm.com} 4813481Sgiacomo.travaglini@arm.com 4913481Sgiacomo.travaglini@arm.comtemplate <class Impl> 5013481Sgiacomo.travaglini@arm.comvoid 5113481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::TrapEvent::process() 5213481Sgiacomo.travaglini@arm.com{ 5313481Sgiacomo.travaglini@arm.com // This will get reset by commit if it was switched out at the 5413481Sgiacomo.travaglini@arm.com // time of this event processing. 5513481Sgiacomo.travaglini@arm.com commit->trapSquash[tid] = true; 5613481Sgiacomo.travaglini@arm.com} 5713481Sgiacomo.travaglini@arm.com 5813481Sgiacomo.travaglini@arm.comtemplate <class Impl> 5913481Sgiacomo.travaglini@arm.comconst char * 6013481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::TrapEvent::description() 6113481Sgiacomo.travaglini@arm.com{ 6213481Sgiacomo.travaglini@arm.com return "Trap event"; 6313481Sgiacomo.travaglini@arm.com} 6413481Sgiacomo.travaglini@arm.com 6513481Sgiacomo.travaglini@arm.comtemplate <class Impl> 6613481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::DefaultCommit(Params *params) 6713481Sgiacomo.travaglini@arm.com : dcacheInterface(params->dcacheInterface), 6813481Sgiacomo.travaglini@arm.com squashCounter(0), 6913481Sgiacomo.travaglini@arm.com iewToCommitDelay(params->iewToCommitDelay), 7013481Sgiacomo.travaglini@arm.com commitToIEWDelay(params->commitToIEWDelay), 7113481Sgiacomo.travaglini@arm.com renameToROBDelay(params->renameToROBDelay), 7213481Sgiacomo.travaglini@arm.com fetchToCommitDelay(params->commitToFetchDelay), 7313481Sgiacomo.travaglini@arm.com renameWidth(params->renameWidth), 7413481Sgiacomo.travaglini@arm.com iewWidth(params->executeWidth), 7513481Sgiacomo.travaglini@arm.com commitWidth(params->commitWidth), 7613481Sgiacomo.travaglini@arm.com numThreads(params->numberOfThreads), 7713481Sgiacomo.travaglini@arm.com switchedOut(false), 7813481Sgiacomo.travaglini@arm.com trapLatency(params->trapLatency), 7913481Sgiacomo.travaglini@arm.com fetchTrapLatency(params->fetchTrapLatency) 8013481Sgiacomo.travaglini@arm.com{ 8113481Sgiacomo.travaglini@arm.com _status = Active; 8213481Sgiacomo.travaglini@arm.com _nextStatus = Inactive; 8313481Sgiacomo.travaglini@arm.com string policy = params->smtCommitPolicy; 8413481Sgiacomo.travaglini@arm.com 8513481Sgiacomo.travaglini@arm.com //Convert string to lowercase 8613481Sgiacomo.travaglini@arm.com std::transform(policy.begin(), policy.end(), policy.begin(), 8713481Sgiacomo.travaglini@arm.com (int(*)(int)) tolower); 8813481Sgiacomo.travaglini@arm.com 8913481Sgiacomo.travaglini@arm.com //Assign commit policy 9013481Sgiacomo.travaglini@arm.com if (policy == "aggressive"){ 9113481Sgiacomo.travaglini@arm.com commitPolicy = Aggressive; 9213481Sgiacomo.travaglini@arm.com 9313481Sgiacomo.travaglini@arm.com DPRINTF(Commit,"Commit Policy set to Aggressive."); 9413481Sgiacomo.travaglini@arm.com } else if (policy == "roundrobin"){ 9513481Sgiacomo.travaglini@arm.com commitPolicy = RoundRobin; 9613481Sgiacomo.travaglini@arm.com 9713481Sgiacomo.travaglini@arm.com //Set-Up Priority List 9813481Sgiacomo.travaglini@arm.com for (int tid=0; tid < numThreads; tid++) { 9913481Sgiacomo.travaglini@arm.com priority_list.push_back(tid); 10013481Sgiacomo.travaglini@arm.com } 10113481Sgiacomo.travaglini@arm.com 10213481Sgiacomo.travaglini@arm.com DPRINTF(Commit,"Commit Policy set to Round Robin."); 10313481Sgiacomo.travaglini@arm.com } else if (policy == "oldestready"){ 10413481Sgiacomo.travaglini@arm.com commitPolicy = OldestReady; 10513481Sgiacomo.travaglini@arm.com 10613481Sgiacomo.travaglini@arm.com DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 10713481Sgiacomo.travaglini@arm.com } else { 10813481Sgiacomo.travaglini@arm.com assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 10913481Sgiacomo.travaglini@arm.com "RoundRobin,OldestReady}"); 11013481Sgiacomo.travaglini@arm.com } 11113481Sgiacomo.travaglini@arm.com 11213481Sgiacomo.travaglini@arm.com for (int i=0; i < numThreads; i++) { 11313481Sgiacomo.travaglini@arm.com commitStatus[i] = Idle; 11413481Sgiacomo.travaglini@arm.com changedROBNumEntries[i] = false; 11513481Sgiacomo.travaglini@arm.com trapSquash[i] = false; 11613481Sgiacomo.travaglini@arm.com xcSquash[i] = false; 11713481Sgiacomo.travaglini@arm.com } 11813481Sgiacomo.travaglini@arm.com 11913481Sgiacomo.travaglini@arm.com fetchFaultTick = 0; 12013481Sgiacomo.travaglini@arm.com fetchTrapWait = 0; 12113481Sgiacomo.travaglini@arm.com} 12213481Sgiacomo.travaglini@arm.com 12313481Sgiacomo.travaglini@arm.comtemplate <class Impl> 12413481Sgiacomo.travaglini@arm.comstd::string 12513481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::name() const 12613481Sgiacomo.travaglini@arm.com{ 12713481Sgiacomo.travaglini@arm.com return cpu->name() + ".commit"; 12813481Sgiacomo.travaglini@arm.com} 12913481Sgiacomo.travaglini@arm.com 13013481Sgiacomo.travaglini@arm.comtemplate <class Impl> 13113481Sgiacomo.travaglini@arm.comvoid 13213481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::regStats() 13313481Sgiacomo.travaglini@arm.com{ 13413481Sgiacomo.travaglini@arm.com using namespace Stats; 13513481Sgiacomo.travaglini@arm.com commitCommittedInsts 13613481Sgiacomo.travaglini@arm.com .name(name() + ".commitCommittedInsts") 13713481Sgiacomo.travaglini@arm.com .desc("The number of committed instructions") 13813481Sgiacomo.travaglini@arm.com .prereq(commitCommittedInsts); 13913481Sgiacomo.travaglini@arm.com commitSquashedInsts 14013481Sgiacomo.travaglini@arm.com .name(name() + ".commitSquashedInsts") 14113481Sgiacomo.travaglini@arm.com .desc("The number of squashed insts skipped by commit") 14213481Sgiacomo.travaglini@arm.com .prereq(commitSquashedInsts); 14313481Sgiacomo.travaglini@arm.com commitSquashEvents 14413481Sgiacomo.travaglini@arm.com .name(name() + ".commitSquashEvents") 14513481Sgiacomo.travaglini@arm.com .desc("The number of times commit is told to squash") 14613481Sgiacomo.travaglini@arm.com .prereq(commitSquashEvents); 14713481Sgiacomo.travaglini@arm.com commitNonSpecStalls 14813481Sgiacomo.travaglini@arm.com .name(name() + ".commitNonSpecStalls") 14913481Sgiacomo.travaglini@arm.com .desc("The number of times commit has been forced to stall to " 15013481Sgiacomo.travaglini@arm.com "communicate backwards") 15113481Sgiacomo.travaglini@arm.com .prereq(commitNonSpecStalls); 15213481Sgiacomo.travaglini@arm.com branchMispredicts 15313481Sgiacomo.travaglini@arm.com .name(name() + ".branchMispredicts") 15413481Sgiacomo.travaglini@arm.com .desc("The number of times a branch was mispredicted") 15513481Sgiacomo.travaglini@arm.com .prereq(branchMispredicts); 15613481Sgiacomo.travaglini@arm.com numCommittedDist 15713481Sgiacomo.travaglini@arm.com .init(0,commitWidth,1) 15813481Sgiacomo.travaglini@arm.com .name(name() + ".COM:committed_per_cycle") 15913481Sgiacomo.travaglini@arm.com .desc("Number of insts commited each cycle") 16013481Sgiacomo.travaglini@arm.com .flags(Stats::pdf) 16113481Sgiacomo.travaglini@arm.com ; 16213481Sgiacomo.travaglini@arm.com 16313481Sgiacomo.travaglini@arm.com statComInst 16413481Sgiacomo.travaglini@arm.com .init(cpu->number_of_threads) 16513481Sgiacomo.travaglini@arm.com .name(name() + ".COM:count") 16613481Sgiacomo.travaglini@arm.com .desc("Number of instructions committed") 16713481Sgiacomo.travaglini@arm.com .flags(total) 16813481Sgiacomo.travaglini@arm.com ; 16913481Sgiacomo.travaglini@arm.com 17013481Sgiacomo.travaglini@arm.com statComSwp 17113481Sgiacomo.travaglini@arm.com .init(cpu->number_of_threads) 17213481Sgiacomo.travaglini@arm.com .name(name() + ".COM:swp_count") 17313481Sgiacomo.travaglini@arm.com .desc("Number of s/w prefetches committed") 17413481Sgiacomo.travaglini@arm.com .flags(total) 17513481Sgiacomo.travaglini@arm.com ; 17613481Sgiacomo.travaglini@arm.com 17713481Sgiacomo.travaglini@arm.com statComRefs 17813481Sgiacomo.travaglini@arm.com .init(cpu->number_of_threads) 17913481Sgiacomo.travaglini@arm.com .name(name() + ".COM:refs") 18013481Sgiacomo.travaglini@arm.com .desc("Number of memory references committed") 18113481Sgiacomo.travaglini@arm.com .flags(total) 18213481Sgiacomo.travaglini@arm.com ; 18313481Sgiacomo.travaglini@arm.com 18413481Sgiacomo.travaglini@arm.com statComLoads 18513481Sgiacomo.travaglini@arm.com .init(cpu->number_of_threads) 18613481Sgiacomo.travaglini@arm.com .name(name() + ".COM:loads") 18713481Sgiacomo.travaglini@arm.com .desc("Number of loads committed") 18813481Sgiacomo.travaglini@arm.com .flags(total) 18913481Sgiacomo.travaglini@arm.com ; 19013481Sgiacomo.travaglini@arm.com 19113481Sgiacomo.travaglini@arm.com statComMembars 19213481Sgiacomo.travaglini@arm.com .init(cpu->number_of_threads) 19313481Sgiacomo.travaglini@arm.com .name(name() + ".COM:membars") 19413481Sgiacomo.travaglini@arm.com .desc("Number of memory barriers committed") 19513481Sgiacomo.travaglini@arm.com .flags(total) 19613481Sgiacomo.travaglini@arm.com ; 19713481Sgiacomo.travaglini@arm.com 19813481Sgiacomo.travaglini@arm.com statComBranches 19913481Sgiacomo.travaglini@arm.com .init(cpu->number_of_threads) 20013481Sgiacomo.travaglini@arm.com .name(name() + ".COM:branches") 20113481Sgiacomo.travaglini@arm.com .desc("Number of branches committed") 20213481Sgiacomo.travaglini@arm.com .flags(total) 20313481Sgiacomo.travaglini@arm.com ; 20413481Sgiacomo.travaglini@arm.com 20513481Sgiacomo.travaglini@arm.com // 20613481Sgiacomo.travaglini@arm.com // Commit-Eligible instructions... 20713481Sgiacomo.travaglini@arm.com // 20813481Sgiacomo.travaglini@arm.com // -> The number of instructions eligible to commit in those 20913481Sgiacomo.travaglini@arm.com // cycles where we reached our commit BW limit (less the number 21013481Sgiacomo.travaglini@arm.com // actually committed) 21113481Sgiacomo.travaglini@arm.com // 21213481Sgiacomo.travaglini@arm.com // -> The average value is computed over ALL CYCLES... not just 21313481Sgiacomo.travaglini@arm.com // the BW limited cycles 21413481Sgiacomo.travaglini@arm.com // 21513481Sgiacomo.travaglini@arm.com // -> The standard deviation is computed only over cycles where 21613481Sgiacomo.travaglini@arm.com // we reached the BW limit 21713481Sgiacomo.travaglini@arm.com // 21813481Sgiacomo.travaglini@arm.com commitEligible 21913481Sgiacomo.travaglini@arm.com .init(cpu->number_of_threads) 22013481Sgiacomo.travaglini@arm.com .name(name() + ".COM:bw_limited") 22113481Sgiacomo.travaglini@arm.com .desc("number of insts not committed due to BW limits") 22213481Sgiacomo.travaglini@arm.com .flags(total) 22313481Sgiacomo.travaglini@arm.com ; 22413481Sgiacomo.travaglini@arm.com 22513481Sgiacomo.travaglini@arm.com commitEligibleSamples 22613481Sgiacomo.travaglini@arm.com .name(name() + ".COM:bw_lim_events") 22713481Sgiacomo.travaglini@arm.com .desc("number cycles where commit BW limit reached") 22813481Sgiacomo.travaglini@arm.com ; 22913481Sgiacomo.travaglini@arm.com} 23013481Sgiacomo.travaglini@arm.com 23113481Sgiacomo.travaglini@arm.comtemplate <class Impl> 23213481Sgiacomo.travaglini@arm.comvoid 23313481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr) 23413481Sgiacomo.travaglini@arm.com{ 23513481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 23613481Sgiacomo.travaglini@arm.com cpu = cpu_ptr; 23713481Sgiacomo.travaglini@arm.com 23813481Sgiacomo.travaglini@arm.com // Commit must broadcast the number of free entries it has at the start of 23913481Sgiacomo.travaglini@arm.com // the simulation, so it starts as active. 24013481Sgiacomo.travaglini@arm.com cpu->activateStage(FullCPU::CommitIdx); 24113481Sgiacomo.travaglini@arm.com 24213481Sgiacomo.travaglini@arm.com trapLatency = cpu->cycles(trapLatency); 24313481Sgiacomo.travaglini@arm.com fetchTrapLatency = cpu->cycles(fetchTrapLatency); 24413481Sgiacomo.travaglini@arm.com} 24513481Sgiacomo.travaglini@arm.com 24613481Sgiacomo.travaglini@arm.comtemplate <class Impl> 24713481Sgiacomo.travaglini@arm.comvoid 24813481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 24913481Sgiacomo.travaglini@arm.com{ 25013481Sgiacomo.travaglini@arm.com thread = threads; 25113481Sgiacomo.travaglini@arm.com} 25213481Sgiacomo.travaglini@arm.com 25313481Sgiacomo.travaglini@arm.comtemplate <class Impl> 25413481Sgiacomo.travaglini@arm.comvoid 25513481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 25613481Sgiacomo.travaglini@arm.com{ 25713481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 25813481Sgiacomo.travaglini@arm.com timeBuffer = tb_ptr; 25913481Sgiacomo.travaglini@arm.com 26013481Sgiacomo.travaglini@arm.com // Setup wire to send information back to IEW. 26113481Sgiacomo.travaglini@arm.com toIEW = timeBuffer->getWire(0); 26213481Sgiacomo.travaglini@arm.com 26313481Sgiacomo.travaglini@arm.com // Setup wire to read data from IEW (for the ROB). 26413481Sgiacomo.travaglini@arm.com robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 26513481Sgiacomo.travaglini@arm.com} 26613481Sgiacomo.travaglini@arm.com 26713481Sgiacomo.travaglini@arm.comtemplate <class Impl> 26813481Sgiacomo.travaglini@arm.comvoid 26913481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 27013481Sgiacomo.travaglini@arm.com{ 27113481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 27213481Sgiacomo.travaglini@arm.com fetchQueue = fq_ptr; 27313481Sgiacomo.travaglini@arm.com 27413481Sgiacomo.travaglini@arm.com // Setup wire to get instructions from rename (for the ROB). 27513481Sgiacomo.travaglini@arm.com fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 27613481Sgiacomo.travaglini@arm.com} 27713481Sgiacomo.travaglini@arm.com 27813481Sgiacomo.travaglini@arm.comtemplate <class Impl> 27913481Sgiacomo.travaglini@arm.comvoid 28013481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 28113481Sgiacomo.travaglini@arm.com{ 28213481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 28313481Sgiacomo.travaglini@arm.com renameQueue = rq_ptr; 28413481Sgiacomo.travaglini@arm.com 28513481Sgiacomo.travaglini@arm.com // Setup wire to get instructions from rename (for the ROB). 28613481Sgiacomo.travaglini@arm.com fromRename = renameQueue->getWire(-renameToROBDelay); 28713481Sgiacomo.travaglini@arm.com} 28813481Sgiacomo.travaglini@arm.com 28913481Sgiacomo.travaglini@arm.comtemplate <class Impl> 29013481Sgiacomo.travaglini@arm.comvoid 29113481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 29213481Sgiacomo.travaglini@arm.com{ 29313481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 29413481Sgiacomo.travaglini@arm.com iewQueue = iq_ptr; 29513481Sgiacomo.travaglini@arm.com 29613481Sgiacomo.travaglini@arm.com // Setup wire to get instructions from IEW. 29713481Sgiacomo.travaglini@arm.com fromIEW = iewQueue->getWire(-iewToCommitDelay); 29813481Sgiacomo.travaglini@arm.com} 29913481Sgiacomo.travaglini@arm.com 30013481Sgiacomo.travaglini@arm.comtemplate <class Impl> 30113481Sgiacomo.travaglini@arm.comvoid 30213481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 30313481Sgiacomo.travaglini@arm.com{ 30413481Sgiacomo.travaglini@arm.com fetchStage = fetch_stage; 30513481Sgiacomo.travaglini@arm.com} 30613481Sgiacomo.travaglini@arm.com 30713481Sgiacomo.travaglini@arm.comtemplate <class Impl> 30813481Sgiacomo.travaglini@arm.comvoid 30913481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 31013481Sgiacomo.travaglini@arm.com{ 31113481Sgiacomo.travaglini@arm.com iewStage = iew_stage; 31213481Sgiacomo.travaglini@arm.com} 31313481Sgiacomo.travaglini@arm.com 31413481Sgiacomo.travaglini@arm.comtemplate<class Impl> 31513481Sgiacomo.travaglini@arm.comvoid 31613481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 31713481Sgiacomo.travaglini@arm.com{ 31813481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 31913481Sgiacomo.travaglini@arm.com activeThreads = at_ptr; 32013481Sgiacomo.travaglini@arm.com} 32113481Sgiacomo.travaglini@arm.com 32213481Sgiacomo.travaglini@arm.comtemplate <class Impl> 32313481Sgiacomo.travaglini@arm.comvoid 32413481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 32513481Sgiacomo.travaglini@arm.com{ 32613481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Setting rename map pointers.\n"); 32713481Sgiacomo.travaglini@arm.com 32813481Sgiacomo.travaglini@arm.com for (int i=0; i < numThreads; i++) { 32913481Sgiacomo.travaglini@arm.com renameMap[i] = &rm_ptr[i]; 33013481Sgiacomo.travaglini@arm.com } 33113481Sgiacomo.travaglini@arm.com} 33213481Sgiacomo.travaglini@arm.com 33313481Sgiacomo.travaglini@arm.comtemplate <class Impl> 33413481Sgiacomo.travaglini@arm.comvoid 33513481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setROB(ROB *rob_ptr) 33613481Sgiacomo.travaglini@arm.com{ 33713481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 33813481Sgiacomo.travaglini@arm.com rob = rob_ptr; 33913481Sgiacomo.travaglini@arm.com} 34013481Sgiacomo.travaglini@arm.com 34113481Sgiacomo.travaglini@arm.comtemplate <class Impl> 34213481Sgiacomo.travaglini@arm.comvoid 34313481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::initStage() 34413481Sgiacomo.travaglini@arm.com{ 34513481Sgiacomo.travaglini@arm.com rob->setActiveThreads(activeThreads); 34613481Sgiacomo.travaglini@arm.com rob->resetEntries(); 34713481Sgiacomo.travaglini@arm.com 34813481Sgiacomo.travaglini@arm.com // Broadcast the number of free entries. 34913481Sgiacomo.travaglini@arm.com for (int i=0; i < numThreads; i++) { 35013481Sgiacomo.travaglini@arm.com toIEW->commitInfo[i].usedROB = true; 35113481Sgiacomo.travaglini@arm.com toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 35213481Sgiacomo.travaglini@arm.com } 35313481Sgiacomo.travaglini@arm.com 35413481Sgiacomo.travaglini@arm.com cpu->activityThisCycle(); 35513481Sgiacomo.travaglini@arm.com} 35613481Sgiacomo.travaglini@arm.com 35713481Sgiacomo.travaglini@arm.comtemplate <class Impl> 35813481Sgiacomo.travaglini@arm.comvoid 35913481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::switchOut() 36013481Sgiacomo.travaglini@arm.com{ 36113481Sgiacomo.travaglini@arm.com switchPending = true; 36213481Sgiacomo.travaglini@arm.com} 36313481Sgiacomo.travaglini@arm.com 36413481Sgiacomo.travaglini@arm.comtemplate <class Impl> 36513481Sgiacomo.travaglini@arm.comvoid 36613481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::doSwitchOut() 36713481Sgiacomo.travaglini@arm.com{ 36813481Sgiacomo.travaglini@arm.com switchedOut = true; 36913481Sgiacomo.travaglini@arm.com switchPending = false; 37013481Sgiacomo.travaglini@arm.com rob->switchOut(); 37113481Sgiacomo.travaglini@arm.com} 37213481Sgiacomo.travaglini@arm.com 37313481Sgiacomo.travaglini@arm.comtemplate <class Impl> 37413481Sgiacomo.travaglini@arm.comvoid 37513481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::takeOverFrom() 37613481Sgiacomo.travaglini@arm.com{ 37713481Sgiacomo.travaglini@arm.com switchedOut = false; 37813481Sgiacomo.travaglini@arm.com _status = Active; 37913481Sgiacomo.travaglini@arm.com _nextStatus = Inactive; 38013481Sgiacomo.travaglini@arm.com for (int i=0; i < numThreads; i++) { 38113481Sgiacomo.travaglini@arm.com commitStatus[i] = Idle; 38213481Sgiacomo.travaglini@arm.com changedROBNumEntries[i] = false; 38313481Sgiacomo.travaglini@arm.com trapSquash[i] = false; 38413481Sgiacomo.travaglini@arm.com xcSquash[i] = false; 38513481Sgiacomo.travaglini@arm.com } 38613481Sgiacomo.travaglini@arm.com squashCounter = 0; 38713481Sgiacomo.travaglini@arm.com rob->takeOverFrom(); 38813481Sgiacomo.travaglini@arm.com} 38913481Sgiacomo.travaglini@arm.com 39013481Sgiacomo.travaglini@arm.comtemplate <class Impl> 39113481Sgiacomo.travaglini@arm.comvoid 39213481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::updateStatus() 39313481Sgiacomo.travaglini@arm.com{ 39413481Sgiacomo.travaglini@arm.com // reset ROB changed variable 39513481Sgiacomo.travaglini@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 39613481Sgiacomo.travaglini@arm.com while (threads != (*activeThreads).end()) { 39713481Sgiacomo.travaglini@arm.com unsigned tid = *threads++; 39813481Sgiacomo.travaglini@arm.com changedROBNumEntries[tid] = false; 39913481Sgiacomo.travaglini@arm.com 40013481Sgiacomo.travaglini@arm.com // Also check if any of the threads has a trap pending 40113481Sgiacomo.travaglini@arm.com if (commitStatus[tid] == TrapPending || 40213481Sgiacomo.travaglini@arm.com commitStatus[tid] == FetchTrapPending) { 40313481Sgiacomo.travaglini@arm.com _nextStatus = Active; 40413481Sgiacomo.travaglini@arm.com } 40513481Sgiacomo.travaglini@arm.com } 40613481Sgiacomo.travaglini@arm.com 40713481Sgiacomo.travaglini@arm.com if (_nextStatus == Inactive && _status == Active) { 40813481Sgiacomo.travaglini@arm.com DPRINTF(Activity, "Deactivating stage.\n"); 40913481Sgiacomo.travaglini@arm.com cpu->deactivateStage(FullCPU::CommitIdx); 41013481Sgiacomo.travaglini@arm.com } else if (_nextStatus == Active && _status == Inactive) { 41113481Sgiacomo.travaglini@arm.com DPRINTF(Activity, "Activating stage.\n"); 41213481Sgiacomo.travaglini@arm.com cpu->activateStage(FullCPU::CommitIdx); 41313481Sgiacomo.travaglini@arm.com } 41413481Sgiacomo.travaglini@arm.com 41513481Sgiacomo.travaglini@arm.com _status = _nextStatus; 41613481Sgiacomo.travaglini@arm.com} 41713481Sgiacomo.travaglini@arm.com 41813481Sgiacomo.travaglini@arm.comtemplate <class Impl> 41913481Sgiacomo.travaglini@arm.comvoid 42013481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::setNextStatus() 42113481Sgiacomo.travaglini@arm.com{ 42213481Sgiacomo.travaglini@arm.com int squashes = 0; 42313481Sgiacomo.travaglini@arm.com 42413481Sgiacomo.travaglini@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 42513481Sgiacomo.travaglini@arm.com 42613481Sgiacomo.travaglini@arm.com while (threads != (*activeThreads).end()) { 42713481Sgiacomo.travaglini@arm.com unsigned tid = *threads++; 42813481Sgiacomo.travaglini@arm.com 42913481Sgiacomo.travaglini@arm.com if (commitStatus[tid] == ROBSquashing) { 43013481Sgiacomo.travaglini@arm.com squashes++; 43113481Sgiacomo.travaglini@arm.com } 43213481Sgiacomo.travaglini@arm.com } 43313481Sgiacomo.travaglini@arm.com 43413481Sgiacomo.travaglini@arm.com assert(squashes == squashCounter); 43513481Sgiacomo.travaglini@arm.com 43613481Sgiacomo.travaglini@arm.com // If commit is currently squashing, then it will have activity for the 43713481Sgiacomo.travaglini@arm.com // next cycle. Set its next status as active. 43813481Sgiacomo.travaglini@arm.com if (squashCounter) { 43913481Sgiacomo.travaglini@arm.com _nextStatus = Active; 44013481Sgiacomo.travaglini@arm.com } 44113481Sgiacomo.travaglini@arm.com} 44213481Sgiacomo.travaglini@arm.com 44313481Sgiacomo.travaglini@arm.comtemplate <class Impl> 44413481Sgiacomo.travaglini@arm.combool 44513481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::changedROBEntries() 44613481Sgiacomo.travaglini@arm.com{ 44713481Sgiacomo.travaglini@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 44813481Sgiacomo.travaglini@arm.com 44913481Sgiacomo.travaglini@arm.com while (threads != (*activeThreads).end()) { 45013481Sgiacomo.travaglini@arm.com unsigned tid = *threads++; 45113481Sgiacomo.travaglini@arm.com 45213481Sgiacomo.travaglini@arm.com if (changedROBNumEntries[tid]) { 45313481Sgiacomo.travaglini@arm.com return true; 45413481Sgiacomo.travaglini@arm.com } 45513481Sgiacomo.travaglini@arm.com } 45613481Sgiacomo.travaglini@arm.com 45713481Sgiacomo.travaglini@arm.com return false; 45813481Sgiacomo.travaglini@arm.com} 45913481Sgiacomo.travaglini@arm.com 46013481Sgiacomo.travaglini@arm.comtemplate <class Impl> 46113481Sgiacomo.travaglini@arm.comunsigned 46213481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 46313481Sgiacomo.travaglini@arm.com{ 46413481Sgiacomo.travaglini@arm.com return rob->numFreeEntries(tid); 46513481Sgiacomo.travaglini@arm.com} 46613481Sgiacomo.travaglini@arm.com 46713481Sgiacomo.travaglini@arm.comtemplate <class Impl> 46813481Sgiacomo.travaglini@arm.comvoid 46913481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::generateTrapEvent(unsigned tid) 47013481Sgiacomo.travaglini@arm.com{ 47113481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 47213481Sgiacomo.travaglini@arm.com 47313481Sgiacomo.travaglini@arm.com TrapEvent *trap = new TrapEvent(this, tid); 47413481Sgiacomo.travaglini@arm.com 47513481Sgiacomo.travaglini@arm.com trap->schedule(curTick + trapLatency); 47613481Sgiacomo.travaglini@arm.com 47713481Sgiacomo.travaglini@arm.com thread[tid]->trapPending = true; 47813481Sgiacomo.travaglini@arm.com} 47913481Sgiacomo.travaglini@arm.com 48013481Sgiacomo.travaglini@arm.comtemplate <class Impl> 48113481Sgiacomo.travaglini@arm.comvoid 48213481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::generateXCEvent(unsigned tid) 48313481Sgiacomo.travaglini@arm.com{ 48413481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid); 48513481Sgiacomo.travaglini@arm.com 48613481Sgiacomo.travaglini@arm.com xcSquash[tid] = true; 48713481Sgiacomo.travaglini@arm.com} 48813481Sgiacomo.travaglini@arm.com 48913481Sgiacomo.travaglini@arm.comtemplate <class Impl> 49013481Sgiacomo.travaglini@arm.comvoid 49113481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::squashAll(unsigned tid) 49213481Sgiacomo.travaglini@arm.com{ 49313481Sgiacomo.travaglini@arm.com // If we want to include the squashing instruction in the squash, 49413481Sgiacomo.travaglini@arm.com // then use one older sequence number. 49513481Sgiacomo.travaglini@arm.com // Hopefully this doesn't mess things up. Basically I want to squash 49613481Sgiacomo.travaglini@arm.com // all instructions of this thread. 49713481Sgiacomo.travaglini@arm.com InstSeqNum squashed_inst = rob->isEmpty() ? 49813481Sgiacomo.travaglini@arm.com 0 : rob->readHeadInst(tid)->seqNum - 1;; 49913481Sgiacomo.travaglini@arm.com 50013481Sgiacomo.travaglini@arm.com // All younger instructions will be squashed. Set the sequence 50113481Sgiacomo.travaglini@arm.com // number as the youngest instruction in the ROB (0 in this case. 50213481Sgiacomo.travaglini@arm.com // Hopefully nothing breaks.) 50313481Sgiacomo.travaglini@arm.com youngestSeqNum[tid] = 0; 50413481Sgiacomo.travaglini@arm.com 50513481Sgiacomo.travaglini@arm.com rob->squash(squashed_inst, tid); 50613481Sgiacomo.travaglini@arm.com changedROBNumEntries[tid] = true; 50713481Sgiacomo.travaglini@arm.com 50813481Sgiacomo.travaglini@arm.com // Send back the sequence number of the squashed instruction. 50913481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 51013481Sgiacomo.travaglini@arm.com 51113481Sgiacomo.travaglini@arm.com // Send back the squash signal to tell stages that they should 51213481Sgiacomo.travaglini@arm.com // squash. 51313481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].squash = true; 51413481Sgiacomo.travaglini@arm.com 51513481Sgiacomo.travaglini@arm.com // Send back the rob squashing signal so other stages know that 51613481Sgiacomo.travaglini@arm.com // the ROB is in the process of squashing. 51713481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].robSquashing = true; 51813481Sgiacomo.travaglini@arm.com 51913481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].branchMispredict = false; 52013481Sgiacomo.travaglini@arm.com 52113481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].nextPC = PC[tid]; 52213481Sgiacomo.travaglini@arm.com} 52313481Sgiacomo.travaglini@arm.com 52413481Sgiacomo.travaglini@arm.comtemplate <class Impl> 52513481Sgiacomo.travaglini@arm.comvoid 52613481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::squashFromTrap(unsigned tid) 52713481Sgiacomo.travaglini@arm.com{ 52813481Sgiacomo.travaglini@arm.com squashAll(tid); 52913481Sgiacomo.travaglini@arm.com 53013481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 53113481Sgiacomo.travaglini@arm.com 53213481Sgiacomo.travaglini@arm.com thread[tid]->trapPending = false; 53313481Sgiacomo.travaglini@arm.com thread[tid]->inSyscall = false; 53413481Sgiacomo.travaglini@arm.com 53513481Sgiacomo.travaglini@arm.com trapSquash[tid] = false; 53613481Sgiacomo.travaglini@arm.com 53713481Sgiacomo.travaglini@arm.com commitStatus[tid] = ROBSquashing; 53813481Sgiacomo.travaglini@arm.com cpu->activityThisCycle(); 53913481Sgiacomo.travaglini@arm.com 54013481Sgiacomo.travaglini@arm.com ++squashCounter; 54113481Sgiacomo.travaglini@arm.com} 54213481Sgiacomo.travaglini@arm.com 54313481Sgiacomo.travaglini@arm.comtemplate <class Impl> 54413481Sgiacomo.travaglini@arm.comvoid 54513481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::squashFromXC(unsigned tid) 54613481Sgiacomo.travaglini@arm.com{ 54713481Sgiacomo.travaglini@arm.com squashAll(tid); 54813481Sgiacomo.travaglini@arm.com 54913481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]); 55013481Sgiacomo.travaglini@arm.com 55113481Sgiacomo.travaglini@arm.com thread[tid]->inSyscall = false; 55213481Sgiacomo.travaglini@arm.com assert(!thread[tid]->trapPending); 55313481Sgiacomo.travaglini@arm.com 55413481Sgiacomo.travaglini@arm.com commitStatus[tid] = ROBSquashing; 55513481Sgiacomo.travaglini@arm.com cpu->activityThisCycle(); 55613481Sgiacomo.travaglini@arm.com 55713481Sgiacomo.travaglini@arm.com xcSquash[tid] = false; 55813481Sgiacomo.travaglini@arm.com 55913481Sgiacomo.travaglini@arm.com ++squashCounter; 56013481Sgiacomo.travaglini@arm.com} 56113481Sgiacomo.travaglini@arm.com 56213481Sgiacomo.travaglini@arm.comtemplate <class Impl> 56313481Sgiacomo.travaglini@arm.comvoid 56413481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::tick() 56513481Sgiacomo.travaglini@arm.com{ 56613481Sgiacomo.travaglini@arm.com wroteToTimeBuffer = false; 56713481Sgiacomo.travaglini@arm.com _nextStatus = Inactive; 56813481Sgiacomo.travaglini@arm.com 56913481Sgiacomo.travaglini@arm.com if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 57013481Sgiacomo.travaglini@arm.com cpu->signalSwitched(); 57113481Sgiacomo.travaglini@arm.com return; 57213481Sgiacomo.travaglini@arm.com } 57313481Sgiacomo.travaglini@arm.com 57413481Sgiacomo.travaglini@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 57513481Sgiacomo.travaglini@arm.com 57613481Sgiacomo.travaglini@arm.com // Check if any of the threads are done squashing. Change the 57713481Sgiacomo.travaglini@arm.com // status if they are done. 57813481Sgiacomo.travaglini@arm.com while (threads != (*activeThreads).end()) { 57913481Sgiacomo.travaglini@arm.com unsigned tid = *threads++; 58013481Sgiacomo.travaglini@arm.com 58113481Sgiacomo.travaglini@arm.com if (commitStatus[tid] == ROBSquashing) { 58213481Sgiacomo.travaglini@arm.com 58313481Sgiacomo.travaglini@arm.com if (rob->isDoneSquashing(tid)) { 58413481Sgiacomo.travaglini@arm.com commitStatus[tid] = Running; 58513481Sgiacomo.travaglini@arm.com --squashCounter; 58613481Sgiacomo.travaglini@arm.com } else { 58713481Sgiacomo.travaglini@arm.com DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 58813481Sgiacomo.travaglini@arm.com "insts this cycle.\n", tid); 58913481Sgiacomo.travaglini@arm.com } 59013481Sgiacomo.travaglini@arm.com } 59113481Sgiacomo.travaglini@arm.com } 59213481Sgiacomo.travaglini@arm.com 59313481Sgiacomo.travaglini@arm.com commit(); 59413481Sgiacomo.travaglini@arm.com 59513481Sgiacomo.travaglini@arm.com markCompletedInsts(); 59613481Sgiacomo.travaglini@arm.com 59713481Sgiacomo.travaglini@arm.com threads = (*activeThreads).begin(); 59813481Sgiacomo.travaglini@arm.com 59913481Sgiacomo.travaglini@arm.com while (threads != (*activeThreads).end()) { 60013481Sgiacomo.travaglini@arm.com unsigned tid = *threads++; 60113481Sgiacomo.travaglini@arm.com 60213481Sgiacomo.travaglini@arm.com if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 60313481Sgiacomo.travaglini@arm.com // The ROB has more instructions it can commit. Its next status 60413481Sgiacomo.travaglini@arm.com // will be active. 60513481Sgiacomo.travaglini@arm.com _nextStatus = Active; 60613481Sgiacomo.travaglini@arm.com 60713481Sgiacomo.travaglini@arm.com DynInstPtr inst = rob->readHeadInst(tid); 60813481Sgiacomo.travaglini@arm.com 60913481Sgiacomo.travaglini@arm.com DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 61013481Sgiacomo.travaglini@arm.com " ROB and ready to commit\n", 61113481Sgiacomo.travaglini@arm.com tid, inst->seqNum, inst->readPC()); 61213481Sgiacomo.travaglini@arm.com 61313481Sgiacomo.travaglini@arm.com } else if (!rob->isEmpty(tid)) { 61413481Sgiacomo.travaglini@arm.com DynInstPtr inst = rob->readHeadInst(tid); 61513481Sgiacomo.travaglini@arm.com 61613481Sgiacomo.travaglini@arm.com DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 61713481Sgiacomo.travaglini@arm.com "%#x is head of ROB and not ready\n", 61813481Sgiacomo.travaglini@arm.com tid, inst->seqNum, inst->readPC()); 61913481Sgiacomo.travaglini@arm.com } 62013481Sgiacomo.travaglini@arm.com 62113481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 62213481Sgiacomo.travaglini@arm.com tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 62313481Sgiacomo.travaglini@arm.com } 62413481Sgiacomo.travaglini@arm.com 62513481Sgiacomo.travaglini@arm.com 62613481Sgiacomo.travaglini@arm.com if (wroteToTimeBuffer) { 62713481Sgiacomo.travaglini@arm.com DPRINTF(Activity, "Activity This Cycle.\n"); 62813481Sgiacomo.travaglini@arm.com cpu->activityThisCycle(); 62913481Sgiacomo.travaglini@arm.com } 63013481Sgiacomo.travaglini@arm.com 63113481Sgiacomo.travaglini@arm.com updateStatus(); 63213481Sgiacomo.travaglini@arm.com} 63313481Sgiacomo.travaglini@arm.com 63413481Sgiacomo.travaglini@arm.comtemplate <class Impl> 63513481Sgiacomo.travaglini@arm.comvoid 63613481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::commit() 63713481Sgiacomo.travaglini@arm.com{ 63813481Sgiacomo.travaglini@arm.com 63913481Sgiacomo.travaglini@arm.com ////////////////////////////////////// 64013481Sgiacomo.travaglini@arm.com // Check for interrupts 64113481Sgiacomo.travaglini@arm.com ////////////////////////////////////// 64213481Sgiacomo.travaglini@arm.com 64313481Sgiacomo.travaglini@arm.com#if FULL_SYSTEM 64413481Sgiacomo.travaglini@arm.com // Process interrupts if interrupts are enabled, not in PAL mode, 64513481Sgiacomo.travaglini@arm.com // and no other traps or external squashes are currently pending. 64613481Sgiacomo.travaglini@arm.com // @todo: Allow other threads to handle interrupts. 64713481Sgiacomo.travaglini@arm.com if (cpu->checkInterrupts && 64813481Sgiacomo.travaglini@arm.com cpu->check_interrupts() && 64913481Sgiacomo.travaglini@arm.com !cpu->inPalMode(readPC()) && 65013481Sgiacomo.travaglini@arm.com !trapSquash[0] && 65113481Sgiacomo.travaglini@arm.com !xcSquash[0]) { 65213481Sgiacomo.travaglini@arm.com // Tell fetch that there is an interrupt pending. This will 65313481Sgiacomo.travaglini@arm.com // make fetch wait until it sees a non PAL-mode PC, at which 65413481Sgiacomo.travaglini@arm.com // point it stops fetching instructions. 65513481Sgiacomo.travaglini@arm.com toIEW->commitInfo[0].interruptPending = true; 65613481Sgiacomo.travaglini@arm.com 65713481Sgiacomo.travaglini@arm.com // Wait until the ROB is empty and all stores have drained in 65813481Sgiacomo.travaglini@arm.com // order to enter the interrupt. 65913481Sgiacomo.travaglini@arm.com if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 66013481Sgiacomo.travaglini@arm.com // Not sure which thread should be the one to interrupt. For now 66113481Sgiacomo.travaglini@arm.com // always do thread 0. 66213481Sgiacomo.travaglini@arm.com assert(!thread[0]->inSyscall); 66313481Sgiacomo.travaglini@arm.com thread[0]->inSyscall = true; 66413481Sgiacomo.travaglini@arm.com 66513481Sgiacomo.travaglini@arm.com // CPU will handle implementation of the interrupt. 66613481Sgiacomo.travaglini@arm.com cpu->processInterrupts(); 66713481Sgiacomo.travaglini@arm.com 66813481Sgiacomo.travaglini@arm.com // Now squash or record that I need to squash this cycle. 66913481Sgiacomo.travaglini@arm.com commitStatus[0] = TrapPending; 67013481Sgiacomo.travaglini@arm.com 67113481Sgiacomo.travaglini@arm.com // Exit state update mode to avoid accidental updating. 67213481Sgiacomo.travaglini@arm.com thread[0]->inSyscall = false; 67313481Sgiacomo.travaglini@arm.com 67413481Sgiacomo.travaglini@arm.com // Generate trap squash event. 67513481Sgiacomo.travaglini@arm.com generateTrapEvent(0); 67613481Sgiacomo.travaglini@arm.com 67713481Sgiacomo.travaglini@arm.com toIEW->commitInfo[0].clearInterrupt = true; 67813481Sgiacomo.travaglini@arm.com 67913481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 68013481Sgiacomo.travaglini@arm.com } else { 68113481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 68213481Sgiacomo.travaglini@arm.com } 68313481Sgiacomo.travaglini@arm.com } 68413481Sgiacomo.travaglini@arm.com#endif // FULL_SYSTEM 68513481Sgiacomo.travaglini@arm.com 68613481Sgiacomo.travaglini@arm.com //////////////////////////////////// 68713481Sgiacomo.travaglini@arm.com // Check for any possible squashes, handle them first 68813481Sgiacomo.travaglini@arm.com //////////////////////////////////// 68913481Sgiacomo.travaglini@arm.com 69013481Sgiacomo.travaglini@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 69113481Sgiacomo.travaglini@arm.com 69213481Sgiacomo.travaglini@arm.com while (threads != (*activeThreads).end()) { 69313481Sgiacomo.travaglini@arm.com unsigned tid = *threads++; 69413481Sgiacomo.travaglini@arm.com 69513481Sgiacomo.travaglini@arm.com if (fromFetch->fetchFault && commitStatus[0] != TrapPending) { 69613481Sgiacomo.travaglini@arm.com // Record the fault. Wait until it's empty in the ROB. 69713481Sgiacomo.travaglini@arm.com // Then handle the trap. Ignore it if there's already a 69813481Sgiacomo.travaglini@arm.com // trap pending as fetch will be redirected. 69913481Sgiacomo.travaglini@arm.com fetchFault = fromFetch->fetchFault; 70013481Sgiacomo.travaglini@arm.com fetchFaultTick = curTick + fetchTrapLatency; 70113481Sgiacomo.travaglini@arm.com commitStatus[0] = FetchTrapPending; 70213481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Fault from fetch recorded. Will trap if the " 70313481Sgiacomo.travaglini@arm.com "ROB empties without squashing the fault.\n"); 70413481Sgiacomo.travaglini@arm.com fetchTrapWait = 0; 70513481Sgiacomo.travaglini@arm.com } 70613481Sgiacomo.travaglini@arm.com 70713481Sgiacomo.travaglini@arm.com // Fetch may tell commit to clear the trap if it's been squashed. 70813481Sgiacomo.travaglini@arm.com if (fromFetch->clearFetchFault) { 70913481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Received clear fetch fault signal\n"); 71013481Sgiacomo.travaglini@arm.com fetchTrapWait = 0; 71113481Sgiacomo.travaglini@arm.com if (commitStatus[0] == FetchTrapPending) { 71213481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Clearing fault from fetch\n"); 71313481Sgiacomo.travaglini@arm.com commitStatus[0] = Running; 71413481Sgiacomo.travaglini@arm.com } 71513481Sgiacomo.travaglini@arm.com } 71613481Sgiacomo.travaglini@arm.com 71713481Sgiacomo.travaglini@arm.com // Not sure which one takes priority. I think if we have 71813481Sgiacomo.travaglini@arm.com // both, that's a bad sign. 71913481Sgiacomo.travaglini@arm.com if (trapSquash[tid] == true) { 72013481Sgiacomo.travaglini@arm.com assert(!xcSquash[tid]); 72113481Sgiacomo.travaglini@arm.com squashFromTrap(tid); 72213481Sgiacomo.travaglini@arm.com } else if (xcSquash[tid] == true) { 72313481Sgiacomo.travaglini@arm.com squashFromXC(tid); 72413481Sgiacomo.travaglini@arm.com } 72513481Sgiacomo.travaglini@arm.com 72613481Sgiacomo.travaglini@arm.com // Squashed sequence number must be older than youngest valid 72713481Sgiacomo.travaglini@arm.com // instruction in the ROB. This prevents squashes from younger 72813481Sgiacomo.travaglini@arm.com // instructions overriding squashes from older instructions. 72913481Sgiacomo.travaglini@arm.com if (fromIEW->squash[tid] && 73013481Sgiacomo.travaglini@arm.com commitStatus[tid] != TrapPending && 73113481Sgiacomo.travaglini@arm.com fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 73213481Sgiacomo.travaglini@arm.com 73313481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 73413481Sgiacomo.travaglini@arm.com tid, 73513481Sgiacomo.travaglini@arm.com fromIEW->mispredPC[tid], 73613481Sgiacomo.travaglini@arm.com fromIEW->squashedSeqNum[tid]); 73713481Sgiacomo.travaglini@arm.com 73813481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 73913481Sgiacomo.travaglini@arm.com tid, 74013481Sgiacomo.travaglini@arm.com fromIEW->nextPC[tid]); 74113481Sgiacomo.travaglini@arm.com 74213481Sgiacomo.travaglini@arm.com commitStatus[tid] = ROBSquashing; 74313481Sgiacomo.travaglini@arm.com 74413481Sgiacomo.travaglini@arm.com ++squashCounter; 74513481Sgiacomo.travaglini@arm.com 74613481Sgiacomo.travaglini@arm.com // If we want to include the squashing instruction in the squash, 74713481Sgiacomo.travaglini@arm.com // then use one older sequence number. 74813481Sgiacomo.travaglini@arm.com InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 74913481Sgiacomo.travaglini@arm.com 75013481Sgiacomo.travaglini@arm.com if (fromIEW->includeSquashInst[tid] == true) 75113481Sgiacomo.travaglini@arm.com squashed_inst--; 75213481Sgiacomo.travaglini@arm.com 75313481Sgiacomo.travaglini@arm.com // All younger instructions will be squashed. Set the sequence 75413481Sgiacomo.travaglini@arm.com // number as the youngest instruction in the ROB. 75513481Sgiacomo.travaglini@arm.com youngestSeqNum[tid] = squashed_inst; 75613481Sgiacomo.travaglini@arm.com 75713481Sgiacomo.travaglini@arm.com rob->squash(squashed_inst, tid); 75813481Sgiacomo.travaglini@arm.com changedROBNumEntries[tid] = true; 75913481Sgiacomo.travaglini@arm.com 76013481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 76113481Sgiacomo.travaglini@arm.com 76213481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].squash = true; 76313481Sgiacomo.travaglini@arm.com 76413481Sgiacomo.travaglini@arm.com // Send back the rob squashing signal so other stages know that 76513481Sgiacomo.travaglini@arm.com // the ROB is in the process of squashing. 76613481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].robSquashing = true; 76713481Sgiacomo.travaglini@arm.com 76813481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].branchMispredict = 76913481Sgiacomo.travaglini@arm.com fromIEW->branchMispredict[tid]; 77013481Sgiacomo.travaglini@arm.com 77113481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].branchTaken = 77213481Sgiacomo.travaglini@arm.com fromIEW->branchTaken[tid]; 77313481Sgiacomo.travaglini@arm.com 77413481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 77513481Sgiacomo.travaglini@arm.com 77613481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 77713481Sgiacomo.travaglini@arm.com 77813481Sgiacomo.travaglini@arm.com if (toIEW->commitInfo[tid].branchMispredict) { 77913481Sgiacomo.travaglini@arm.com ++branchMispredicts; 78013481Sgiacomo.travaglini@arm.com } 78113481Sgiacomo.travaglini@arm.com } 78213481Sgiacomo.travaglini@arm.com 78313481Sgiacomo.travaglini@arm.com } 78413481Sgiacomo.travaglini@arm.com 78513481Sgiacomo.travaglini@arm.com setNextStatus(); 78613481Sgiacomo.travaglini@arm.com 78713481Sgiacomo.travaglini@arm.com if (squashCounter != numThreads) { 78813481Sgiacomo.travaglini@arm.com // If we're not currently squashing, then get instructions. 78913481Sgiacomo.travaglini@arm.com getInsts(); 79013481Sgiacomo.travaglini@arm.com 79113481Sgiacomo.travaglini@arm.com // Try to commit any instructions. 79213481Sgiacomo.travaglini@arm.com commitInsts(); 79313481Sgiacomo.travaglini@arm.com } 79413481Sgiacomo.travaglini@arm.com 79513481Sgiacomo.travaglini@arm.com //Check for any activity 79613481Sgiacomo.travaglini@arm.com threads = (*activeThreads).begin(); 79713481Sgiacomo.travaglini@arm.com 79813481Sgiacomo.travaglini@arm.com while (threads != (*activeThreads).end()) { 79913481Sgiacomo.travaglini@arm.com unsigned tid = *threads++; 80013481Sgiacomo.travaglini@arm.com 80113481Sgiacomo.travaglini@arm.com if (changedROBNumEntries[tid]) { 80213481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].usedROB = true; 80313481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 80413481Sgiacomo.travaglini@arm.com 80513481Sgiacomo.travaglini@arm.com if (rob->isEmpty(tid)) { 80613481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].emptyROB = true; 80713481Sgiacomo.travaglini@arm.com } 80813481Sgiacomo.travaglini@arm.com 80913481Sgiacomo.travaglini@arm.com wroteToTimeBuffer = true; 81013481Sgiacomo.travaglini@arm.com changedROBNumEntries[tid] = false; 81113481Sgiacomo.travaglini@arm.com } 81213481Sgiacomo.travaglini@arm.com } 81313481Sgiacomo.travaglini@arm.com} 81413481Sgiacomo.travaglini@arm.com 81513481Sgiacomo.travaglini@arm.comtemplate <class Impl> 81613481Sgiacomo.travaglini@arm.comvoid 81713481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::commitInsts() 81813481Sgiacomo.travaglini@arm.com{ 81913481Sgiacomo.travaglini@arm.com //////////////////////////////////// 82013481Sgiacomo.travaglini@arm.com // Handle commit 82113481Sgiacomo.travaglini@arm.com // Note that commit will be handled prior to putting new 82213481Sgiacomo.travaglini@arm.com // instructions in the ROB so that the ROB only tries to commit 82313481Sgiacomo.travaglini@arm.com // instructions it has in this current cycle, and not instructions 82413481Sgiacomo.travaglini@arm.com // it is writing in during this cycle. Can't commit and squash 82513481Sgiacomo.travaglini@arm.com // things at the same time... 82613481Sgiacomo.travaglini@arm.com //////////////////////////////////// 82713481Sgiacomo.travaglini@arm.com 82813481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 82913481Sgiacomo.travaglini@arm.com 83013481Sgiacomo.travaglini@arm.com unsigned num_committed = 0; 83113481Sgiacomo.travaglini@arm.com 83213481Sgiacomo.travaglini@arm.com DynInstPtr head_inst; 83313481Sgiacomo.travaglini@arm.com 83413481Sgiacomo.travaglini@arm.com // Commit as many instructions as possible until the commit bandwidth 83513481Sgiacomo.travaglini@arm.com // limit is reached, or it becomes impossible to commit any more. 83613481Sgiacomo.travaglini@arm.com while (num_committed < commitWidth) { 83713481Sgiacomo.travaglini@arm.com int commit_thread = getCommittingThread(); 83813481Sgiacomo.travaglini@arm.com 83913481Sgiacomo.travaglini@arm.com if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 84013481Sgiacomo.travaglini@arm.com break; 84113481Sgiacomo.travaglini@arm.com 84213481Sgiacomo.travaglini@arm.com head_inst = rob->readHeadInst(commit_thread); 84313481Sgiacomo.travaglini@arm.com 84413481Sgiacomo.travaglini@arm.com int tid = head_inst->threadNumber; 84513481Sgiacomo.travaglini@arm.com 84613481Sgiacomo.travaglini@arm.com assert(tid == commit_thread); 84713481Sgiacomo.travaglini@arm.com 84813481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 84913481Sgiacomo.travaglini@arm.com head_inst->seqNum, tid); 85013481Sgiacomo.travaglini@arm.com 85113481Sgiacomo.travaglini@arm.com // If the head instruction is squashed, it is ready to retire 85213481Sgiacomo.travaglini@arm.com // (be removed from the ROB) at any time. 85313481Sgiacomo.travaglini@arm.com if (head_inst->isSquashed()) { 85413481Sgiacomo.travaglini@arm.com 85513481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Retiring squashed instruction from " 85613481Sgiacomo.travaglini@arm.com "ROB.\n"); 85713481Sgiacomo.travaglini@arm.com 85813481Sgiacomo.travaglini@arm.com rob->retireHead(commit_thread); 85913481Sgiacomo.travaglini@arm.com 86013481Sgiacomo.travaglini@arm.com ++commitSquashedInsts; 86113481Sgiacomo.travaglini@arm.com 86213481Sgiacomo.travaglini@arm.com // Record that the number of ROB entries has changed. 86313481Sgiacomo.travaglini@arm.com changedROBNumEntries[tid] = true; 86413481Sgiacomo.travaglini@arm.com } else { 86513481Sgiacomo.travaglini@arm.com PC[tid] = head_inst->readPC(); 86613481Sgiacomo.travaglini@arm.com nextPC[tid] = head_inst->readNextPC(); 86713481Sgiacomo.travaglini@arm.com 86813481Sgiacomo.travaglini@arm.com // Increment the total number of non-speculative instructions 86913481Sgiacomo.travaglini@arm.com // executed. 87013481Sgiacomo.travaglini@arm.com // Hack for now: it really shouldn't happen until after the 87113481Sgiacomo.travaglini@arm.com // commit is deemed to be successful, but this count is needed 87213481Sgiacomo.travaglini@arm.com // for syscalls. 87313481Sgiacomo.travaglini@arm.com thread[tid]->funcExeInst++; 87413481Sgiacomo.travaglini@arm.com 87513481Sgiacomo.travaglini@arm.com // Try to commit the head instruction. 87613481Sgiacomo.travaglini@arm.com bool commit_success = commitHead(head_inst, num_committed); 87713481Sgiacomo.travaglini@arm.com 87813481Sgiacomo.travaglini@arm.com if (commit_success) { 87913481Sgiacomo.travaglini@arm.com ++num_committed; 88013481Sgiacomo.travaglini@arm.com 88113481Sgiacomo.travaglini@arm.com changedROBNumEntries[tid] = true; 88213481Sgiacomo.travaglini@arm.com 88313481Sgiacomo.travaglini@arm.com // Set the doneSeqNum to the youngest committed instruction. 88413481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 88513481Sgiacomo.travaglini@arm.com 88613481Sgiacomo.travaglini@arm.com ++commitCommittedInsts; 88713481Sgiacomo.travaglini@arm.com 88813481Sgiacomo.travaglini@arm.com // To match the old model, don't count nops and instruction 88913481Sgiacomo.travaglini@arm.com // prefetches towards the total commit count. 89013481Sgiacomo.travaglini@arm.com if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 89113481Sgiacomo.travaglini@arm.com cpu->instDone(tid); 89213481Sgiacomo.travaglini@arm.com } 89313481Sgiacomo.travaglini@arm.com 89413481Sgiacomo.travaglini@arm.com PC[tid] = nextPC[tid]; 89513481Sgiacomo.travaglini@arm.com nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 89613481Sgiacomo.travaglini@arm.com#if FULL_SYSTEM 89713481Sgiacomo.travaglini@arm.com int count = 0; 89813481Sgiacomo.travaglini@arm.com Addr oldpc; 89913481Sgiacomo.travaglini@arm.com do { 90013481Sgiacomo.travaglini@arm.com // Debug statement. Checks to make sure we're not 90113481Sgiacomo.travaglini@arm.com // currently updating state while handling PC events. 90213481Sgiacomo.travaglini@arm.com if (count == 0) 90313481Sgiacomo.travaglini@arm.com assert(!thread[tid]->inSyscall && 90413481Sgiacomo.travaglini@arm.com !thread[tid]->trapPending); 90513481Sgiacomo.travaglini@arm.com oldpc = PC[tid]; 90613481Sgiacomo.travaglini@arm.com cpu->system->pcEventQueue.service( 90713481Sgiacomo.travaglini@arm.com thread[tid]->getXCProxy()); 90813481Sgiacomo.travaglini@arm.com count++; 90913481Sgiacomo.travaglini@arm.com } while (oldpc != PC[tid]); 91013481Sgiacomo.travaglini@arm.com if (count > 1) { 91113481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "PC skip function event, stopping commit\n"); 91213481Sgiacomo.travaglini@arm.com break; 91313481Sgiacomo.travaglini@arm.com } 91413481Sgiacomo.travaglini@arm.com#endif 91513481Sgiacomo.travaglini@arm.com } else { 91613481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 91713481Sgiacomo.travaglini@arm.com "[tid:%i] [sn:%i].\n", 91813481Sgiacomo.travaglini@arm.com head_inst->readPC(), tid ,head_inst->seqNum); 91913481Sgiacomo.travaglini@arm.com break; 92013481Sgiacomo.travaglini@arm.com } 92113481Sgiacomo.travaglini@arm.com } 92213481Sgiacomo.travaglini@arm.com } 92313481Sgiacomo.travaglini@arm.com 92413481Sgiacomo.travaglini@arm.com DPRINTF(CommitRate, "%i\n", num_committed); 92513481Sgiacomo.travaglini@arm.com numCommittedDist.sample(num_committed); 92613481Sgiacomo.travaglini@arm.com 92713481Sgiacomo.travaglini@arm.com if (num_committed == commitWidth) { 92813481Sgiacomo.travaglini@arm.com commitEligible[0]++; 92913481Sgiacomo.travaglini@arm.com } 93013481Sgiacomo.travaglini@arm.com} 93113481Sgiacomo.travaglini@arm.com 93213481Sgiacomo.travaglini@arm.comtemplate <class Impl> 93313481Sgiacomo.travaglini@arm.combool 93413481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 93513481Sgiacomo.travaglini@arm.com{ 93613481Sgiacomo.travaglini@arm.com assert(head_inst); 93713481Sgiacomo.travaglini@arm.com 93813481Sgiacomo.travaglini@arm.com int tid = head_inst->threadNumber; 93913481Sgiacomo.travaglini@arm.com 94013481Sgiacomo.travaglini@arm.com // If the instruction is not executed yet, then it will need extra 94113481Sgiacomo.travaglini@arm.com // handling. Signal backwards that it should be executed. 94213481Sgiacomo.travaglini@arm.com if (!head_inst->isExecuted()) { 94313481Sgiacomo.travaglini@arm.com // Keep this number correct. We have not yet actually executed 94413481Sgiacomo.travaglini@arm.com // and committed this instruction. 94513481Sgiacomo.travaglini@arm.com thread[tid]->funcExeInst--; 94613481Sgiacomo.travaglini@arm.com 94713481Sgiacomo.travaglini@arm.com head_inst->reachedCommit = true; 94813481Sgiacomo.travaglini@arm.com 94913481Sgiacomo.travaglini@arm.com if (head_inst->isNonSpeculative() || 95013481Sgiacomo.travaglini@arm.com head_inst->isMemBarrier() || 95113481Sgiacomo.travaglini@arm.com head_inst->isWriteBarrier()) { 95213481Sgiacomo.travaglini@arm.com 95313481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Encountered a barrier or non-speculative " 95413481Sgiacomo.travaglini@arm.com "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 95513481Sgiacomo.travaglini@arm.com head_inst->seqNum, head_inst->readPC()); 95613481Sgiacomo.travaglini@arm.com 95713481Sgiacomo.travaglini@arm.com#if !FULL_SYSTEM 95813481Sgiacomo.travaglini@arm.com // Hack to make sure syscalls/memory barriers/quiesces 95913481Sgiacomo.travaglini@arm.com // aren't executed until all stores write back their data. 96013481Sgiacomo.travaglini@arm.com // This direct communication shouldn't be used for 96113481Sgiacomo.travaglini@arm.com // anything other than this. 96213481Sgiacomo.travaglini@arm.com if (inst_num > 0 || iewStage->hasStoresToWB()) 96313481Sgiacomo.travaglini@arm.com#else 96413481Sgiacomo.travaglini@arm.com if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 96513481Sgiacomo.travaglini@arm.com head_inst->isQuiesce()) && 96613481Sgiacomo.travaglini@arm.com iewStage->hasStoresToWB()) 96713481Sgiacomo.travaglini@arm.com#endif 96813481Sgiacomo.travaglini@arm.com { 96913481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 97013481Sgiacomo.travaglini@arm.com return false; 97113481Sgiacomo.travaglini@arm.com } 97213481Sgiacomo.travaglini@arm.com 97313481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 97413481Sgiacomo.travaglini@arm.com 97513481Sgiacomo.travaglini@arm.com // Change the instruction so it won't try to commit again until 97613481Sgiacomo.travaglini@arm.com // it is executed. 97713481Sgiacomo.travaglini@arm.com head_inst->clearCanCommit(); 97813481Sgiacomo.travaglini@arm.com 97913481Sgiacomo.travaglini@arm.com ++commitNonSpecStalls; 98013481Sgiacomo.travaglini@arm.com 98113481Sgiacomo.travaglini@arm.com return false; 98213481Sgiacomo.travaglini@arm.com } else if (head_inst->isLoad()) { 98313481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 98413481Sgiacomo.travaglini@arm.com head_inst->seqNum, head_inst->readPC()); 98513481Sgiacomo.travaglini@arm.com 98613481Sgiacomo.travaglini@arm.com // Send back the non-speculative instruction's sequence 98713481Sgiacomo.travaglini@arm.com // number. Tell the lsq to re-execute the load. 98813481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 98913481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].uncached = true; 99013481Sgiacomo.travaglini@arm.com toIEW->commitInfo[tid].uncachedLoad = head_inst; 99113481Sgiacomo.travaglini@arm.com 99213481Sgiacomo.travaglini@arm.com head_inst->clearCanCommit(); 99313481Sgiacomo.travaglini@arm.com 99413481Sgiacomo.travaglini@arm.com return false; 99513481Sgiacomo.travaglini@arm.com } else { 99613481Sgiacomo.travaglini@arm.com panic("Trying to commit un-executed instruction " 99713481Sgiacomo.travaglini@arm.com "of unknown type!\n"); 99813481Sgiacomo.travaglini@arm.com } 99913481Sgiacomo.travaglini@arm.com } 100013481Sgiacomo.travaglini@arm.com 100113481Sgiacomo.travaglini@arm.com if (head_inst->isThreadSync()) { 100213481Sgiacomo.travaglini@arm.com // Not handled for now. 100313481Sgiacomo.travaglini@arm.com panic("Thread sync instructions are not handled yet.\n"); 100413481Sgiacomo.travaglini@arm.com } 100513481Sgiacomo.travaglini@arm.com 100613481Sgiacomo.travaglini@arm.com // Stores mark themselves as completed. 100713481Sgiacomo.travaglini@arm.com if (!head_inst->isStore()) { 100813481Sgiacomo.travaglini@arm.com head_inst->setCompleted(); 100913481Sgiacomo.travaglini@arm.com } 101013481Sgiacomo.travaglini@arm.com 101113481Sgiacomo.travaglini@arm.com // Use checker prior to updating anything due to traps or PC 101213481Sgiacomo.travaglini@arm.com // based events. 101313481Sgiacomo.travaglini@arm.com if (cpu->checker) { 101413481Sgiacomo.travaglini@arm.com cpu->checker->tick(head_inst); 101513481Sgiacomo.travaglini@arm.com } 101613481Sgiacomo.travaglini@arm.com 101713481Sgiacomo.travaglini@arm.com // Check if the instruction caused a fault. If so, trap. 101813481Sgiacomo.travaglini@arm.com Fault inst_fault = head_inst->getFault(); 101913481Sgiacomo.travaglini@arm.com 102013481Sgiacomo.travaglini@arm.com if (inst_fault != NoFault) { 102113481Sgiacomo.travaglini@arm.com head_inst->setCompleted(); 102213481Sgiacomo.travaglini@arm.com#if FULL_SYSTEM 102313481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 102413481Sgiacomo.travaglini@arm.com head_inst->seqNum, head_inst->readPC()); 102513481Sgiacomo.travaglini@arm.com 102613481Sgiacomo.travaglini@arm.com if (iewStage->hasStoresToWB() || inst_num > 0) { 102713481Sgiacomo.travaglini@arm.com DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 102813481Sgiacomo.travaglini@arm.com return false; 102913481Sgiacomo.travaglini@arm.com } 103013481Sgiacomo.travaglini@arm.com 103113481Sgiacomo.travaglini@arm.com if (cpu->checker && head_inst->isStore()) { 103213481Sgiacomo.travaglini@arm.com cpu->checker->tick(head_inst); 103313481Sgiacomo.travaglini@arm.com } 103413481Sgiacomo.travaglini@arm.com 103513481Sgiacomo.travaglini@arm.com assert(!thread[tid]->inSyscall); 103613481Sgiacomo.travaglini@arm.com 103713481Sgiacomo.travaglini@arm.com // Mark that we're in state update mode so that the trap's 103813481Sgiacomo.travaglini@arm.com // execution doesn't generate extra squashes. 103913481Sgiacomo.travaglini@arm.com thread[tid]->inSyscall = true; 104013481Sgiacomo.travaglini@arm.com 104113481Sgiacomo.travaglini@arm.com // DTB will sometimes need the machine instruction for when 104213481Sgiacomo.travaglini@arm.com // faults happen. So we will set it here, prior to the DTB 104313481Sgiacomo.travaglini@arm.com // possibly needing it for its fault. 104413481Sgiacomo.travaglini@arm.com thread[tid]->setInst( 104513481Sgiacomo.travaglini@arm.com static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 104613481Sgiacomo.travaglini@arm.com 104713481Sgiacomo.travaglini@arm.com // Execute the trap. Although it's slightly unrealistic in 104813481Sgiacomo.travaglini@arm.com // terms of timing (as it doesn't wait for the full timing of 104913481Sgiacomo.travaglini@arm.com // the trap event to complete before updating state), it's 105013481Sgiacomo.travaglini@arm.com // needed to update the state as soon as possible. This 105113481Sgiacomo.travaglini@arm.com // prevents external agents from changing any specific state 105213481Sgiacomo.travaglini@arm.com // that the trap need. 105313481Sgiacomo.travaglini@arm.com cpu->trap(inst_fault, tid); 105413481Sgiacomo.travaglini@arm.com 105513481Sgiacomo.travaglini@arm.com // Exit state update mode to avoid accidental updating. 105613481Sgiacomo.travaglini@arm.com thread[tid]->inSyscall = false; 105713481Sgiacomo.travaglini@arm.com 105813481Sgiacomo.travaglini@arm.com commitStatus[tid] = TrapPending; 105913481Sgiacomo.travaglini@arm.com 106013481Sgiacomo.travaglini@arm.com // Generate trap squash event. 106113481Sgiacomo.travaglini@arm.com generateTrapEvent(tid); 106213481Sgiacomo.travaglini@arm.com 106313481Sgiacomo.travaglini@arm.com return false; 106413481Sgiacomo.travaglini@arm.com#else // !FULL_SYSTEM 106513481Sgiacomo.travaglini@arm.com panic("fault (%d) detected @ PC %08p", inst_fault, 106613481Sgiacomo.travaglini@arm.com head_inst->PC); 106713481Sgiacomo.travaglini@arm.com#endif // FULL_SYSTEM 106813481Sgiacomo.travaglini@arm.com } 106913481Sgiacomo.travaglini@arm.com 107013481Sgiacomo.travaglini@arm.com updateComInstStats(head_inst); 107113481Sgiacomo.travaglini@arm.com 107213481Sgiacomo.travaglini@arm.com if (head_inst->traceData) { 107313481Sgiacomo.travaglini@arm.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 107413481Sgiacomo.travaglini@arm.com head_inst->traceData->setCPSeq(thread[tid]->numInst); 107513481Sgiacomo.travaglini@arm.com head_inst->traceData->finalize(); 107613481Sgiacomo.travaglini@arm.com head_inst->traceData = NULL; 107713481Sgiacomo.travaglini@arm.com } 107813481Sgiacomo.travaglini@arm.com 107913481Sgiacomo.travaglini@arm.com // Update the commit rename map 108013481Sgiacomo.travaglini@arm.com for (int i = 0; i < head_inst->numDestRegs(); i++) { 108113481Sgiacomo.travaglini@arm.com renameMap[tid]->setEntry(head_inst->destRegIdx(i), 108213481Sgiacomo.travaglini@arm.com head_inst->renamedDestRegIdx(i)); 108313481Sgiacomo.travaglini@arm.com } 108413481Sgiacomo.travaglini@arm.com 108513481Sgiacomo.travaglini@arm.com // Finally clear the head ROB entry. 108613481Sgiacomo.travaglini@arm.com rob->retireHead(tid); 108713481Sgiacomo.travaglini@arm.com 108813481Sgiacomo.travaglini@arm.com // Return true to indicate that we have committed an instruction. 108913481Sgiacomo.travaglini@arm.com return true; 109013481Sgiacomo.travaglini@arm.com} 109113481Sgiacomo.travaglini@arm.com 109213481Sgiacomo.travaglini@arm.comtemplate <class Impl> 109313481Sgiacomo.travaglini@arm.comvoid 109413481Sgiacomo.travaglini@arm.comDefaultCommit<Impl>::getInsts() 109513481Sgiacomo.travaglini@arm.com{ 1096 // Read any renamed instructions and place them into the ROB. 1097 int insts_to_process = min((int)renameWidth, fromRename->size); 1098 1099 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 1100 { 1101 DynInstPtr inst = fromRename->insts[inst_num]; 1102 int tid = inst->threadNumber; 1103 1104 if (!inst->isSquashed() && 1105 commitStatus[tid] != ROBSquashing) { 1106 changedROBNumEntries[tid] = true; 1107 1108 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1109 inst->readPC(), inst->seqNum, tid); 1110 1111 rob->insertInst(inst); 1112 1113 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1114 1115 youngestSeqNum[tid] = inst->seqNum; 1116 } else { 1117 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1118 "squashed, skipping.\n", 1119 inst->readPC(), inst->seqNum, tid); 1120 } 1121 } 1122} 1123 1124template <class Impl> 1125void 1126DefaultCommit<Impl>::markCompletedInsts() 1127{ 1128 // Grab completed insts out of the IEW instruction queue, and mark 1129 // instructions completed within the ROB. 1130 for (int inst_num = 0; 1131 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1132 ++inst_num) 1133 { 1134 if (!fromIEW->insts[inst_num]->isSquashed()) { 1135 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1136 "within ROB.\n", 1137 fromIEW->insts[inst_num]->threadNumber, 1138 fromIEW->insts[inst_num]->readPC(), 1139 fromIEW->insts[inst_num]->seqNum); 1140 1141 // Mark the instruction as ready to commit. 1142 fromIEW->insts[inst_num]->setCanCommit(); 1143 } 1144 } 1145} 1146 1147template <class Impl> 1148bool 1149DefaultCommit<Impl>::robDoneSquashing() 1150{ 1151 list<unsigned>::iterator threads = (*activeThreads).begin(); 1152 1153 while (threads != (*activeThreads).end()) { 1154 unsigned tid = *threads++; 1155 1156 if (!rob->isDoneSquashing(tid)) 1157 return false; 1158 } 1159 1160 return true; 1161} 1162 1163template <class Impl> 1164void 1165DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1166{ 1167 unsigned thread = inst->threadNumber; 1168 1169 // 1170 // Pick off the software prefetches 1171 // 1172#ifdef TARGET_ALPHA 1173 if (inst->isDataPrefetch()) { 1174 statComSwp[thread]++; 1175 } else { 1176 statComInst[thread]++; 1177 } 1178#else 1179 statComInst[thread]++; 1180#endif 1181 1182 // 1183 // Control Instructions 1184 // 1185 if (inst->isControl()) 1186 statComBranches[thread]++; 1187 1188 // 1189 // Memory references 1190 // 1191 if (inst->isMemRef()) { 1192 statComRefs[thread]++; 1193 1194 if (inst->isLoad()) { 1195 statComLoads[thread]++; 1196 } 1197 } 1198 1199 if (inst->isMemBarrier()) { 1200 statComMembars[thread]++; 1201 } 1202} 1203 1204//////////////////////////////////////// 1205// // 1206// SMT COMMIT POLICY MAINTAINED HERE // 1207// // 1208//////////////////////////////////////// 1209template <class Impl> 1210int 1211DefaultCommit<Impl>::getCommittingThread() 1212{ 1213 if (numThreads > 1) { 1214 switch (commitPolicy) { 1215 1216 case Aggressive: 1217 //If Policy is Aggressive, commit will call 1218 //this function multiple times per 1219 //cycle 1220 return oldestReady(); 1221 1222 case RoundRobin: 1223 return roundRobin(); 1224 1225 case OldestReady: 1226 return oldestReady(); 1227 1228 default: 1229 return -1; 1230 } 1231 } else { 1232 int tid = (*activeThreads).front(); 1233 1234 if (commitStatus[tid] == Running || 1235 commitStatus[tid] == Idle || 1236 commitStatus[tid] == FetchTrapPending) { 1237 return tid; 1238 } else { 1239 return -1; 1240 } 1241 } 1242} 1243 1244template<class Impl> 1245int 1246DefaultCommit<Impl>::roundRobin() 1247{ 1248 list<unsigned>::iterator pri_iter = priority_list.begin(); 1249 list<unsigned>::iterator end = priority_list.end(); 1250 1251 while (pri_iter != end) { 1252 unsigned tid = *pri_iter; 1253 1254 if (commitStatus[tid] == Running || 1255 commitStatus[tid] == Idle) { 1256 1257 if (rob->isHeadReady(tid)) { 1258 priority_list.erase(pri_iter); 1259 priority_list.push_back(tid); 1260 1261 return tid; 1262 } 1263 } 1264 1265 pri_iter++; 1266 } 1267 1268 return -1; 1269} 1270 1271template<class Impl> 1272int 1273DefaultCommit<Impl>::oldestReady() 1274{ 1275 unsigned oldest = 0; 1276 bool first = true; 1277 1278 list<unsigned>::iterator threads = (*activeThreads).begin(); 1279 1280 while (threads != (*activeThreads).end()) { 1281 unsigned tid = *threads++; 1282 1283 if (!rob->isEmpty(tid) && 1284 (commitStatus[tid] == Running || 1285 commitStatus[tid] == Idle || 1286 commitStatus[tid] == FetchTrapPending)) { 1287 1288 if (rob->isHeadReady(tid)) { 1289 1290 DynInstPtr head_inst = rob->readHeadInst(tid); 1291 1292 if (first) { 1293 oldest = tid; 1294 first = false; 1295 } else if (head_inst->seqNum < oldest) { 1296 oldest = tid; 1297 } 1298 } 1299 } 1300 } 1301 1302 if (!first) { 1303 return oldest; 1304 } else { 1305 return -1; 1306 } 1307} 1308