commit_impl.hh revision 2654:9559cfa91b9d
12810SN/A/* 212728Snikos.nikoleris@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 39796Sprakash.ramrakhyani@arm.com * All rights reserved. 49796Sprakash.ramrakhyani@arm.com * 59796Sprakash.ramrakhyani@arm.com * Redistribution and use in source and binary forms, with or without 69796Sprakash.ramrakhyani@arm.com * modification, are permitted provided that the following conditions are 79796Sprakash.ramrakhyani@arm.com * met: redistributions of source code must retain the above copyright 89796Sprakash.ramrakhyani@arm.com * notice, this list of conditions and the following disclaimer; 99796Sprakash.ramrakhyani@arm.com * redistributions in binary form must reproduce the above copyright 109796Sprakash.ramrakhyani@arm.com * notice, this list of conditions and the following disclaimer in the 119796Sprakash.ramrakhyani@arm.com * documentation and/or other materials provided with the distribution; 129796Sprakash.ramrakhyani@arm.com * neither the name of the copyright holders nor the names of its 139796Sprakash.ramrakhyani@arm.com * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A */ 282810SN/A 292810SN/A#include <algorithm> 302810SN/A#include <string> 312810SN/A 322810SN/A#include "base/loader/symtab.hh" 332810SN/A#include "base/timebuf.hh" 342810SN/A#include "cpu/checker/cpu.hh" 352810SN/A#include "cpu/exetrace.hh" 362810SN/A#include "cpu/o3/commit.hh" 372810SN/A#include "cpu/o3/thread_state.hh" 382810SN/A 392810SN/Ausing namespace std; 402810SN/A 412810SN/Atemplate <class Impl> 422810SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 432810SN/A unsigned _tid) 442810SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 452810SN/A{ 462810SN/A this->setFlags(Event::AutoDelete); 472810SN/A} 482810SN/A 4911486Snikos.nikoleris@arm.comtemplate <class Impl> 5011486Snikos.nikoleris@arm.comvoid 5112727Snikos.nikoleris@arm.comDefaultCommit<Impl>::TrapEvent::process() 5212727Snikos.nikoleris@arm.com{ 5312727Snikos.nikoleris@arm.com // This will get reset by commit if it was switched out at the 545338Sstever@gmail.com // time of this event processing. 5513219Sodanrc@yahoo.com.br commit->trapSquash[tid] = true; 5612727Snikos.nikoleris@arm.com} 5712727Snikos.nikoleris@arm.com 582810SN/Atemplate <class Impl> 5912727Snikos.nikoleris@arm.comconst char * 602810SN/ADefaultCommit<Impl>::TrapEvent::description() 619796Sprakash.ramrakhyani@arm.com{ 6211893Snikos.nikoleris@arm.com return "Trap event"; 6311893Snikos.nikoleris@arm.com} 6411722Ssophiane.senni@gmail.com 6511722Ssophiane.senni@gmail.comtemplate <class Impl> 6611722Ssophiane.senni@gmail.comDefaultCommit<Impl>::DefaultCommit(Params *params) 6711722Ssophiane.senni@gmail.com : dcacheInterface(params->dcacheInterface), 6813219Sodanrc@yahoo.com.br squashCounter(0), 6912513Sodanrc@yahoo.com.br iewToCommitDelay(params->iewToCommitDelay), 7012629Sodanrc@yahoo.com.br commitToIEWDelay(params->commitToIEWDelay), 7112629Sodanrc@yahoo.com.br renameToROBDelay(params->renameToROBDelay), 729796Sprakash.ramrakhyani@arm.com fetchToCommitDelay(params->commitToFetchDelay), 739796Sprakash.ramrakhyani@arm.com renameWidth(params->renameWidth), 749796Sprakash.ramrakhyani@arm.com iewWidth(params->executeWidth), 752810SN/A commitWidth(params->commitWidth), 762810SN/A numThreads(params->numberOfThreads), 772810SN/A switchedOut(false), 7810360Sandreas.hansson@arm.com trapLatency(params->trapLatency), 792810SN/A fetchTrapLatency(params->fetchTrapLatency) 802810SN/A{ 812810SN/A _status = Active; 8213219Sodanrc@yahoo.com.br _nextStatus = Inactive; 8313219Sodanrc@yahoo.com.br string policy = params->smtCommitPolicy; 8413217Sodanrc@yahoo.com.br 8513219Sodanrc@yahoo.com.br //Convert string to lowercase 8613217Sodanrc@yahoo.com.br std::transform(policy.begin(), policy.end(), policy.begin(), 8713217Sodanrc@yahoo.com.br (int(*)(int)) tolower); 8813217Sodanrc@yahoo.com.br 8913217Sodanrc@yahoo.com.br //Assign commit policy 9013217Sodanrc@yahoo.com.br if (policy == "aggressive"){ 9113217Sodanrc@yahoo.com.br commitPolicy = Aggressive; 9213217Sodanrc@yahoo.com.br 9313217Sodanrc@yahoo.com.br DPRINTF(Commit,"Commit Policy set to Aggressive."); 9413219Sodanrc@yahoo.com.br } else if (policy == "roundrobin"){ 9513219Sodanrc@yahoo.com.br commitPolicy = RoundRobin; 9613219Sodanrc@yahoo.com.br 9713217Sodanrc@yahoo.com.br //Set-Up Priority List 9813217Sodanrc@yahoo.com.br for (int tid=0; tid < numThreads; tid++) { 9913219Sodanrc@yahoo.com.br priority_list.push_back(tid); 10013217Sodanrc@yahoo.com.br } 10113217Sodanrc@yahoo.com.br 10213217Sodanrc@yahoo.com.br DPRINTF(Commit,"Commit Policy set to Round Robin."); 10313217Sodanrc@yahoo.com.br } else if (policy == "oldestready"){ 10413217Sodanrc@yahoo.com.br commitPolicy = OldestReady; 10513217Sodanrc@yahoo.com.br 10613217Sodanrc@yahoo.com.br DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 10713217Sodanrc@yahoo.com.br } else { 10813217Sodanrc@yahoo.com.br assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 10913217Sodanrc@yahoo.com.br "RoundRobin,OldestReady}"); 11013217Sodanrc@yahoo.com.br } 1112810SN/A 11213215Sodanrc@yahoo.com.br for (int i=0; i < numThreads; i++) { 11313215Sodanrc@yahoo.com.br commitStatus[i] = Idle; 11413215Sodanrc@yahoo.com.br changedROBNumEntries[i] = false; 11512636Sodanrc@yahoo.com.br trapSquash[i] = false; 11612722Snikos.nikoleris@arm.com xcSquash[i] = false; 11712722Snikos.nikoleris@arm.com } 11812636Sodanrc@yahoo.com.br 11912636Sodanrc@yahoo.com.br fetchFaultTick = 0; 12012636Sodanrc@yahoo.com.br fetchTrapWait = 0; 12113215Sodanrc@yahoo.com.br} 12213215Sodanrc@yahoo.com.br 12312636Sodanrc@yahoo.com.brtemplate <class Impl> 12412691Sodanrc@yahoo.com.brstd::string 12513215Sodanrc@yahoo.com.brDefaultCommit<Impl>::name() const 12612636Sodanrc@yahoo.com.br{ 12713215Sodanrc@yahoo.com.br return cpu->name() + ".commit"; 12812703Snikos.nikoleris@arm.com} 12912703Snikos.nikoleris@arm.com 13012703Snikos.nikoleris@arm.comtemplate <class Impl> 13112703Snikos.nikoleris@arm.comvoid 13212703Snikos.nikoleris@arm.comDefaultCommit<Impl>::regStats() 13312636Sodanrc@yahoo.com.br{ 13412636Sodanrc@yahoo.com.br using namespace Stats; 13512636Sodanrc@yahoo.com.br commitCommittedInsts 13612636Sodanrc@yahoo.com.br .name(name() + ".commitCommittedInsts") 13712636Sodanrc@yahoo.com.br .desc("The number of committed instructions") 13813219Sodanrc@yahoo.com.br .prereq(commitCommittedInsts); 13913219Sodanrc@yahoo.com.br commitSquashedInsts 14013219Sodanrc@yahoo.com.br .name(name() + ".commitSquashedInsts") 14113219Sodanrc@yahoo.com.br .desc("The number of squashed insts skipped by commit") 14213219Sodanrc@yahoo.com.br .prereq(commitSquashedInsts); 14313219Sodanrc@yahoo.com.br commitSquashEvents 14412636Sodanrc@yahoo.com.br .name(name() + ".commitSquashEvents") 14512728Snikos.nikoleris@arm.com .desc("The number of times commit is told to squash") 14612728Snikos.nikoleris@arm.com .prereq(commitSquashEvents); 14712728Snikos.nikoleris@arm.com commitNonSpecStalls 14812728Snikos.nikoleris@arm.com .name(name() + ".commitNonSpecStalls") 14912728Snikos.nikoleris@arm.com .desc("The number of times commit has been forced to stall to " 15012728Snikos.nikoleris@arm.com "communicate backwards") 15112728Snikos.nikoleris@arm.com .prereq(commitNonSpecStalls); 15212728Snikos.nikoleris@arm.com branchMispredicts 15312728Snikos.nikoleris@arm.com .name(name() + ".branchMispredicts") 15412728Snikos.nikoleris@arm.com .desc("The number of times a branch was mispredicted") 15512728Snikos.nikoleris@arm.com .prereq(branchMispredicts); 15612728Snikos.nikoleris@arm.com numCommittedDist 15712728Snikos.nikoleris@arm.com .init(0,commitWidth,1) 15812728Snikos.nikoleris@arm.com .name(name() + ".COM:committed_per_cycle") 15912728Snikos.nikoleris@arm.com .desc("Number of insts commited each cycle") 16012728Snikos.nikoleris@arm.com .flags(Stats::pdf) 16112728Snikos.nikoleris@arm.com ; 16212728Snikos.nikoleris@arm.com 16312728Snikos.nikoleris@arm.com statComInst 16412728Snikos.nikoleris@arm.com .init(cpu->number_of_threads) 16512728Snikos.nikoleris@arm.com .name(name() + ".COM:count") 16612728Snikos.nikoleris@arm.com .desc("Number of instructions committed") 16712728Snikos.nikoleris@arm.com .flags(total) 16812728Snikos.nikoleris@arm.com ; 16912728Snikos.nikoleris@arm.com 17012728Snikos.nikoleris@arm.com statComSwp 17112728Snikos.nikoleris@arm.com .init(cpu->number_of_threads) 17212728Snikos.nikoleris@arm.com .name(name() + ".COM:swp_count") 17312728Snikos.nikoleris@arm.com .desc("Number of s/w prefetches committed") 17412728Snikos.nikoleris@arm.com .flags(total) 17512728Snikos.nikoleris@arm.com ; 17612728Snikos.nikoleris@arm.com 17712728Snikos.nikoleris@arm.com statComRefs 17812728Snikos.nikoleris@arm.com .init(cpu->number_of_threads) 17912728Snikos.nikoleris@arm.com .name(name() + ".COM:refs") 18012728Snikos.nikoleris@arm.com .desc("Number of memory references committed") 18112728Snikos.nikoleris@arm.com .flags(total) 18212728Snikos.nikoleris@arm.com ; 18312728Snikos.nikoleris@arm.com 18412728Snikos.nikoleris@arm.com statComLoads 18512728Snikos.nikoleris@arm.com .init(cpu->number_of_threads) 18612728Snikos.nikoleris@arm.com .name(name() + ".COM:loads") 18712728Snikos.nikoleris@arm.com .desc("Number of loads committed") 18812728Snikos.nikoleris@arm.com .flags(total) 18912728Snikos.nikoleris@arm.com ; 19012728Snikos.nikoleris@arm.com 19112728Snikos.nikoleris@arm.com statComMembars 19212728Snikos.nikoleris@arm.com .init(cpu->number_of_threads) 19312728Snikos.nikoleris@arm.com .name(name() + ".COM:membars") 19412728Snikos.nikoleris@arm.com .desc("Number of memory barriers committed") 19512728Snikos.nikoleris@arm.com .flags(total) 19612728Snikos.nikoleris@arm.com ; 19712728Snikos.nikoleris@arm.com 19812728Snikos.nikoleris@arm.com statComBranches 19912728Snikos.nikoleris@arm.com .init(cpu->number_of_threads) 20012728Snikos.nikoleris@arm.com .name(name() + ".COM:branches") 20112728Snikos.nikoleris@arm.com .desc("Number of branches committed") 20212728Snikos.nikoleris@arm.com .flags(total) 20312728Snikos.nikoleris@arm.com ; 20413222Sodanrc@yahoo.com.br 20512728Snikos.nikoleris@arm.com // 20612728Snikos.nikoleris@arm.com // Commit-Eligible instructions... 20712728Snikos.nikoleris@arm.com // 20812728Snikos.nikoleris@arm.com // -> The number of instructions eligible to commit in those 20912728Snikos.nikoleris@arm.com // cycles where we reached our commit BW limit (less the number 21012728Snikos.nikoleris@arm.com // actually committed) 21112728Snikos.nikoleris@arm.com // 21212728Snikos.nikoleris@arm.com // -> The average value is computed over ALL CYCLES... not just 21312728Snikos.nikoleris@arm.com // the BW limited cycles 21412728Snikos.nikoleris@arm.com // 2159796Sprakash.ramrakhyani@arm.com // -> The standard deviation is computed only over cycles where 2162810SN/A // we reached the BW limit 21711522Sstephan.diestelhorst@arm.com // 21811522Sstephan.diestelhorst@arm.com commitEligible 2192810SN/A .init(cpu->number_of_threads) 22011522Sstephan.diestelhorst@arm.com .name(name() + ".COM:bw_limited") 2212810SN/A .desc("number of insts not committed due to BW limits") 2229796Sprakash.ramrakhyani@arm.com .flags(total) 2232810SN/A ; 2242810SN/A 2252810SN/A commitEligibleSamples 2262810SN/A .name(name() + ".COM:bw_lim_events") 2279796Sprakash.ramrakhyani@arm.com .desc("number cycles where commit BW limit reached") 2282810SN/A ; 2292810SN/A} 2302810SN/A 2312810SN/Atemplate <class Impl> 2329796Sprakash.ramrakhyani@arm.comvoid 2332810SN/ADefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr) 2342810SN/A{ 2352810SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2362810SN/A cpu = cpu_ptr; 2379796Sprakash.ramrakhyani@arm.com 2382810SN/A // Commit must broadcast the number of free entries it has at the start of 2392810SN/A // the simulation, so it starts as active. 2402810SN/A cpu->activateStage(FullCPU::CommitIdx); 2412810SN/A 2422810SN/A trapLatency = cpu->cycles(trapLatency); 2432810SN/A fetchTrapLatency = cpu->cycles(fetchTrapLatency); 2449796Sprakash.ramrakhyani@arm.com} 2452810SN/A 2462810SN/Atemplate <class Impl> 2472810SN/Avoid 2486978SLisa.Hsu@amd.comDefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 2498833Sdam.sunwoo@arm.com{ 2509796Sprakash.ramrakhyani@arm.com thread = threads; 2518833Sdam.sunwoo@arm.com} 2526978SLisa.Hsu@amd.com 2536978SLisa.Hsu@amd.comtemplate <class Impl> 2548833Sdam.sunwoo@arm.comvoid 2558833Sdam.sunwoo@arm.comDefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2568833Sdam.sunwoo@arm.com{ 2576978SLisa.Hsu@amd.com DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2586978SLisa.Hsu@amd.com timeBuffer = tb_ptr; 2599796Sprakash.ramrakhyani@arm.com 2606978SLisa.Hsu@amd.com // Setup wire to send information back to IEW. 2618833Sdam.sunwoo@arm.com toIEW = timeBuffer->getWire(0); 2626978SLisa.Hsu@amd.com 2638833Sdam.sunwoo@arm.com // Setup wire to read data from IEW (for the ROB). 2648833Sdam.sunwoo@arm.com robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2658833Sdam.sunwoo@arm.com} 2666978SLisa.Hsu@amd.com 2676978SLisa.Hsu@amd.comtemplate <class Impl> 2686978SLisa.Hsu@amd.comvoid 26910024Sdam.sunwoo@arm.comDefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 27010024Sdam.sunwoo@arm.com{ 27110024Sdam.sunwoo@arm.com DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 27210024Sdam.sunwoo@arm.com fetchQueue = fq_ptr; 27310024Sdam.sunwoo@arm.com 27410024Sdam.sunwoo@arm.com // Setup wire to get instructions from rename (for the ROB). 27510024Sdam.sunwoo@arm.com fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 27610024Sdam.sunwoo@arm.com} 27710024Sdam.sunwoo@arm.com 27810024Sdam.sunwoo@arm.comtemplate <class Impl> 27910024Sdam.sunwoo@arm.comvoid 28010024Sdam.sunwoo@arm.comDefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 28110024Sdam.sunwoo@arm.com{ 28210024Sdam.sunwoo@arm.com DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 28310024Sdam.sunwoo@arm.com renameQueue = rq_ptr; 28410024Sdam.sunwoo@arm.com 28510024Sdam.sunwoo@arm.com // Setup wire to get instructions from rename (for the ROB). 28610024Sdam.sunwoo@arm.com fromRename = renameQueue->getWire(-renameToROBDelay); 28710024Sdam.sunwoo@arm.com} 28810024Sdam.sunwoo@arm.com 28910024Sdam.sunwoo@arm.comtemplate <class Impl> 29010024Sdam.sunwoo@arm.comvoid 29110025Stimothy.jones@arm.comDefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 29210025Stimothy.jones@arm.com{ 29310025Stimothy.jones@arm.com DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 29410025Stimothy.jones@arm.com iewQueue = iq_ptr; 29510025Stimothy.jones@arm.com 29610025Stimothy.jones@arm.com // Setup wire to get instructions from IEW. 29710025Stimothy.jones@arm.com fromIEW = iewQueue->getWire(-iewToCommitDelay); 29810025Stimothy.jones@arm.com} 29910025Stimothy.jones@arm.com 30010025Stimothy.jones@arm.comtemplate <class Impl> 30110024Sdam.sunwoo@arm.comvoid 3022810SN/ADefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 3032810SN/A{ 304 fetchStage = fetch_stage; 305} 306 307template <class Impl> 308void 309DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 310{ 311 iewStage = iew_stage; 312} 313 314template<class Impl> 315void 316DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 317{ 318 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 319 activeThreads = at_ptr; 320} 321 322template <class Impl> 323void 324DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 325{ 326 DPRINTF(Commit, "Setting rename map pointers.\n"); 327 328 for (int i=0; i < numThreads; i++) { 329 renameMap[i] = &rm_ptr[i]; 330 } 331} 332 333template <class Impl> 334void 335DefaultCommit<Impl>::setROB(ROB *rob_ptr) 336{ 337 DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 338 rob = rob_ptr; 339} 340 341template <class Impl> 342void 343DefaultCommit<Impl>::initStage() 344{ 345 rob->setActiveThreads(activeThreads); 346 rob->resetEntries(); 347 348 // Broadcast the number of free entries. 349 for (int i=0; i < numThreads; i++) { 350 toIEW->commitInfo[i].usedROB = true; 351 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 352 } 353 354 cpu->activityThisCycle(); 355} 356 357template <class Impl> 358void 359DefaultCommit<Impl>::switchOut() 360{ 361 switchPending = true; 362} 363 364template <class Impl> 365void 366DefaultCommit<Impl>::doSwitchOut() 367{ 368 switchedOut = true; 369 switchPending = false; 370 rob->switchOut(); 371} 372 373template <class Impl> 374void 375DefaultCommit<Impl>::takeOverFrom() 376{ 377 switchedOut = false; 378 _status = Active; 379 _nextStatus = Inactive; 380 for (int i=0; i < numThreads; i++) { 381 commitStatus[i] = Idle; 382 changedROBNumEntries[i] = false; 383 trapSquash[i] = false; 384 xcSquash[i] = false; 385 } 386 squashCounter = 0; 387 rob->takeOverFrom(); 388} 389 390template <class Impl> 391void 392DefaultCommit<Impl>::updateStatus() 393{ 394 // reset ROB changed variable 395 list<unsigned>::iterator threads = (*activeThreads).begin(); 396 while (threads != (*activeThreads).end()) { 397 unsigned tid = *threads++; 398 changedROBNumEntries[tid] = false; 399 400 // Also check if any of the threads has a trap pending 401 if (commitStatus[tid] == TrapPending || 402 commitStatus[tid] == FetchTrapPending) { 403 _nextStatus = Active; 404 } 405 } 406 407 if (_nextStatus == Inactive && _status == Active) { 408 DPRINTF(Activity, "Deactivating stage.\n"); 409 cpu->deactivateStage(FullCPU::CommitIdx); 410 } else if (_nextStatus == Active && _status == Inactive) { 411 DPRINTF(Activity, "Activating stage.\n"); 412 cpu->activateStage(FullCPU::CommitIdx); 413 } 414 415 _status = _nextStatus; 416} 417 418template <class Impl> 419void 420DefaultCommit<Impl>::setNextStatus() 421{ 422 int squashes = 0; 423 424 list<unsigned>::iterator threads = (*activeThreads).begin(); 425 426 while (threads != (*activeThreads).end()) { 427 unsigned tid = *threads++; 428 429 if (commitStatus[tid] == ROBSquashing) { 430 squashes++; 431 } 432 } 433 434 assert(squashes == squashCounter); 435 436 // If commit is currently squashing, then it will have activity for the 437 // next cycle. Set its next status as active. 438 if (squashCounter) { 439 _nextStatus = Active; 440 } 441} 442 443template <class Impl> 444bool 445DefaultCommit<Impl>::changedROBEntries() 446{ 447 list<unsigned>::iterator threads = (*activeThreads).begin(); 448 449 while (threads != (*activeThreads).end()) { 450 unsigned tid = *threads++; 451 452 if (changedROBNumEntries[tid]) { 453 return true; 454 } 455 } 456 457 return false; 458} 459 460template <class Impl> 461unsigned 462DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 463{ 464 return rob->numFreeEntries(tid); 465} 466 467template <class Impl> 468void 469DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 470{ 471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 472 473 TrapEvent *trap = new TrapEvent(this, tid); 474 475 trap->schedule(curTick + trapLatency); 476 477 thread[tid]->trapPending = true; 478} 479 480template <class Impl> 481void 482DefaultCommit<Impl>::generateXCEvent(unsigned tid) 483{ 484 DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid); 485 486 xcSquash[tid] = true; 487} 488 489template <class Impl> 490void 491DefaultCommit<Impl>::squashAll(unsigned tid) 492{ 493 // If we want to include the squashing instruction in the squash, 494 // then use one older sequence number. 495 // Hopefully this doesn't mess things up. Basically I want to squash 496 // all instructions of this thread. 497 InstSeqNum squashed_inst = rob->isEmpty() ? 498 0 : rob->readHeadInst(tid)->seqNum - 1;; 499 500 // All younger instructions will be squashed. Set the sequence 501 // number as the youngest instruction in the ROB (0 in this case. 502 // Hopefully nothing breaks.) 503 youngestSeqNum[tid] = 0; 504 505 rob->squash(squashed_inst, tid); 506 changedROBNumEntries[tid] = true; 507 508 // Send back the sequence number of the squashed instruction. 509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 510 511 // Send back the squash signal to tell stages that they should 512 // squash. 513 toIEW->commitInfo[tid].squash = true; 514 515 // Send back the rob squashing signal so other stages know that 516 // the ROB is in the process of squashing. 517 toIEW->commitInfo[tid].robSquashing = true; 518 519 toIEW->commitInfo[tid].branchMispredict = false; 520 521 toIEW->commitInfo[tid].nextPC = PC[tid]; 522} 523 524template <class Impl> 525void 526DefaultCommit<Impl>::squashFromTrap(unsigned tid) 527{ 528 squashAll(tid); 529 530 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 531 532 thread[tid]->trapPending = false; 533 thread[tid]->inSyscall = false; 534 535 trapSquash[tid] = false; 536 537 commitStatus[tid] = ROBSquashing; 538 cpu->activityThisCycle(); 539 540 ++squashCounter; 541} 542 543template <class Impl> 544void 545DefaultCommit<Impl>::squashFromXC(unsigned tid) 546{ 547 squashAll(tid); 548 549 DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]); 550 551 thread[tid]->inSyscall = false; 552 assert(!thread[tid]->trapPending); 553 554 commitStatus[tid] = ROBSquashing; 555 cpu->activityThisCycle(); 556 557 xcSquash[tid] = false; 558 559 ++squashCounter; 560} 561 562template <class Impl> 563void 564DefaultCommit<Impl>::tick() 565{ 566 wroteToTimeBuffer = false; 567 _nextStatus = Inactive; 568 569 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 570 cpu->signalSwitched(); 571 return; 572 } 573 574 list<unsigned>::iterator threads = (*activeThreads).begin(); 575 576 // Check if any of the threads are done squashing. Change the 577 // status if they are done. 578 while (threads != (*activeThreads).end()) { 579 unsigned tid = *threads++; 580 581 if (commitStatus[tid] == ROBSquashing) { 582 583 if (rob->isDoneSquashing(tid)) { 584 commitStatus[tid] = Running; 585 --squashCounter; 586 } else { 587 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 588 "insts this cycle.\n", tid); 589 } 590 } 591 } 592 593 commit(); 594 595 markCompletedInsts(); 596 597 threads = (*activeThreads).begin(); 598 599 while (threads != (*activeThreads).end()) { 600 unsigned tid = *threads++; 601 602 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 603 // The ROB has more instructions it can commit. Its next status 604 // will be active. 605 _nextStatus = Active; 606 607 DynInstPtr inst = rob->readHeadInst(tid); 608 609 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 610 " ROB and ready to commit\n", 611 tid, inst->seqNum, inst->readPC()); 612 613 } else if (!rob->isEmpty(tid)) { 614 DynInstPtr inst = rob->readHeadInst(tid); 615 616 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 617 "%#x is head of ROB and not ready\n", 618 tid, inst->seqNum, inst->readPC()); 619 } 620 621 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 622 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 623 } 624 625 626 if (wroteToTimeBuffer) { 627 DPRINTF(Activity, "Activity This Cycle.\n"); 628 cpu->activityThisCycle(); 629 } 630 631 updateStatus(); 632} 633 634template <class Impl> 635void 636DefaultCommit<Impl>::commit() 637{ 638 639 ////////////////////////////////////// 640 // Check for interrupts 641 ////////////////////////////////////// 642 643#if FULL_SYSTEM 644 // Process interrupts if interrupts are enabled, not in PAL mode, 645 // and no other traps or external squashes are currently pending. 646 // @todo: Allow other threads to handle interrupts. 647 if (cpu->checkInterrupts && 648 cpu->check_interrupts() && 649 !cpu->inPalMode(readPC()) && 650 !trapSquash[0] && 651 !xcSquash[0]) { 652 // Tell fetch that there is an interrupt pending. This will 653 // make fetch wait until it sees a non PAL-mode PC, at which 654 // point it stops fetching instructions. 655 toIEW->commitInfo[0].interruptPending = true; 656 657 // Wait until the ROB is empty and all stores have drained in 658 // order to enter the interrupt. 659 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 660 // Not sure which thread should be the one to interrupt. For now 661 // always do thread 0. 662 assert(!thread[0]->inSyscall); 663 thread[0]->inSyscall = true; 664 665 // CPU will handle implementation of the interrupt. 666 cpu->processInterrupts(); 667 668 // Now squash or record that I need to squash this cycle. 669 commitStatus[0] = TrapPending; 670 671 // Exit state update mode to avoid accidental updating. 672 thread[0]->inSyscall = false; 673 674 // Generate trap squash event. 675 generateTrapEvent(0); 676 677 toIEW->commitInfo[0].clearInterrupt = true; 678 679 DPRINTF(Commit, "Interrupt detected.\n"); 680 } else { 681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 682 } 683 } 684#endif // FULL_SYSTEM 685 686 //////////////////////////////////// 687 // Check for any possible squashes, handle them first 688 //////////////////////////////////// 689 690 list<unsigned>::iterator threads = (*activeThreads).begin(); 691 692 while (threads != (*activeThreads).end()) { 693 unsigned tid = *threads++; 694 695 if (fromFetch->fetchFault && commitStatus[0] != TrapPending) { 696 // Record the fault. Wait until it's empty in the ROB. 697 // Then handle the trap. Ignore it if there's already a 698 // trap pending as fetch will be redirected. 699 fetchFault = fromFetch->fetchFault; 700 fetchFaultTick = curTick + fetchTrapLatency; 701 commitStatus[0] = FetchTrapPending; 702 DPRINTF(Commit, "Fault from fetch recorded. Will trap if the " 703 "ROB empties without squashing the fault.\n"); 704 fetchTrapWait = 0; 705 } 706 707 // Fetch may tell commit to clear the trap if it's been squashed. 708 if (fromFetch->clearFetchFault) { 709 DPRINTF(Commit, "Received clear fetch fault signal\n"); 710 fetchTrapWait = 0; 711 if (commitStatus[0] == FetchTrapPending) { 712 DPRINTF(Commit, "Clearing fault from fetch\n"); 713 commitStatus[0] = Running; 714 } 715 } 716 717 // Not sure which one takes priority. I think if we have 718 // both, that's a bad sign. 719 if (trapSquash[tid] == true) { 720 assert(!xcSquash[tid]); 721 squashFromTrap(tid); 722 } else if (xcSquash[tid] == true) { 723 squashFromXC(tid); 724 } 725 726 // Squashed sequence number must be older than youngest valid 727 // instruction in the ROB. This prevents squashes from younger 728 // instructions overriding squashes from older instructions. 729 if (fromIEW->squash[tid] && 730 commitStatus[tid] != TrapPending && 731 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 732 733 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 734 tid, 735 fromIEW->mispredPC[tid], 736 fromIEW->squashedSeqNum[tid]); 737 738 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 739 tid, 740 fromIEW->nextPC[tid]); 741 742 commitStatus[tid] = ROBSquashing; 743 744 ++squashCounter; 745 746 // If we want to include the squashing instruction in the squash, 747 // then use one older sequence number. 748 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 749 750 if (fromIEW->includeSquashInst[tid] == true) 751 squashed_inst--; 752 753 // All younger instructions will be squashed. Set the sequence 754 // number as the youngest instruction in the ROB. 755 youngestSeqNum[tid] = squashed_inst; 756 757 rob->squash(squashed_inst, tid); 758 changedROBNumEntries[tid] = true; 759 760 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 761 762 toIEW->commitInfo[tid].squash = true; 763 764 // Send back the rob squashing signal so other stages know that 765 // the ROB is in the process of squashing. 766 toIEW->commitInfo[tid].robSquashing = true; 767 768 toIEW->commitInfo[tid].branchMispredict = 769 fromIEW->branchMispredict[tid]; 770 771 toIEW->commitInfo[tid].branchTaken = 772 fromIEW->branchTaken[tid]; 773 774 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 775 776 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 777 778 if (toIEW->commitInfo[tid].branchMispredict) { 779 ++branchMispredicts; 780 } 781 } 782 783 } 784 785 setNextStatus(); 786 787 if (squashCounter != numThreads) { 788 // If we're not currently squashing, then get instructions. 789 getInsts(); 790 791 // Try to commit any instructions. 792 commitInsts(); 793 } 794 795 //Check for any activity 796 threads = (*activeThreads).begin(); 797 798 while (threads != (*activeThreads).end()) { 799 unsigned tid = *threads++; 800 801 if (changedROBNumEntries[tid]) { 802 toIEW->commitInfo[tid].usedROB = true; 803 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 804 805 if (rob->isEmpty(tid)) { 806 toIEW->commitInfo[tid].emptyROB = true; 807 } 808 809 wroteToTimeBuffer = true; 810 changedROBNumEntries[tid] = false; 811 } 812 } 813} 814 815template <class Impl> 816void 817DefaultCommit<Impl>::commitInsts() 818{ 819 //////////////////////////////////// 820 // Handle commit 821 // Note that commit will be handled prior to putting new 822 // instructions in the ROB so that the ROB only tries to commit 823 // instructions it has in this current cycle, and not instructions 824 // it is writing in during this cycle. Can't commit and squash 825 // things at the same time... 826 //////////////////////////////////// 827 828 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 829 830 unsigned num_committed = 0; 831 832 DynInstPtr head_inst; 833 834 // Commit as many instructions as possible until the commit bandwidth 835 // limit is reached, or it becomes impossible to commit any more. 836 while (num_committed < commitWidth) { 837 int commit_thread = getCommittingThread(); 838 839 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 840 break; 841 842 head_inst = rob->readHeadInst(commit_thread); 843 844 int tid = head_inst->threadNumber; 845 846 assert(tid == commit_thread); 847 848 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 849 head_inst->seqNum, tid); 850 851 // If the head instruction is squashed, it is ready to retire 852 // (be removed from the ROB) at any time. 853 if (head_inst->isSquashed()) { 854 855 DPRINTF(Commit, "Retiring squashed instruction from " 856 "ROB.\n"); 857 858 rob->retireHead(commit_thread); 859 860 ++commitSquashedInsts; 861 862 // Record that the number of ROB entries has changed. 863 changedROBNumEntries[tid] = true; 864 } else { 865 PC[tid] = head_inst->readPC(); 866 nextPC[tid] = head_inst->readNextPC(); 867 868 // Increment the total number of non-speculative instructions 869 // executed. 870 // Hack for now: it really shouldn't happen until after the 871 // commit is deemed to be successful, but this count is needed 872 // for syscalls. 873 thread[tid]->funcExeInst++; 874 875 // Try to commit the head instruction. 876 bool commit_success = commitHead(head_inst, num_committed); 877 878 if (commit_success) { 879 ++num_committed; 880 881 changedROBNumEntries[tid] = true; 882 883 // Set the doneSeqNum to the youngest committed instruction. 884 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 885 886 ++commitCommittedInsts; 887 888 // To match the old model, don't count nops and instruction 889 // prefetches towards the total commit count. 890 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 891 cpu->instDone(tid); 892 } 893 894 PC[tid] = nextPC[tid]; 895 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 896#if FULL_SYSTEM 897 int count = 0; 898 Addr oldpc; 899 do { 900 // Debug statement. Checks to make sure we're not 901 // currently updating state while handling PC events. 902 if (count == 0) 903 assert(!thread[tid]->inSyscall && 904 !thread[tid]->trapPending); 905 oldpc = PC[tid]; 906 cpu->system->pcEventQueue.service( 907 thread[tid]->getXCProxy()); 908 count++; 909 } while (oldpc != PC[tid]); 910 if (count > 1) { 911 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 912 break; 913 } 914#endif 915 } else { 916 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 917 "[tid:%i] [sn:%i].\n", 918 head_inst->readPC(), tid ,head_inst->seqNum); 919 break; 920 } 921 } 922 } 923 924 DPRINTF(CommitRate, "%i\n", num_committed); 925 numCommittedDist.sample(num_committed); 926 927 if (num_committed == commitWidth) { 928 commitEligible[0]++; 929 } 930} 931 932template <class Impl> 933bool 934DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 935{ 936 assert(head_inst); 937 938 int tid = head_inst->threadNumber; 939 940 // If the instruction is not executed yet, then it will need extra 941 // handling. Signal backwards that it should be executed. 942 if (!head_inst->isExecuted()) { 943 // Keep this number correct. We have not yet actually executed 944 // and committed this instruction. 945 thread[tid]->funcExeInst--; 946 947 head_inst->reachedCommit = true; 948 949 if (head_inst->isNonSpeculative() || 950 head_inst->isMemBarrier() || 951 head_inst->isWriteBarrier()) { 952 953 DPRINTF(Commit, "Encountered a barrier or non-speculative " 954 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 955 head_inst->seqNum, head_inst->readPC()); 956 957#if !FULL_SYSTEM 958 // Hack to make sure syscalls/memory barriers/quiesces 959 // aren't executed until all stores write back their data. 960 // This direct communication shouldn't be used for 961 // anything other than this. 962 if (inst_num > 0 || iewStage->hasStoresToWB()) 963#else 964 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 965 head_inst->isQuiesce()) && 966 iewStage->hasStoresToWB()) 967#endif 968 { 969 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 970 return false; 971 } 972 973 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 974 975 // Change the instruction so it won't try to commit again until 976 // it is executed. 977 head_inst->clearCanCommit(); 978 979 ++commitNonSpecStalls; 980 981 return false; 982 } else if (head_inst->isLoad()) { 983 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 984 head_inst->seqNum, head_inst->readPC()); 985 986 // Send back the non-speculative instruction's sequence 987 // number. Tell the lsq to re-execute the load. 988 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 989 toIEW->commitInfo[tid].uncached = true; 990 toIEW->commitInfo[tid].uncachedLoad = head_inst; 991 992 head_inst->clearCanCommit(); 993 994 return false; 995 } else { 996 panic("Trying to commit un-executed instruction " 997 "of unknown type!\n"); 998 } 999 } 1000 1001 if (head_inst->isThreadSync()) { 1002 // Not handled for now. 1003 panic("Thread sync instructions are not handled yet.\n"); 1004 } 1005 1006 // Stores mark themselves as completed. 1007 if (!head_inst->isStore()) { 1008 head_inst->setCompleted(); 1009 } 1010 1011 // Use checker prior to updating anything due to traps or PC 1012 // based events. 1013 if (cpu->checker) { 1014 cpu->checker->tick(head_inst); 1015 } 1016 1017 // Check if the instruction caused a fault. If so, trap. 1018 Fault inst_fault = head_inst->getFault(); 1019 1020 if (inst_fault != NoFault) { 1021 head_inst->setCompleted(); 1022#if FULL_SYSTEM 1023 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1024 head_inst->seqNum, head_inst->readPC()); 1025 1026 if (iewStage->hasStoresToWB() || inst_num > 0) { 1027 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1028 return false; 1029 } 1030 1031 if (cpu->checker && head_inst->isStore()) { 1032 cpu->checker->tick(head_inst); 1033 } 1034 1035 assert(!thread[tid]->inSyscall); 1036 1037 // Mark that we're in state update mode so that the trap's 1038 // execution doesn't generate extra squashes. 1039 thread[tid]->inSyscall = true; 1040 1041 // DTB will sometimes need the machine instruction for when 1042 // faults happen. So we will set it here, prior to the DTB 1043 // possibly needing it for its fault. 1044 thread[tid]->setInst( 1045 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1046 1047 // Execute the trap. Although it's slightly unrealistic in 1048 // terms of timing (as it doesn't wait for the full timing of 1049 // the trap event to complete before updating state), it's 1050 // needed to update the state as soon as possible. This 1051 // prevents external agents from changing any specific state 1052 // that the trap need. 1053 cpu->trap(inst_fault, tid); 1054 1055 // Exit state update mode to avoid accidental updating. 1056 thread[tid]->inSyscall = false; 1057 1058 commitStatus[tid] = TrapPending; 1059 1060 // Generate trap squash event. 1061 generateTrapEvent(tid); 1062 1063 return false; 1064#else // !FULL_SYSTEM 1065 panic("fault (%d) detected @ PC %08p", inst_fault, 1066 head_inst->PC); 1067#endif // FULL_SYSTEM 1068 } 1069 1070 updateComInstStats(head_inst); 1071 1072 if (head_inst->traceData) { 1073 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1074 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1075 head_inst->traceData->finalize(); 1076 head_inst->traceData = NULL; 1077 } 1078 1079 // Update the commit rename map 1080 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1081 renameMap[tid]->setEntry(head_inst->destRegIdx(i), 1082 head_inst->renamedDestRegIdx(i)); 1083 } 1084 1085 // Finally clear the head ROB entry. 1086 rob->retireHead(tid); 1087 1088 // Return true to indicate that we have committed an instruction. 1089 return true; 1090} 1091 1092template <class Impl> 1093void 1094DefaultCommit<Impl>::getInsts() 1095{ 1096 // Read any renamed instructions and place them into the ROB. 1097 int insts_to_process = min((int)renameWidth, fromRename->size); 1098 1099 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 1100 { 1101 DynInstPtr inst = fromRename->insts[inst_num]; 1102 int tid = inst->threadNumber; 1103 1104 if (!inst->isSquashed() && 1105 commitStatus[tid] != ROBSquashing) { 1106 changedROBNumEntries[tid] = true; 1107 1108 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1109 inst->readPC(), inst->seqNum, tid); 1110 1111 rob->insertInst(inst); 1112 1113 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1114 1115 youngestSeqNum[tid] = inst->seqNum; 1116 } else { 1117 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1118 "squashed, skipping.\n", 1119 inst->readPC(), inst->seqNum, tid); 1120 } 1121 } 1122} 1123 1124template <class Impl> 1125void 1126DefaultCommit<Impl>::markCompletedInsts() 1127{ 1128 // Grab completed insts out of the IEW instruction queue, and mark 1129 // instructions completed within the ROB. 1130 for (int inst_num = 0; 1131 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1132 ++inst_num) 1133 { 1134 if (!fromIEW->insts[inst_num]->isSquashed()) { 1135 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1136 "within ROB.\n", 1137 fromIEW->insts[inst_num]->threadNumber, 1138 fromIEW->insts[inst_num]->readPC(), 1139 fromIEW->insts[inst_num]->seqNum); 1140 1141 // Mark the instruction as ready to commit. 1142 fromIEW->insts[inst_num]->setCanCommit(); 1143 } 1144 } 1145} 1146 1147template <class Impl> 1148bool 1149DefaultCommit<Impl>::robDoneSquashing() 1150{ 1151 list<unsigned>::iterator threads = (*activeThreads).begin(); 1152 1153 while (threads != (*activeThreads).end()) { 1154 unsigned tid = *threads++; 1155 1156 if (!rob->isDoneSquashing(tid)) 1157 return false; 1158 } 1159 1160 return true; 1161} 1162 1163template <class Impl> 1164void 1165DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1166{ 1167 unsigned thread = inst->threadNumber; 1168 1169 // 1170 // Pick off the software prefetches 1171 // 1172#ifdef TARGET_ALPHA 1173 if (inst->isDataPrefetch()) { 1174 statComSwp[thread]++; 1175 } else { 1176 statComInst[thread]++; 1177 } 1178#else 1179 statComInst[thread]++; 1180#endif 1181 1182 // 1183 // Control Instructions 1184 // 1185 if (inst->isControl()) 1186 statComBranches[thread]++; 1187 1188 // 1189 // Memory references 1190 // 1191 if (inst->isMemRef()) { 1192 statComRefs[thread]++; 1193 1194 if (inst->isLoad()) { 1195 statComLoads[thread]++; 1196 } 1197 } 1198 1199 if (inst->isMemBarrier()) { 1200 statComMembars[thread]++; 1201 } 1202} 1203 1204//////////////////////////////////////// 1205// // 1206// SMT COMMIT POLICY MAINTAINED HERE // 1207// // 1208//////////////////////////////////////// 1209template <class Impl> 1210int 1211DefaultCommit<Impl>::getCommittingThread() 1212{ 1213 if (numThreads > 1) { 1214 switch (commitPolicy) { 1215 1216 case Aggressive: 1217 //If Policy is Aggressive, commit will call 1218 //this function multiple times per 1219 //cycle 1220 return oldestReady(); 1221 1222 case RoundRobin: 1223 return roundRobin(); 1224 1225 case OldestReady: 1226 return oldestReady(); 1227 1228 default: 1229 return -1; 1230 } 1231 } else { 1232 int tid = (*activeThreads).front(); 1233 1234 if (commitStatus[tid] == Running || 1235 commitStatus[tid] == Idle || 1236 commitStatus[tid] == FetchTrapPending) { 1237 return tid; 1238 } else { 1239 return -1; 1240 } 1241 } 1242} 1243 1244template<class Impl> 1245int 1246DefaultCommit<Impl>::roundRobin() 1247{ 1248 list<unsigned>::iterator pri_iter = priority_list.begin(); 1249 list<unsigned>::iterator end = priority_list.end(); 1250 1251 while (pri_iter != end) { 1252 unsigned tid = *pri_iter; 1253 1254 if (commitStatus[tid] == Running || 1255 commitStatus[tid] == Idle) { 1256 1257 if (rob->isHeadReady(tid)) { 1258 priority_list.erase(pri_iter); 1259 priority_list.push_back(tid); 1260 1261 return tid; 1262 } 1263 } 1264 1265 pri_iter++; 1266 } 1267 1268 return -1; 1269} 1270 1271template<class Impl> 1272int 1273DefaultCommit<Impl>::oldestReady() 1274{ 1275 unsigned oldest = 0; 1276 bool first = true; 1277 1278 list<unsigned>::iterator threads = (*activeThreads).begin(); 1279 1280 while (threads != (*activeThreads).end()) { 1281 unsigned tid = *threads++; 1282 1283 if (!rob->isEmpty(tid) && 1284 (commitStatus[tid] == Running || 1285 commitStatus[tid] == Idle || 1286 commitStatus[tid] == FetchTrapPending)) { 1287 1288 if (rob->isHeadReady(tid)) { 1289 1290 DynInstPtr head_inst = rob->readHeadInst(tid); 1291 1292 if (first) { 1293 oldest = tid; 1294 first = false; 1295 } else if (head_inst->seqNum < oldest) { 1296 oldest = tid; 1297 } 1298 } 1299 } 1300 } 1301 1302 if (!first) { 1303 return oldest; 1304 } else { 1305 return -1; 1306 } 1307} 1308