commit_impl.hh revision 13449:2f7efa89c58b
11689SN/A/* 22329SN/A * Copyright 2014 Google, Inc. 31689SN/A * Copyright (c) 2010-2014, 2017 ARM Limited 41689SN/A * All rights reserved 51689SN/A * 61689SN/A * The license below extends only to copyright in the software and shall 71689SN/A * not be construed as granting a license to any other intellectual 81689SN/A * property including but not limited to intellectual property relating 91689SN/A * to a hardware implementation of the functionality of the software 101689SN/A * licensed hereunder. You may use the software subject to the license 111689SN/A * terms below provided that you ensure that this notice is replicated 121689SN/A * unmodified and in its entirety in all distributions of the software, 131689SN/A * modified or unmodified, in source code or in binary form. 141689SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292935Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341858SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351717SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391061SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402292SN/A * 412292SN/A * Authors: Kevin Lim 422292SN/A * Korey Sewell 432292SN/A */ 442292SN/A#ifndef __CPU_O3_COMMIT_IMPL_HH__ 452292SN/A#define __CPU_O3_COMMIT_IMPL_HH__ 462292SN/A 471060SN/A#include <algorithm> 482292SN/A#include <set> 492292SN/A#include <string> 502292SN/A 512292SN/A#include "arch/utility.hh" 522292SN/A#include "base/cp_annotate.hh" 532292SN/A#include "base/loader/symtab.hh" 542292SN/A#include "base/logging.hh" 552292SN/A#include "config/the_isa.hh" 562292SN/A#include "cpu/checker/cpu.hh" 572292SN/A#include "cpu/o3/commit.hh" 582292SN/A#include "cpu/o3/thread_state.hh" 592301SN/A#include "cpu/base.hh" 602292SN/A#include "cpu/exetrace.hh" 612292SN/A#include "cpu/timebuf.hh" 622292SN/A#include "debug/Activity.hh" 632292SN/A#include "debug/Commit.hh" 642292SN/A#include "debug/CommitRate.hh" 652292SN/A#include "debug/Drain.hh" 662292SN/A#include "debug/ExecFaulting.hh" 672292SN/A#include "debug/O3PipeView.hh" 682292SN/A#include "params/DerivO3CPU.hh" 692292SN/A#include "sim/faults.hh" 702292SN/A#include "sim/full_system.hh" 712292SN/A 722292SN/Ausing namespace std; 732292SN/A 742292SN/Atemplate <class Impl> 752292SN/Avoid 762292SN/ADefaultCommit<Impl>::processTrapEvent(ThreadID tid) 771060SN/A{ 781060SN/A // This will get reset by commit if it was switched out at the 791061SN/A // time of this event processing. 801060SN/A trapSquash[tid] = true; 812292SN/A} 821062SN/A 831062SN/Atemplate <class Impl> 842301SN/ADefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 851062SN/A : cpu(_cpu), 861062SN/A iewToCommitDelay(params->iewToCommitDelay), 871062SN/A commitToIEWDelay(params->commitToIEWDelay), 882301SN/A renameToROBDelay(params->renameToROBDelay), 891062SN/A fetchToCommitDelay(params->commitToFetchDelay), 901062SN/A renameWidth(params->renameWidth), 911062SN/A commitWidth(params->commitWidth), 922301SN/A numThreads(params->numThreads), 931062SN/A drainPending(false), 941062SN/A drainImminent(false), 952301SN/A trapLatency(params->trapLatency), 962301SN/A canHandleInterrupts(true), 972301SN/A avoidQuiesceLiveLock(false) 982301SN/A{ 992292SN/A if (commitWidth > Impl::MaxWidth) 1002301SN/A fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 1012292SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 1022292SN/A commitWidth, static_cast<int>(Impl::MaxWidth)); 1031062SN/A 1042301SN/A _status = Active; 1051062SN/A _nextStatus = Inactive; 1061062SN/A std::string policy = params->smtCommitPolicy; 1071062SN/A 1082301SN/A //Convert string to lowercase 1091062SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1101062SN/A (int(*)(int)) tolower); 1111062SN/A 1122301SN/A //Assign commit policy 1131062SN/A if (policy == "aggressive"){ 1141062SN/A commitPolicy = Aggressive; 1151062SN/A 1162301SN/A DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 1172292SN/A } else if (policy == "roundrobin"){ 1181062SN/A commitPolicy = RoundRobin; 1191062SN/A 1202301SN/A //Set-Up Priority List 1212292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1221062SN/A priority_list.push_back(tid); 1232292SN/A } 1242301SN/A 1252292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 1262292SN/A } else if (policy == "oldestready"){ 1271062SN/A commitPolicy = OldestReady; 1282301SN/A 1291062SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1301062SN/A } else { 1311062SN/A panic("Invalid SMT commit policy. Options are: Aggressive, " 1322301SN/A "RoundRobin, OldestReady"); 1331062SN/A } 1341062SN/A 1351062SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1362301SN/A commitStatus[tid] = Idle; 1371062SN/A changedROBNumEntries[tid] = false; 1381062SN/A checkEmptyROB[tid] = false; 1391062SN/A trapInFlight[tid] = false; 1402301SN/A committedStores[tid] = false; 1411062SN/A trapSquash[tid] = false; 1421062SN/A tcSquash[tid] = false; 1431062SN/A pc[tid].set(0); 1442301SN/A lastCommitedSeqNum[tid] = 0; 1451062SN/A squashAfterInst[tid] = NULL; 1461062SN/A } 1472301SN/A interrupt = NoFault; 1482301SN/A} 1492301SN/A 1502301SN/Atemplate <class Impl> 1512301SN/Astd::string 1522301SN/ADefaultCommit<Impl>::name() const 1532301SN/A{ 1542301SN/A return cpu->name() + ".commit"; 1552301SN/A} 1562301SN/A 1572307SN/Atemplate <class Impl> 1582307SN/Avoid 1592307SN/ADefaultCommit<Impl>::regProbePoints() 1602307SN/A{ 1612307SN/A ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 1621062SN/A ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 1631062SN/A ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash"); 1641062SN/A} 1651062SN/A 1662733Sktlim@umich.edutemplate <class Impl> 1671060SN/Avoid 1682292SN/ADefaultCommit<Impl>::regStats() 1691060SN/A{ 1701060SN/A using namespace Stats; 1711060SN/A commitSquashedInsts 1721061SN/A .name(name() + ".commitSquashedInsts") 1731060SN/A .desc("The number of squashed insts skipped by commit") 1742292SN/A .prereq(commitSquashedInsts); 1751060SN/A 1762292SN/A commitNonSpecStalls 1771060SN/A .name(name() + ".commitNonSpecStalls") 1781060SN/A .desc("The number of times commit has been forced to stall to " 1791060SN/A "communicate backwards") 1801060SN/A .prereq(commitNonSpecStalls); 1811060SN/A 1821060SN/A branchMispredicts 1831060SN/A .name(name() + ".branchMispredicts") 1841060SN/A .desc("The number of times a branch was mispredicted") 1851060SN/A .prereq(branchMispredicts); 1861060SN/A 1871060SN/A numCommittedDist 1881060SN/A .init(0,commitWidth,1) 1891061SN/A .name(name() + ".committed_per_cycle") 1901060SN/A .desc("Number of insts commited each cycle") 1912292SN/A .flags(Stats::pdf) 1921060SN/A ; 1932292SN/A 1941060SN/A instsCommitted 1951060SN/A .init(cpu->numThreads) 1961060SN/A .name(name() + ".committedInsts") 1971060SN/A .desc("Number of instructions committed") 1981060SN/A .flags(total) 1991060SN/A ; 2001061SN/A 2011060SN/A opsCommitted 2022292SN/A .init(cpu->numThreads) 2031060SN/A .name(name() + ".committedOps") 2042292SN/A .desc("Number of ops (including micro ops) committed") 2051060SN/A .flags(total) 2061060SN/A ; 2071060SN/A 2081060SN/A statComSwp 2091060SN/A .init(cpu->numThreads) 2101060SN/A .name(name() + ".swp_count") 2111061SN/A .desc("Number of s/w prefetches committed") 2121060SN/A .flags(total) 2132292SN/A ; 2141060SN/A 2152329SN/A statComRefs 2162292SN/A .init(cpu->numThreads) 2172292SN/A .name(name() + ".refs") 2182292SN/A .desc("Number of memory references committed") 2192292SN/A .flags(total) 2202292SN/A ; 2212292SN/A 2221060SN/A statComLoads 2231060SN/A .init(cpu->numThreads) 2242292SN/A .name(name() + ".loads") 2252292SN/A .desc("Number of loads committed") 2262292SN/A .flags(total) 2272292SN/A ; 2282292SN/A 2292292SN/A statComMembars 2302292SN/A .init(cpu->numThreads) 2312292SN/A .name(name() + ".membars") 2322292SN/A .desc("Number of memory barriers committed") 2331061SN/A .flags(total) 2341060SN/A ; 2352292SN/A 2361060SN/A statComBranches 2372292SN/A .init(cpu->numThreads) 2381060SN/A .name(name() + ".branches") 2392292SN/A .desc("Number of branches committed") 2402292SN/A .flags(total) 2411060SN/A ; 2421060SN/A 2431060SN/A statComFloating 2441061SN/A .init(cpu->numThreads) 2451060SN/A .name(name() + ".fp_insts") 2462292SN/A .desc("Number of committed floating point instructions.") 2471060SN/A .flags(total) 2482292SN/A ; 2492292SN/A 2502292SN/A statComVector 2511060SN/A .init(cpu->numThreads) 2522292SN/A .name(name() + ".vec_insts") 2532292SN/A .desc("Number of committed Vector instructions.") 2542292SN/A .flags(total) 2552292SN/A ; 2562292SN/A 2572292SN/A statComInteger 2581060SN/A .init(cpu->numThreads) 2591060SN/A .name(name()+".int_insts") 2601061SN/A .desc("Number of committed integer instructions.") 2612863Sktlim@umich.edu .flags(total) 2622843Sktlim@umich.edu ; 2631060SN/A 2642348SN/A statComFunctionCalls 2652843Sktlim@umich.edu .init(cpu->numThreads) 2662863Sktlim@umich.edu .name(name()+".function_calls") 2672316SN/A .desc("Number of function calls committed.") 2681060SN/A .flags(total) 2692316SN/A ; 2702316SN/A 2712843Sktlim@umich.edu statCommittedInstType 2722316SN/A .init(numThreads,Enums::Num_OpClass) 2732348SN/A .name(name() + ".op_class") 2742307SN/A .desc("Class of committed instruction") 2752307SN/A .flags(total | pdf | dist) 2762307SN/A ; 2772307SN/A statCommittedInstType.ysubnames(Enums::OpClassStrings); 2782307SN/A 2792307SN/A commitEligibleSamples 2802307SN/A .name(name() + ".bw_lim_events") 2812307SN/A .desc("number cycles where commit BW limit reached") 2822307SN/A ; 2832307SN/A} 2842307SN/A 2852307SN/Atemplate <class Impl> 2862307SN/Avoid 2872307SN/ADefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2882307SN/A{ 2892307SN/A thread = threads; 2902307SN/A} 2912307SN/A 2922307SN/Atemplate <class Impl> 2932307SN/Avoid 2941060SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2951060SN/A{ 2961060SN/A timeBuffer = tb_ptr; 2971061SN/A 2981060SN/A // Setup wire to send information back to IEW. 2992307SN/A toIEW = timeBuffer->getWire(0); 3001060SN/A 3012307SN/A // Setup wire to read data from IEW (for the ROB). 3022307SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 3031060SN/A} 3042329SN/A 3052307SN/Atemplate <class Impl> 3062307SN/Avoid 3071060SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 3082307SN/A{ 3092307SN/A fetchQueue = fq_ptr; 3102307SN/A 3112307SN/A // Setup wire to get instructions from rename (for the ROB). 3122307SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3132307SN/A} 3142307SN/A 3152307SN/Atemplate <class Impl> 3162307SN/Avoid 3172307SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3182307SN/A{ 3192307SN/A renameQueue = rq_ptr; 3202307SN/A 3212307SN/A // Setup wire to get instructions from rename (for the ROB). 3222935Sksewell@umich.edu fromRename = renameQueue->getWire(-renameToROBDelay); 3231858SN/A} 3242292SN/A 3251858SN/Atemplate <class Impl> 3262292SN/Avoid 3272292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3282292SN/A{ 3292292SN/A iewQueue = iq_ptr; 3302292SN/A 3312301SN/A // Setup wire to get instructions from IEW. 3322698Sktlim@umich.edu fromIEW = iewQueue->getWire(-iewToCommitDelay); 3332292SN/A} 3342698Sktlim@umich.edu 3352301SN/Atemplate <class Impl> 3362292SN/Avoid 3372292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3382292SN/A{ 3392292SN/A iewStage = iew_stage; 3402292SN/A} 3412329SN/A 3422292SN/Atemplate<class Impl> 3432292SN/Avoid 3442292SN/ADefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3452935Sksewell@umich.edu{ 3462935Sksewell@umich.edu activeThreads = at_ptr; 3472731Sktlim@umich.edu} 3482292SN/A 3492292SN/Atemplate <class Impl> 3502292SN/Avoid 3512935Sksewell@umich.eduDefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3522292SN/A{ 3532292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 3542935Sksewell@umich.edu renameMap[tid] = &rm_ptr[tid]; 3552935Sksewell@umich.edu} 3562935Sksewell@umich.edu 3572935Sksewell@umich.edutemplate <class Impl> 3582935Sksewell@umich.eduvoid 3592935Sksewell@umich.eduDefaultCommit<Impl>::setROB(ROB *rob_ptr) 3602292SN/A{ 3612935Sksewell@umich.edu rob = rob_ptr; 3622935Sksewell@umich.edu} 3632935Sksewell@umich.edu 3642935Sksewell@umich.edutemplate <class Impl> 3652935Sksewell@umich.eduvoid 3662935Sksewell@umich.eduDefaultCommit<Impl>::startupStage() 3672935Sksewell@umich.edu{ 3682935Sksewell@umich.edu rob->setActiveThreads(activeThreads); 3692935Sksewell@umich.edu rob->resetEntries(); 3702935Sksewell@umich.edu 3712935Sksewell@umich.edu // Broadcast the number of free entries. 3722935Sksewell@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 3732935Sksewell@umich.edu toIEW->commitInfo[tid].usedROB = true; 3742292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3752292SN/A toIEW->commitInfo[tid].emptyROB = true; 3762935Sksewell@umich.edu } 3772935Sksewell@umich.edu 3782935Sksewell@umich.edu // Commit must broadcast the number of free entries it has at the 3792292SN/A // start of the simulation, so it starts as active. 3802935Sksewell@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3812935Sksewell@umich.edu 3822935Sksewell@umich.edu cpu->activityThisCycle(); 3832935Sksewell@umich.edu} 3842935Sksewell@umich.edu 3852935Sksewell@umich.edutemplate <class Impl> 3862935Sksewell@umich.eduvoid 3872935Sksewell@umich.eduDefaultCommit<Impl>::drain() 3882935Sksewell@umich.edu{ 3892935Sksewell@umich.edu drainPending = true; 3902935Sksewell@umich.edu} 3912935Sksewell@umich.edu 3922935Sksewell@umich.edutemplate <class Impl> 3932935Sksewell@umich.eduvoid 3942292SN/ADefaultCommit<Impl>::drainResume() 3952292SN/A{ 3962292SN/A drainPending = false; 3972292SN/A drainImminent = false; 3982292SN/A} 3992292SN/A 4002292SN/Atemplate <class Impl> 4012292SN/Avoid 4022292SN/ADefaultCommit<Impl>::drainSanityCheck() const 4032292SN/A{ 4042292SN/A assert(isDrained()); 4052292SN/A rob->drainSanityCheck(); 4062292SN/A} 4072292SN/A 4082292SN/Atemplate <class Impl> 4092292SN/Abool 4102292SN/ADefaultCommit<Impl>::isDrained() const 4112292SN/A{ 4122292SN/A /* Make sure no one is executing microcode. There are two reasons 4132292SN/A * for this: 4142292SN/A * - Hardware virtualized CPUs can't switch into the middle of a 4152292SN/A * microcode sequence. 4162292SN/A * - The current fetch implementation will most likely get very 4172292SN/A * confused if it tries to start fetching an instruction that 4182292SN/A * is executing in the middle of a ucode sequence that changes 4192292SN/A * address mappings. This can happen on for example x86. 4202292SN/A */ 4212292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4222292SN/A if (pc[tid].microPC() != 0) 4232292SN/A return false; 4242292SN/A } 4252292SN/A 4262292SN/A /* Make sure that all instructions have finished committing before 4272292SN/A * declaring the system as drained. We want the pipeline to be 4282292SN/A * completely empty when we declare the CPU to be drained. This 4292292SN/A * makes debugging easier since CPU handover and restoring from a 4302292SN/A * checkpoint with a different CPU should have the same timing. 4312292SN/A */ 4322292SN/A return rob->isEmpty() && 4332292SN/A interrupt == NoFault; 4342292SN/A} 4352292SN/A 4362292SN/Atemplate <class Impl> 4372292SN/Avoid 4382292SN/ADefaultCommit<Impl>::takeOverFrom() 4392292SN/A{ 4402292SN/A _status = Active; 4412292SN/A _nextStatus = Inactive; 4422292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4432292SN/A commitStatus[tid] = Idle; 4442292SN/A changedROBNumEntries[tid] = false; 4452292SN/A trapSquash[tid] = false; 4462292SN/A tcSquash[tid] = false; 4472292SN/A squashAfterInst[tid] = NULL; 4482292SN/A } 4492292SN/A rob->takeOverFrom(); 4502292SN/A} 4512292SN/A 4522292SN/Atemplate <class Impl> 4532292SN/Avoid 4542292SN/ADefaultCommit<Impl>::deactivateThread(ThreadID tid) 4552292SN/A{ 4562292SN/A list<ThreadID>::iterator thread_it = std::find(priority_list.begin(), 4572292SN/A priority_list.end(), tid); 4582292SN/A 4592292SN/A if (thread_it != priority_list.end()) { 4602292SN/A priority_list.erase(thread_it); 4612292SN/A } 4622292SN/A} 4632292SN/A 4642292SN/A 4652292SN/Atemplate <class Impl> 4662292SN/Avoid 4672292SN/ADefaultCommit<Impl>::updateStatus() 4682292SN/A{ 4692292SN/A // reset ROB changed variable 4702292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 4712301SN/A list<ThreadID>::iterator end = activeThreads->end(); 4722301SN/A 4732292SN/A while (threads != end) { 4742292SN/A ThreadID tid = *threads++; 4752292SN/A 4762292SN/A changedROBNumEntries[tid] = false; 4772292SN/A 4782292SN/A // Also check if any of the threads has a trap pending 4792292SN/A if (commitStatus[tid] == TrapPending || 4802292SN/A commitStatus[tid] == FetchTrapPending) { 4812292SN/A _nextStatus = Active; 4822292SN/A } 4832292SN/A } 4842292SN/A 4852292SN/A if (_nextStatus == Inactive && _status == Active) { 4862292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4872292SN/A cpu->deactivateStage(O3CPU::CommitIdx); 4882292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4892292SN/A DPRINTF(Activity, "Activating stage.\n"); 4902292SN/A cpu->activateStage(O3CPU::CommitIdx); 4912292SN/A } 4922292SN/A 4931858SN/A _status = _nextStatus; 4941858SN/A} 4951858SN/A 4961858SN/Atemplate <class Impl> 4971858SN/Abool 4982292SN/ADefaultCommit<Impl>::changedROBEntries() 4991858SN/A{ 5002292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 5012292SN/A list<ThreadID>::iterator end = activeThreads->end(); 5022292SN/A 5032292SN/A while (threads != end) { 5041858SN/A ThreadID tid = *threads++; 5052292SN/A 5062292SN/A if (changedROBNumEntries[tid]) { 5072292SN/A return true; 5082292SN/A } 5092292SN/A } 5102292SN/A 5112292SN/A return false; 5122292SN/A} 5132292SN/A 5142292SN/Atemplate <class Impl> 5152292SN/Asize_t 5162292SN/ADefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 5172292SN/A{ 5181858SN/A return rob->numFreeEntries(tid); 5192292SN/A} 5202292SN/A 5212292SN/Atemplate <class Impl> 5222292SN/Avoid 5232292SN/ADefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault) 5242292SN/A{ 5252292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5262292SN/A 5272292SN/A EventFunctionWrapper *trap = new EventFunctionWrapper( 5282292SN/A [this, tid]{ processTrapEvent(tid); }, 5292292SN/A "Trap", true, Event::CPU_Tick_Pri); 5302292SN/A 5312292SN/A Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ? 5322292SN/A cpu->syscallRetryLatency : trapLatency; 5332292SN/A 5342292SN/A cpu->schedule(trap, cpu->clockEdge(latency)); 5352292SN/A trapInFlight[tid] = true; 5362292SN/A thread[tid]->trapPending = true; 5372292SN/A} 5382292SN/A 5392292SN/Atemplate <class Impl> 5402292SN/Avoid 5412292SN/ADefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5422292SN/A{ 5432292SN/A assert(!trapInFlight[tid]); 5442292SN/A DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5452292SN/A 5462292SN/A tcSquash[tid] = true; 5472292SN/A} 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Avoid 5512292SN/ADefaultCommit<Impl>::squashAll(ThreadID tid) 5522292SN/A{ 5532292SN/A // If we want to include the squashing instruction in the squash, 5542292SN/A // then use one older sequence number. 5552292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5562292SN/A // all instructions of this thread. 5572292SN/A InstSeqNum squashed_inst = rob->isEmpty(tid) ? 5582292SN/A lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5592292SN/A 5602292SN/A // All younger instructions will be squashed. Set the sequence 5612292SN/A // number as the youngest instruction in the ROB (0 in this case. 5622292SN/A // Hopefully nothing breaks.) 5632292SN/A youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5642292SN/A 5652292SN/A rob->squash(squashed_inst, tid); 5662292SN/A changedROBNumEntries[tid] = true; 5672292SN/A 5682292SN/A // Send back the sequence number of the squashed instruction. 5692292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5702292SN/A 5712292SN/A // Send back the squash signal to tell stages that they should 5722292SN/A // squash. 5732292SN/A toIEW->commitInfo[tid].squash = true; 5742292SN/A 5752292SN/A // Send back the rob squashing signal so other stages know that 5762292SN/A // the ROB is in the process of squashing. 5772292SN/A toIEW->commitInfo[tid].robSquashing = true; 5782292SN/A 5792292SN/A toIEW->commitInfo[tid].mispredictInst = NULL; 5802292SN/A toIEW->commitInfo[tid].squashInst = NULL; 5812292SN/A 5822292SN/A toIEW->commitInfo[tid].pc = pc[tid]; 5832292SN/A} 5842292SN/A 5852292SN/Atemplate <class Impl> 5862292SN/Avoid 5872292SN/ADefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5882292SN/A{ 5892292SN/A squashAll(tid); 5902292SN/A 5912292SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5922292SN/A 5932292SN/A thread[tid]->trapPending = false; 5942292SN/A thread[tid]->noSquashFromTC = false; 5952292SN/A trapInFlight[tid] = false; 5962292SN/A 5972292SN/A trapSquash[tid] = false; 5982292SN/A 5992292SN/A commitStatus[tid] = ROBSquashing; 6002292SN/A cpu->activityThisCycle(); 6012292SN/A} 6022292SN/A 6032292SN/Atemplate <class Impl> 6042292SN/Avoid 6052292SN/ADefaultCommit<Impl>::squashFromTC(ThreadID tid) 6062292SN/A{ 6072292SN/A squashAll(tid); 6082292SN/A 6092292SN/A DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 6102292SN/A 6112292SN/A thread[tid]->noSquashFromTC = false; 6122935Sksewell@umich.edu assert(!thread[tid]->trapPending); 6132292SN/A 6142292SN/A commitStatus[tid] = ROBSquashing; 6152292SN/A cpu->activityThisCycle(); 6162292SN/A 6172292SN/A tcSquash[tid] = false; 6182292SN/A} 6192292SN/A 6202292SN/Atemplate <class Impl> 6212292SN/Avoid 6222292SN/ADefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 6232292SN/A{ 6242292SN/A DPRINTF(Commit, "Squashing after squash after request, " 6252292SN/A "restarting at PC %s\n", pc[tid]); 6262292SN/A 6272292SN/A squashAll(tid); 6282292SN/A // Make sure to inform the fetch stage of which instruction caused 6292292SN/A // the squash. It'll try to re-fetch an instruction executing in 6302336SN/A // microcode unless this is set. 6312336SN/A toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 6322336SN/A squashAfterInst[tid] = NULL; 6332336SN/A 6342336SN/A commitStatus[tid] = ROBSquashing; 6352336SN/A cpu->activityThisCycle(); 6362336SN/A} 6372336SN/A 6382292SN/Atemplate <class Impl> 6392292SN/Avoid 6402301SN/ADefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst) 6412301SN/A{ 6422292SN/A DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6432301SN/A tid, head_inst->seqNum); 6442301SN/A 6452301SN/A assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 6462292SN/A commitStatus[tid] = SquashAfterPending; 6472301SN/A squashAfterInst[tid] = head_inst; 6482292SN/A} 6492301SN/A 6502292SN/Atemplate <class Impl> 6512301SN/Avoid 6522292SN/ADefaultCommit<Impl>::tick() 6532292SN/A{ 6542292SN/A wroteToTimeBuffer = false; 6552292SN/A _nextStatus = Inactive; 6562336SN/A 6572336SN/A if (activeThreads->empty()) 6582292SN/A return; 6592292SN/A 6602307SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6612307SN/A list<ThreadID>::iterator end = activeThreads->end(); 6622292SN/A 6632292SN/A // Check if any of the threads are done squashing. Change the 6642292SN/A // status if they are done. 6652292SN/A while (threads != end) { 6662292SN/A ThreadID tid = *threads++; 6672292SN/A 6682292SN/A // Clear the bit saying if the thread has committed stores 6692292SN/A // this cycle. 6702292SN/A committedStores[tid] = false; 6712292SN/A 6722292SN/A if (commitStatus[tid] == ROBSquashing) { 6732292SN/A 6742292SN/A if (rob->isDoneSquashing(tid)) { 6752292SN/A commitStatus[tid] = Running; 6762292SN/A } else { 6772292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6782292SN/A " insts this cycle.\n", tid); 6792292SN/A rob->doSquash(tid); 6802292SN/A toIEW->commitInfo[tid].robSquashing = true; 6812292SN/A wroteToTimeBuffer = true; 6822292SN/A } 6832292SN/A } 6842292SN/A } 6852292SN/A 6862292SN/A commit(); 6872292SN/A 6882292SN/A markCompletedInsts(); 6892292SN/A 6902292SN/A threads = activeThreads->begin(); 6912292SN/A 6922292SN/A while (threads != end) { 6932292SN/A ThreadID tid = *threads++; 6942292SN/A 6952292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6962292SN/A // The ROB has more instructions it can commit. Its next status 6972307SN/A // will be active. 6982292SN/A _nextStatus = Active; 6992292SN/A 7002292SN/A const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid); 7012292SN/A 7022292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 7032292SN/A " ROB and ready to commit\n", 7042292SN/A tid, inst->seqNum, inst->pcState()); 7052292SN/A 7062292SN/A } else if (!rob->isEmpty(tid)) { 7072292SN/A const DynInstPtr &inst = rob->readHeadInst(tid); 7082292SN/A 7092292SN/A ppCommitStall->notify(inst); 7102292SN/A 7112292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 7122292SN/A "%s is head of ROB and not ready\n", 7132292SN/A tid, inst->seqNum, inst->pcState()); 7142292SN/A } 7152292SN/A 7162292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 7172292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 7182292SN/A } 7192292SN/A 7202292SN/A 7212292SN/A if (wroteToTimeBuffer) { 7222292SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 7232292SN/A cpu->activityThisCycle(); 7242292SN/A } 7252292SN/A 7262292SN/A updateStatus(); 7272292SN/A} 7282292SN/A 7292292SN/Atemplate <class Impl> 7302292SN/Avoid 7312292SN/ADefaultCommit<Impl>::handleInterrupt() 7322307SN/A{ 7332307SN/A // Verify that we still have an interrupt to handle 7342292SN/A if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7352292SN/A DPRINTF(Commit, "Pending interrupt is cleared by master before " 7362292SN/A "it got handled. Restart fetching from the orig path.\n"); 7372292SN/A toIEW->commitInfo[0].clearInterrupt = true; 7382292SN/A interrupt = NoFault; 7392292SN/A avoidQuiesceLiveLock = true; 7402292SN/A return; 7412292SN/A } 7422292SN/A 7432292SN/A // Wait until all in flight instructions are finished before enterring 7442292SN/A // the interrupt. 7452292SN/A if (canHandleInterrupts && cpu->instList.empty()) { 7462329SN/A // Squash or record that I need to squash this cycle if 7472935Sksewell@umich.edu // an interrupt needed to be handled. 7482292SN/A DPRINTF(Commit, "Interrupt detected.\n"); 7492292SN/A 7502329SN/A // Clear the interrupt now that it's going to be handled 7512935Sksewell@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 7522292SN/A 7532292SN/A assert(!thread[0]->noSquashFromTC); 7542292SN/A thread[0]->noSquashFromTC = true; 7552292SN/A 7562292SN/A if (cpu->checker) { 7572292SN/A cpu->checker->handlePendingInt(); 7582292SN/A } 7592292SN/A 7602292SN/A // CPU will handle interrupt. Note that we ignore the local copy of 7612292SN/A // interrupt. This is because the local copy may no longer be the 7622292SN/A // interrupt that the interrupt controller thinks is being handled. 7632292SN/A cpu->processInterrupts(cpu->getInterrupts()); 7642292SN/A 7652292SN/A thread[0]->noSquashFromTC = false; 7662292SN/A 7672292SN/A commitStatus[0] = TrapPending; 7682292SN/A 7692292SN/A interrupt = NoFault; 7702292SN/A 7712292SN/A // Generate trap squash event. 7722292SN/A generateTrapEvent(0, interrupt); 7732292SN/A 7742292SN/A avoidQuiesceLiveLock = false; 7752292SN/A } else { 7762292SN/A DPRINTF(Commit, "Interrupt pending: instruction is %sin " 7772292SN/A "flight, ROB is %sempty\n", 7782292SN/A canHandleInterrupts ? "not " : "", 7792292SN/A cpu->instList.empty() ? "" : "not " ); 7802292SN/A } 7812292SN/A} 7822292SN/A 7832292SN/Atemplate <class Impl> 7842292SN/Avoid 7852292SN/ADefaultCommit<Impl>::propagateInterrupt() 7862292SN/A{ 7872292SN/A // Don't propagate intterupts if we are currently handling a trap or 7882292SN/A // in draining and the last observable instruction has been committed. 7892292SN/A if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 7902292SN/A tcSquash[0] || drainImminent) 7912292SN/A return; 7922292SN/A 7932292SN/A // Process interrupts if interrupts are enabled, not in PAL 7942292SN/A // mode, and no other traps or external squashes are currently 7952292SN/A // pending. 7962292SN/A // @todo: Allow other threads to handle interrupts. 7972292SN/A 7982733Sktlim@umich.edu // Get any interrupt that happened 7992292SN/A interrupt = cpu->getInterrupts(); 8002292SN/A 8012292SN/A // Tell fetch that there is an interrupt pending. This 8022292SN/A // will make fetch wait until it sees a non PAL-mode PC, 8032292SN/A // at which point it stops fetching instructions. 8042292SN/A if (interrupt != NoFault) 8052292SN/A toIEW->commitInfo[0].interruptPending = true; 8062292SN/A} 8072733Sktlim@umich.edu 8082292SN/Atemplate <class Impl> 8092292SN/Avoid 8102292SN/ADefaultCommit<Impl>::commit() 8112292SN/A{ 8122292SN/A if (FullSystem) { 8132292SN/A // Check if we have a interrupt and get read to handle it 8142292SN/A if (cpu->checkInterrupts(cpu->tcBase(0))) 8152292SN/A propagateInterrupt(); 8162292SN/A } 8172292SN/A 8182292SN/A //////////////////////////////////// 8192292SN/A // Check for any possible squashes, handle them first 8202292SN/A //////////////////////////////////// 8212292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 8222292SN/A list<ThreadID>::iterator end = activeThreads->end(); 8232292SN/A 8242292SN/A int num_squashing_threads = 0; 8252292SN/A 8262292SN/A while (threads != end) { 8272292SN/A ThreadID tid = *threads++; 8282292SN/A 8292292SN/A // Not sure which one takes priority. I think if we have 8302292SN/A // both, that's a bad sign. 8312329SN/A if (trapSquash[tid]) { 8322329SN/A assert(!tcSquash[tid]); 8332301SN/A squashFromTrap(tid); 8342292SN/A } else if (tcSquash[tid]) { 8352292SN/A assert(commitStatus[tid] != TrapPending); 8362292SN/A squashFromTC(tid); 8372292SN/A } else if (commitStatus[tid] == SquashAfterPending) { 8382292SN/A // A squash from the previous cycle of the commit stage (i.e., 8392292SN/A // commitInsts() called squashAfter) is pending. Squash the 8402292SN/A // thread now. 8412292SN/A squashFromSquashAfter(tid); 8422292SN/A } 8432292SN/A 8442292SN/A // Squashed sequence number must be older than youngest valid 8452292SN/A // instruction in the ROB. This prevents squashes from younger 8462292SN/A // instructions overriding squashes from older instructions. 8472292SN/A if (fromIEW->squash[tid] && 8482292SN/A commitStatus[tid] != TrapPending && 8492292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8502301SN/A 8512292SN/A if (fromIEW->mispredictInst[tid]) { 8522292SN/A DPRINTF(Commit, 8532292SN/A "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8542292SN/A tid, 8552292SN/A fromIEW->mispredictInst[tid]->instAddr(), 8562292SN/A fromIEW->squashedSeqNum[tid]); 8572292SN/A } else { 8582292SN/A DPRINTF(Commit, 8592292SN/A "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8602292SN/A tid, fromIEW->squashedSeqNum[tid]); 8612292SN/A } 8622292SN/A 8632292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8642292SN/A tid, 8652292SN/A fromIEW->pc[tid].nextInstAddr()); 8662935Sksewell@umich.edu 8672292SN/A commitStatus[tid] = ROBSquashing; 8682292SN/A 8692292SN/A // If we want to include the squashing instruction in the squash, 8701060SN/A // then use one older sequence number. 8711060SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8722292SN/A 8731060SN/A if (fromIEW->includeSquashInst[tid]) { 8741060SN/A squashed_inst--; 8751060SN/A } 8761060SN/A 8771060SN/A // All younger instructions will be squashed. Set the sequence 8782292SN/A // number as the youngest instruction in the ROB. 8792292SN/A youngestSeqNum[tid] = squashed_inst; 8802292SN/A 8811062SN/A rob->squash(squashed_inst, tid); 8822292SN/A changedROBNumEntries[tid] = true; 8832292SN/A 8841060SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8852292SN/A 8862292SN/A toIEW->commitInfo[tid].squash = true; 8872292SN/A 8881060SN/A // Send back the rob squashing signal so other stages know that 8892292SN/A // the ROB is in the process of squashing. 8902292SN/A toIEW->commitInfo[tid].robSquashing = true; 8911062SN/A 8922292SN/A toIEW->commitInfo[tid].mispredictInst = 8931061SN/A fromIEW->mispredictInst[tid]; 8941062SN/A toIEW->commitInfo[tid].branchTaken = 8951060SN/A fromIEW->branchTaken[tid]; 8961060SN/A toIEW->commitInfo[tid].squashInst = 8971060SN/A rob->findInst(tid, squashed_inst); 8981060SN/A if (toIEW->commitInfo[tid].mispredictInst) { 8991060SN/A if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 9002292SN/A toIEW->commitInfo[tid].branchTaken = true; 9011060SN/A } 9022292SN/A ++branchMispredicts; 9032292SN/A } 9042292SN/A 9052292SN/A toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 9062292SN/A } 9071060SN/A 9081061SN/A if (commitStatus[tid] == ROBSquashing) { 9091060SN/A num_squashing_threads++; 9102292SN/A } 9112292SN/A } 9122292SN/A 9132292SN/A // If commit is currently squashing, then it will have activity for the 9142292SN/A // next cycle. Set its next status as active. 9152292SN/A if (num_squashing_threads) { 9161060SN/A _nextStatus = Active; 9171060SN/A } 9181060SN/A 9192292SN/A if (num_squashing_threads != numThreads) { 9202292SN/A // If we're not currently squashing, then get instructions. 9212292SN/A getInsts(); 9222292SN/A 9232292SN/A // Try to commit any instructions. 9242292SN/A commitInsts(); 9252292SN/A } 9261060SN/A 9272329SN/A //Check for any activity 9282329SN/A threads = activeThreads->begin(); 9292292SN/A 9301061SN/A while (threads != end) { 9312292SN/A ThreadID tid = *threads++; 9322292SN/A 9331061SN/A if (changedROBNumEntries[tid]) { 9342292SN/A toIEW->commitInfo[tid].usedROB = true; 9351060SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9361060SN/A 9371060SN/A wroteToTimeBuffer = true; 9381061SN/A changedROBNumEntries[tid] = false; 9391061SN/A if (rob->isEmpty(tid)) 9402292SN/A checkEmptyROB[tid] = true; 9411061SN/A } 9422292SN/A 9432292SN/A // ROB is only considered "empty" for previous stages if: a) 9441061SN/A // ROB is empty, b) there are no outstanding stores, c) IEW 9451061SN/A // stage has received any information regarding stores that 9461061SN/A // committed. 9471061SN/A // c) is checked by making sure to not consider the ROB empty 9481061SN/A // on the same cycle as when stores have been committed. 9492292SN/A // @todo: Make this handle multi-cycle communication between 9501061SN/A // commit and IEW. 9511061SN/A if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9521061SN/A !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9531061SN/A checkEmptyROB[tid] = false; 9542292SN/A toIEW->commitInfo[tid].usedROB = true; 9551061SN/A toIEW->commitInfo[tid].emptyROB = true; 9562292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9572292SN/A wroteToTimeBuffer = true; 9582292SN/A } 9591061SN/A 9601061SN/A } 9611061SN/A} 9622292SN/A 9632292SN/Atemplate <class Impl> 9642292SN/Avoid 9651061SN/ADefaultCommit<Impl>::commitInsts() 9661061SN/A{ 9671061SN/A //////////////////////////////////// 9681062SN/A // Handle commit 9691062SN/A // Note that commit will be handled prior to putting new 9701061SN/A // instructions in the ROB so that the ROB only tries to commit 9711061SN/A // instructions it has in this current cycle, and not instructions 9721061SN/A // it is writing in during this cycle. Can't commit and squash 9731061SN/A // things at the same time... 9741061SN/A //////////////////////////////////// 9752292SN/A 9761061SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9772292SN/A 9781061SN/A unsigned num_committed = 0; 9791061SN/A 9801061SN/A DynInstPtr head_inst; 9812292SN/A 9822292SN/A // Commit as many instructions as possible until the commit bandwidth 9832292SN/A // limit is reached, or it becomes impossible to commit any more. 9841061SN/A while (num_committed < commitWidth) { 9852292SN/A // Check for any interrupt that we've already squashed for 9862292SN/A // and start processing it. 9872292SN/A if (interrupt != NoFault) 9881061SN/A handleInterrupt(); 9892292SN/A 9902292SN/A ThreadID commit_thread = getCommittingThread(); 9911062SN/A 9922292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9932292SN/A break; 9942292SN/A 9951062SN/A head_inst = rob->readHeadInst(commit_thread); 9962292SN/A 9972292SN/A ThreadID tid = head_inst->threadNumber; 9982292SN/A 9992292SN/A assert(tid == commit_thread); 10001062SN/A 10012292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 10021062SN/A head_inst->seqNum, tid); 10032935Sksewell@umich.edu 10042935Sksewell@umich.edu // If the head instruction is squashed, it is ready to retire 10052935Sksewell@umich.edu // (be removed from the ROB) at any time. 10062292SN/A if (head_inst->isSquashed()) { 10071062SN/A 10082292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 10092292SN/A "ROB.\n"); 10102292SN/A 10112292SN/A rob->retireHead(commit_thread); 10122292SN/A 10132292SN/A ++commitSquashedInsts; 10142292SN/A // Notify potential listeners that this instruction is squashed 10152292SN/A ppSquash->notify(head_inst); 10161062SN/A 10172292SN/A // Record that the number of ROB entries has changed. 10181061SN/A changedROBNumEntries[tid] = true; 10191061SN/A } else { 10201061SN/A pc[tid] = head_inst->pcState(); 10211061SN/A 10221061SN/A // Increment the total number of non-speculative instructions 10232292SN/A // executed. 10241061SN/A // Hack for now: it really shouldn't happen until after the 10252292SN/A // commit is deemed to be successful, but this count is needed 10262292SN/A // for syscalls. 10272292SN/A thread[tid]->funcExeInst++; 10282292SN/A 10292292SN/A // Try to commit the head instruction. 10302292SN/A bool commit_success = commitHead(head_inst, num_committed); 10311061SN/A 10321061SN/A if (commit_success) { 10331061SN/A ++num_committed; 10341061SN/A statCommittedInstType[tid][head_inst->opClass()]++; 10352292SN/A ppCommit->notify(head_inst); 10361061SN/A 10372292SN/A changedROBNumEntries[tid] = true; 10382292SN/A 10392292SN/A // Set the doneSeqNum to the youngest committed instruction. 10402292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 10412292SN/A 10422292SN/A if (tid == 0) { 10432292SN/A canHandleInterrupts = (!head_inst->isDelayedCommit()) && 10442292SN/A ((THE_ISA != ALPHA_ISA) || 10452292SN/A (!(pc[0].instAddr() & 0x3))); 10462292SN/A } 10472292SN/A 10482292SN/A // at this point store conditionals should either have 10492292SN/A // been completed or predicated false 10502292SN/A assert(!head_inst->isStoreConditional() || 10512292SN/A head_inst->isCompleted() || 10522292SN/A !head_inst->readPredicate()); 10532292SN/A 10542292SN/A // Updates misc. registers. 10552292SN/A head_inst->updateMiscRegs(); 10562292SN/A 10572292SN/A // Check instruction execution if it successfully commits and 10582292SN/A // is not carrying a fault. 10592292SN/A if (cpu->checker) { 10602292SN/A cpu->checker->verify(head_inst); 10612292SN/A } 10622292SN/A 10632292SN/A cpu->traceFunctions(pc[tid].instAddr()); 10642731Sktlim@umich.edu 10652292SN/A TheISA::advancePC(pc[tid], head_inst->staticInst); 10662292SN/A 10672292SN/A // Keep track of the last sequence number commited 10682292SN/A lastCommitedSeqNum[tid] = head_inst->seqNum; 10692292SN/A 10702292SN/A // If this is an instruction that doesn't play nicely with 10712292SN/A // others squash everything and restart fetch 10722292SN/A if (head_inst->isSquashAfter()) 10732292SN/A squashAfter(tid, head_inst); 10742292SN/A 10752292SN/A if (drainPending) { 10762292SN/A if (pc[tid].microPC() == 0 && interrupt == NoFault && 10772292SN/A !thread[tid]->trapPending) { 10782292SN/A // Last architectually committed instruction. 10792292SN/A // Squash the pipeline, stall fetch, and use 10802292SN/A // drainImminent to disable interrupts 10812292SN/A DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 10822292SN/A squashAfter(tid, head_inst); 10832292SN/A cpu->commitDrained(tid); 10842292SN/A drainImminent = true; 10852292SN/A } 10862292SN/A } 10872292SN/A 10882292SN/A bool onInstBoundary = !head_inst->isMicroop() || 10892292SN/A head_inst->isLastMicroop() || 10902292SN/A !head_inst->isDelayedCommit(); 10912292SN/A 10922292SN/A if (onInstBoundary) { 10932292SN/A int count = 0; 10942292SN/A Addr oldpc; 10952292SN/A // Make sure we're not currently updating state while 10962292SN/A // handling PC events. 10972292SN/A assert(!thread[tid]->noSquashFromTC && 10982292SN/A !thread[tid]->trapPending); 10992292SN/A do { 11002292SN/A oldpc = pc[tid].instAddr(); 11012292SN/A cpu->system->pcEventQueue.service(thread[tid]->getTC()); 11022292SN/A count++; 11032292SN/A } while (oldpc != pc[tid].instAddr()); 11042292SN/A if (count > 1) { 11052292SN/A DPRINTF(Commit, 11062292SN/A "PC skip function event, stopping commit\n"); 11072292SN/A break; 11082292SN/A } 11092292SN/A } 11102292SN/A 11112292SN/A // Check if an instruction just enabled interrupts and we've 11122292SN/A // previously had an interrupt pending that was not handled 11132292SN/A // because interrupts were subsequently disabled before the 11142292SN/A // pipeline reached a place to handle the interrupt. In that 11152292SN/A // case squash now to make sure the interrupt is handled. 11162292SN/A // 11172292SN/A // If we don't do this, we might end up in a live lock situation 11182301SN/A if (!interrupt && avoidQuiesceLiveLock && 11192292SN/A onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0))) 11202301SN/A squashAfter(tid, head_inst); 11212292SN/A } else { 11222292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%s " 11232292SN/A "[tid:%i] [sn:%i].\n", 11242292SN/A head_inst->pcState(), tid ,head_inst->seqNum); 11252292SN/A break; 11262292SN/A } 11272292SN/A } 11282292SN/A } 11292292SN/A 11302292SN/A DPRINTF(CommitRate, "%i\n", num_committed); 11312292SN/A numCommittedDist.sample(num_committed); 11322292SN/A 11332292SN/A if (num_committed == commitWidth) { 11342292SN/A commitEligibleSamples++; 11352292SN/A } 11362292SN/A} 11372292SN/A 11382292SN/Atemplate <class Impl> 11392292SN/Abool 11402292SN/ADefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) 11412292SN/A{ 11422292SN/A assert(head_inst); 11432292SN/A 11442292SN/A ThreadID tid = head_inst->threadNumber; 11452292SN/A 11462292SN/A // If the instruction is not executed yet, then it will need extra 11472292SN/A // handling. Signal backwards that it should be executed. 11482292SN/A if (!head_inst->isExecuted()) { 11492292SN/A // Keep this number correct. We have not yet actually executed 11502292SN/A // and committed this instruction. 11512292SN/A thread[tid]->funcExeInst--; 11522292SN/A 11532292SN/A // Make sure we are only trying to commit un-executed instructions we 11542292SN/A // think are possible. 11552292SN/A assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 11562292SN/A || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 11572292SN/A (head_inst->isLoad() && head_inst->strictlyOrdered())); 11582292SN/A 11592292SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 11602292SN/A "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 11612292SN/A head_inst->seqNum, head_inst->pcState()); 11622292SN/A 11632292SN/A if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 11642292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 11652292SN/A return false; 11662292SN/A } 11672292SN/A 11682292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11692292SN/A 11702292SN/A // Change the instruction so it won't try to commit again until 11712292SN/A // it is executed. 11722292SN/A head_inst->clearCanCommit(); 11732292SN/A 11742301SN/A if (head_inst->isLoad() && head_inst->strictlyOrdered()) { 11752292SN/A DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n", 11762292SN/A head_inst->seqNum, head_inst->pcState()); 11772292SN/A toIEW->commitInfo[tid].strictlyOrdered = true; 11782292SN/A toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst; 11792292SN/A } else { 11802292SN/A ++commitNonSpecStalls; 11812292SN/A } 11822292SN/A 11832292SN/A return false; 11842935Sksewell@umich.edu } 11852935Sksewell@umich.edu 11862935Sksewell@umich.edu if (head_inst->isThreadSync()) { 11872935Sksewell@umich.edu // Not handled for now. 11882935Sksewell@umich.edu panic("Thread sync instructions are not handled yet.\n"); 11892935Sksewell@umich.edu } 11902935Sksewell@umich.edu 11912292SN/A // Check if the instruction caused a fault. If so, trap. 11922292SN/A Fault inst_fault = head_inst->getFault(); 11932292SN/A 11942292SN/A // Stores mark themselves as completed. 11952292SN/A if (!head_inst->isStore() && inst_fault == NoFault) { 11962292SN/A head_inst->setCompleted(); 11972292SN/A } 11982292SN/A 11992292SN/A if (inst_fault != NoFault) { 12002292SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 12012292SN/A head_inst->seqNum, head_inst->pcState()); 12022292SN/A 12032292SN/A if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 12042292SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 12052292SN/A return false; 12062292SN/A } 12072292SN/A 12082292SN/A head_inst->setCompleted(); 12092292SN/A 12102292SN/A // If instruction has faulted, let the checker execute it and 12112292SN/A // check if it sees the same fault and control flow. 12122292SN/A if (cpu->checker) { 12132292SN/A // Need to check the instruction before its fault is processed 12142292SN/A cpu->checker->verify(head_inst); 12152292SN/A } 12162292SN/A 12172292SN/A assert(!thread[tid]->noSquashFromTC); 12182292SN/A 12192292SN/A // Mark that we're in state update mode so that the trap's 12202292SN/A // execution doesn't generate extra squashes. 12212292SN/A thread[tid]->noSquashFromTC = true; 12222292SN/A 12232292SN/A // Execute the trap. Although it's slightly unrealistic in 12242292SN/A // terms of timing (as it doesn't wait for the full timing of 12252292SN/A // the trap event to complete before updating state), it's 12262292SN/A // needed to update the state as soon as possible. This 12272292SN/A // prevents external agents from changing any specific state 12282292SN/A // that the trap need. 12292301SN/A cpu->trap(inst_fault, tid, 12302292SN/A head_inst->notAnInst() ? 12312301SN/A StaticInst::nullStaticInstPtr : 12322292SN/A head_inst->staticInst); 12332292SN/A 12342301SN/A // Exit state update mode to avoid accidental updating. 12352292SN/A thread[tid]->noSquashFromTC = false; 12362292SN/A 12372292SN/A commitStatus[tid] = TrapPending; 12382292SN/A 12392292SN/A DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 12402292SN/A head_inst->seqNum); 12412292SN/A if (head_inst->traceData) { 12422301SN/A if (DTRACE(ExecFaulting)) { 12432292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 12442292SN/A head_inst->traceData->setCPSeq(thread[tid]->numOp); 12452301SN/A head_inst->traceData->dump(); 12462292SN/A } 12472292SN/A delete head_inst->traceData; 12482301SN/A head_inst->traceData = NULL; 12492292SN/A } 12502301SN/A 12512292SN/A // Generate trap squash event. 12522292SN/A generateTrapEvent(tid, inst_fault); 12532292SN/A return false; 12542703Sktlim@umich.edu } 12552292SN/A 12562301SN/A updateComInstStats(head_inst); 12572292SN/A 12582292SN/A if (FullSystem) { 12592292SN/A if (thread[tid]->profile) { 12602292SN/A thread[tid]->profilePC = head_inst->instAddr(); 12612292SN/A ProfileNode *node = thread[tid]->profile->consume( 12622292SN/A thread[tid]->getTC(), head_inst->staticInst); 12632292SN/A 12641061SN/A if (node) 12651061SN/A thread[tid]->profileNode = node; 12661060SN/A } 12671060SN/A if (CPA::available()) { 12682292SN/A if (head_inst->isControl()) { 12692292SN/A ThreadContext *tc = thread[tid]->getTC(); 12701060SN/A CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 12712292SN/A } 12722292SN/A } 12732292SN/A } 12741060SN/A DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 12751060SN/A head_inst->seqNum, head_inst->pcState()); 12761060SN/A if (head_inst->traceData) { 12772292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 12782292SN/A head_inst->traceData->setCPSeq(thread[tid]->numOp); 12792292SN/A head_inst->traceData->dump(); 12802292SN/A delete head_inst->traceData; 12812292SN/A head_inst->traceData = NULL; 12822292SN/A } 12832292SN/A if (head_inst->isReturn()) { 12842292SN/A DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 12852292SN/A head_inst->seqNum, head_inst->pcState()); 12862292SN/A } 12872292SN/A 12882292SN/A // Update the commit rename map 12892292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12902292SN/A renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12912292SN/A head_inst->renamedDestRegIdx(i)); 12922292SN/A } 12932292SN/A 12942292SN/A // Finally clear the head ROB entry. 12952292SN/A rob->retireHead(tid); 12962292SN/A 12972292SN/A#if TRACING_ON 12981060SN/A if (DTRACE(O3PipeView)) { 12992292SN/A head_inst->commitTick = curTick() - head_inst->fetchTick; 13001060SN/A } 13012292SN/A#endif 13022292SN/A 13032292SN/A // If this was a store, record it for this cycle. 13042292SN/A if (head_inst->isStore()) 13052292SN/A committedStores[tid] = true; 13061060SN/A 13072292SN/A // Return true to indicate that we have committed an instruction. 13081060SN/A return true; 13092292SN/A} 13101060SN/A 13112292SN/Atemplate <class Impl> 13122292SN/Avoid 13132292SN/ADefaultCommit<Impl>::getInsts() 13142292SN/A{ 13151060SN/A DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 13162292SN/A 13171062SN/A // Read any renamed instructions and place them into the ROB. 13181060SN/A int insts_to_process = std::min((int)renameWidth, fromRename->size); 13191060SN/A 1320 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1321 const DynInstPtr &inst = fromRename->insts[inst_num]; 1322 ThreadID tid = inst->threadNumber; 1323 1324 if (!inst->isSquashed() && 1325 commitStatus[tid] != ROBSquashing && 1326 commitStatus[tid] != TrapPending) { 1327 changedROBNumEntries[tid] = true; 1328 1329 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1330 inst->pcState(), inst->seqNum, tid); 1331 1332 rob->insertInst(inst); 1333 1334 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1335 1336 youngestSeqNum[tid] = inst->seqNum; 1337 } else { 1338 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1339 "squashed, skipping.\n", 1340 inst->pcState(), inst->seqNum, tid); 1341 } 1342 } 1343} 1344 1345template <class Impl> 1346void 1347DefaultCommit<Impl>::markCompletedInsts() 1348{ 1349 // Grab completed insts out of the IEW instruction queue, and mark 1350 // instructions completed within the ROB. 1351 for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) { 1352 assert(fromIEW->insts[inst_num]); 1353 if (!fromIEW->insts[inst_num]->isSquashed()) { 1354 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1355 "within ROB.\n", 1356 fromIEW->insts[inst_num]->threadNumber, 1357 fromIEW->insts[inst_num]->pcState(), 1358 fromIEW->insts[inst_num]->seqNum); 1359 1360 // Mark the instruction as ready to commit. 1361 fromIEW->insts[inst_num]->setCanCommit(); 1362 } 1363 } 1364} 1365 1366template <class Impl> 1367void 1368DefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst) 1369{ 1370 ThreadID tid = inst->threadNumber; 1371 1372 if (!inst->isMicroop() || inst->isLastMicroop()) 1373 instsCommitted[tid]++; 1374 opsCommitted[tid]++; 1375 1376 // To match the old model, don't count nops and instruction 1377 // prefetches towards the total commit count. 1378 if (!inst->isNop() && !inst->isInstPrefetch()) { 1379 cpu->instDone(tid, inst); 1380 } 1381 1382 // 1383 // Control Instructions 1384 // 1385 if (inst->isControl()) 1386 statComBranches[tid]++; 1387 1388 // 1389 // Memory references 1390 // 1391 if (inst->isMemRef()) { 1392 statComRefs[tid]++; 1393 1394 if (inst->isLoad()) { 1395 statComLoads[tid]++; 1396 } 1397 } 1398 1399 if (inst->isMemBarrier()) { 1400 statComMembars[tid]++; 1401 } 1402 1403 // Integer Instruction 1404 if (inst->isInteger()) 1405 statComInteger[tid]++; 1406 1407 // Floating Point Instruction 1408 if (inst->isFloating()) 1409 statComFloating[tid]++; 1410 // Vector Instruction 1411 if (inst->isVector()) 1412 statComVector[tid]++; 1413 1414 // Function Calls 1415 if (inst->isCall()) 1416 statComFunctionCalls[tid]++; 1417 1418} 1419 1420//////////////////////////////////////// 1421// // 1422// SMT COMMIT POLICY MAINTAINED HERE // 1423// // 1424//////////////////////////////////////// 1425template <class Impl> 1426ThreadID 1427DefaultCommit<Impl>::getCommittingThread() 1428{ 1429 if (numThreads > 1) { 1430 switch (commitPolicy) { 1431 1432 case Aggressive: 1433 //If Policy is Aggressive, commit will call 1434 //this function multiple times per 1435 //cycle 1436 return oldestReady(); 1437 1438 case RoundRobin: 1439 return roundRobin(); 1440 1441 case OldestReady: 1442 return oldestReady(); 1443 1444 default: 1445 return InvalidThreadID; 1446 } 1447 } else { 1448 assert(!activeThreads->empty()); 1449 ThreadID tid = activeThreads->front(); 1450 1451 if (commitStatus[tid] == Running || 1452 commitStatus[tid] == Idle || 1453 commitStatus[tid] == FetchTrapPending) { 1454 return tid; 1455 } else { 1456 return InvalidThreadID; 1457 } 1458 } 1459} 1460 1461template<class Impl> 1462ThreadID 1463DefaultCommit<Impl>::roundRobin() 1464{ 1465 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1466 list<ThreadID>::iterator end = priority_list.end(); 1467 1468 while (pri_iter != end) { 1469 ThreadID tid = *pri_iter; 1470 1471 if (commitStatus[tid] == Running || 1472 commitStatus[tid] == Idle || 1473 commitStatus[tid] == FetchTrapPending) { 1474 1475 if (rob->isHeadReady(tid)) { 1476 priority_list.erase(pri_iter); 1477 priority_list.push_back(tid); 1478 1479 return tid; 1480 } 1481 } 1482 1483 pri_iter++; 1484 } 1485 1486 return InvalidThreadID; 1487} 1488 1489template<class Impl> 1490ThreadID 1491DefaultCommit<Impl>::oldestReady() 1492{ 1493 unsigned oldest = 0; 1494 bool first = true; 1495 1496 list<ThreadID>::iterator threads = activeThreads->begin(); 1497 list<ThreadID>::iterator end = activeThreads->end(); 1498 1499 while (threads != end) { 1500 ThreadID tid = *threads++; 1501 1502 if (!rob->isEmpty(tid) && 1503 (commitStatus[tid] == Running || 1504 commitStatus[tid] == Idle || 1505 commitStatus[tid] == FetchTrapPending)) { 1506 1507 if (rob->isHeadReady(tid)) { 1508 1509 const DynInstPtr &head_inst = rob->readHeadInst(tid); 1510 1511 if (first) { 1512 oldest = tid; 1513 first = false; 1514 } else if (head_inst->seqNum < oldest) { 1515 oldest = tid; 1516 } 1517 } 1518 } 1519 } 1520 1521 if (!first) { 1522 return oldest; 1523 } else { 1524 return InvalidThreadID; 1525 } 1526} 1527 1528#endif//__CPU_O3_COMMIT_IMPL_HH__ 1529