commit_impl.hh revision 11246:93d2a1526103 
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2014 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44#ifndef __CPU_O3_COMMIT_IMPL_HH__
45#define __CPU_O3_COMMIT_IMPL_HH__
46
47#include <algorithm>
48#include <set>
49#include <string>
50
51#include "arch/utility.hh"
52#include "base/loader/symtab.hh"
53#include "base/cp_annotate.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/commit.hh"
57#include "cpu/o3/thread_state.hh"
58#include "cpu/base.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/timebuf.hh"
61#include "debug/Activity.hh"
62#include "debug/Commit.hh"
63#include "debug/CommitRate.hh"
64#include "debug/Drain.hh"
65#include "debug/ExecFaulting.hh"
66#include "debug/O3PipeView.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/faults.hh"
69#include "sim/full_system.hh"
70
71using namespace std;
72
73template <class Impl>
74DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
75                                          ThreadID _tid)
76    : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
77{
78}
79
80template <class Impl>
81void
82DefaultCommit<Impl>::TrapEvent::process()
83{
84    // This will get reset by commit if it was switched out at the
85    // time of this event processing.
86    commit->trapSquash[tid] = true;
87}
88
89template <class Impl>
90const char *
91DefaultCommit<Impl>::TrapEvent::description() const
92{
93    return "Trap";
94}
95
96template <class Impl>
97DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
98    : cpu(_cpu),
99      iewToCommitDelay(params->iewToCommitDelay),
100      commitToIEWDelay(params->commitToIEWDelay),
101      renameToROBDelay(params->renameToROBDelay),
102      fetchToCommitDelay(params->commitToFetchDelay),
103      renameWidth(params->renameWidth),
104      commitWidth(params->commitWidth),
105      numThreads(params->numThreads),
106      drainPending(false),
107      drainImminent(false),
108      trapLatency(params->trapLatency),
109      canHandleInterrupts(true),
110      avoidQuiesceLiveLock(false)
111{
112    if (commitWidth > Impl::MaxWidth)
113        fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
114             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
115             commitWidth, static_cast<int>(Impl::MaxWidth));
116
117    _status = Active;
118    _nextStatus = Inactive;
119    std::string policy = params->smtCommitPolicy;
120
121    //Convert string to lowercase
122    std::transform(policy.begin(), policy.end(), policy.begin(),
123                   (int(*)(int)) tolower);
124
125    //Assign commit policy
126    if (policy == "aggressive"){
127        commitPolicy = Aggressive;
128
129        DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
130    } else if (policy == "roundrobin"){
131        commitPolicy = RoundRobin;
132
133        //Set-Up Priority List
134        for (ThreadID tid = 0; tid < numThreads; tid++) {
135            priority_list.push_back(tid);
136        }
137
138        DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
139    } else if (policy == "oldestready"){
140        commitPolicy = OldestReady;
141
142        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
143    } else {
144        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
145               "RoundRobin,OldestReady}");
146    }
147
148    for (ThreadID tid = 0; tid < numThreads; tid++) {
149        commitStatus[tid] = Idle;
150        changedROBNumEntries[tid] = false;
151        checkEmptyROB[tid] = false;
152        trapInFlight[tid] = false;
153        committedStores[tid] = false;
154        trapSquash[tid] = false;
155        tcSquash[tid] = false;
156        pc[tid].set(0);
157        lastCommitedSeqNum[tid] = 0;
158        squashAfterInst[tid] = NULL;
159    }
160    interrupt = NoFault;
161}
162
163template <class Impl>
164std::string
165DefaultCommit<Impl>::name() const
166{
167    return cpu->name() + ".commit";
168}
169
170template <class Impl>
171void
172DefaultCommit<Impl>::regProbePoints()
173{
174    ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
175    ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
176    ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
177}
178
179template <class Impl>
180void
181DefaultCommit<Impl>::regStats()
182{
183    using namespace Stats;
184    commitSquashedInsts
185        .name(name() + ".commitSquashedInsts")
186        .desc("The number of squashed insts skipped by commit")
187        .prereq(commitSquashedInsts);
188
189    commitNonSpecStalls
190        .name(name() + ".commitNonSpecStalls")
191        .desc("The number of times commit has been forced to stall to "
192              "communicate backwards")
193        .prereq(commitNonSpecStalls);
194
195    branchMispredicts
196        .name(name() + ".branchMispredicts")
197        .desc("The number of times a branch was mispredicted")
198        .prereq(branchMispredicts);
199
200    numCommittedDist
201        .init(0,commitWidth,1)
202        .name(name() + ".committed_per_cycle")
203        .desc("Number of insts commited each cycle")
204        .flags(Stats::pdf)
205        ;
206
207    instsCommitted
208        .init(cpu->numThreads)
209        .name(name() + ".committedInsts")
210        .desc("Number of instructions committed")
211        .flags(total)
212        ;
213
214    opsCommitted
215        .init(cpu->numThreads)
216        .name(name() + ".committedOps")
217        .desc("Number of ops (including micro ops) committed")
218        .flags(total)
219        ;
220
221    statComSwp
222        .init(cpu->numThreads)
223        .name(name() + ".swp_count")
224        .desc("Number of s/w prefetches committed")
225        .flags(total)
226        ;
227
228    statComRefs
229        .init(cpu->numThreads)
230        .name(name() +  ".refs")
231        .desc("Number of memory references committed")
232        .flags(total)
233        ;
234
235    statComLoads
236        .init(cpu->numThreads)
237        .name(name() +  ".loads")
238        .desc("Number of loads committed")
239        .flags(total)
240        ;
241
242    statComMembars
243        .init(cpu->numThreads)
244        .name(name() +  ".membars")
245        .desc("Number of memory barriers committed")
246        .flags(total)
247        ;
248
249    statComBranches
250        .init(cpu->numThreads)
251        .name(name() + ".branches")
252        .desc("Number of branches committed")
253        .flags(total)
254        ;
255
256    statComFloating
257        .init(cpu->numThreads)
258        .name(name() + ".fp_insts")
259        .desc("Number of committed floating point instructions.")
260        .flags(total)
261        ;
262
263    statComInteger
264        .init(cpu->numThreads)
265        .name(name()+".int_insts")
266        .desc("Number of committed integer instructions.")
267        .flags(total)
268        ;
269
270    statComFunctionCalls
271        .init(cpu->numThreads)
272        .name(name()+".function_calls")
273        .desc("Number of function calls committed.")
274        .flags(total)
275        ;
276
277    statCommittedInstType
278        .init(numThreads,Enums::Num_OpClass)
279        .name(name() + ".op_class")
280        .desc("Class of committed instruction")
281        .flags(total | pdf | dist)
282        ;
283    statCommittedInstType.ysubnames(Enums::OpClassStrings);
284
285    commitEligibleSamples
286        .name(name() + ".bw_lim_events")
287        .desc("number cycles where commit BW limit reached")
288        ;
289}
290
291template <class Impl>
292void
293DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
294{
295    thread = threads;
296}
297
298template <class Impl>
299void
300DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
301{
302    timeBuffer = tb_ptr;
303
304    // Setup wire to send information back to IEW.
305    toIEW = timeBuffer->getWire(0);
306
307    // Setup wire to read data from IEW (for the ROB).
308    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
309}
310
311template <class Impl>
312void
313DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
314{
315    fetchQueue = fq_ptr;
316
317    // Setup wire to get instructions from rename (for the ROB).
318    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
319}
320
321template <class Impl>
322void
323DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
324{
325    renameQueue = rq_ptr;
326
327    // Setup wire to get instructions from rename (for the ROB).
328    fromRename = renameQueue->getWire(-renameToROBDelay);
329}
330
331template <class Impl>
332void
333DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
334{
335    iewQueue = iq_ptr;
336
337    // Setup wire to get instructions from IEW.
338    fromIEW = iewQueue->getWire(-iewToCommitDelay);
339}
340
341template <class Impl>
342void
343DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
344{
345    iewStage = iew_stage;
346}
347
348template<class Impl>
349void
350DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
351{
352    activeThreads = at_ptr;
353}
354
355template <class Impl>
356void
357DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
358{
359    for (ThreadID tid = 0; tid < numThreads; tid++)
360        renameMap[tid] = &rm_ptr[tid];
361}
362
363template <class Impl>
364void
365DefaultCommit<Impl>::setROB(ROB *rob_ptr)
366{
367    rob = rob_ptr;
368}
369
370template <class Impl>
371void
372DefaultCommit<Impl>::startupStage()
373{
374    rob->setActiveThreads(activeThreads);
375    rob->resetEntries();
376
377    // Broadcast the number of free entries.
378    for (ThreadID tid = 0; tid < numThreads; tid++) {
379        toIEW->commitInfo[tid].usedROB = true;
380        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
381        toIEW->commitInfo[tid].emptyROB = true;
382    }
383
384    // Commit must broadcast the number of free entries it has at the
385    // start of the simulation, so it starts as active.
386    cpu->activateStage(O3CPU::CommitIdx);
387
388    cpu->activityThisCycle();
389}
390
391template <class Impl>
392void
393DefaultCommit<Impl>::drain()
394{
395    drainPending = true;
396}
397
398template <class Impl>
399void
400DefaultCommit<Impl>::drainResume()
401{
402    drainPending = false;
403    drainImminent = false;
404}
405
406template <class Impl>
407void
408DefaultCommit<Impl>::drainSanityCheck() const
409{
410    assert(isDrained());
411    rob->drainSanityCheck();
412}
413
414template <class Impl>
415bool
416DefaultCommit<Impl>::isDrained() const
417{
418    /* Make sure no one is executing microcode. There are two reasons
419     * for this:
420     * - Hardware virtualized CPUs can't switch into the middle of a
421     *   microcode sequence.
422     * - The current fetch implementation will most likely get very
423     *   confused if it tries to start fetching an instruction that
424     *   is executing in the middle of a ucode sequence that changes
425     *   address mappings. This can happen on for example x86.
426     */
427    for (ThreadID tid = 0; tid < numThreads; tid++) {
428        if (pc[tid].microPC() != 0)
429            return false;
430    }
431
432    /* Make sure that all instructions have finished committing before
433     * declaring the system as drained. We want the pipeline to be
434     * completely empty when we declare the CPU to be drained. This
435     * makes debugging easier since CPU handover and restoring from a
436     * checkpoint with a different CPU should have the same timing.
437     */
438    return rob->isEmpty() &&
439        interrupt == NoFault;
440}
441
442template <class Impl>
443void
444DefaultCommit<Impl>::takeOverFrom()
445{
446    _status = Active;
447    _nextStatus = Inactive;
448    for (ThreadID tid = 0; tid < numThreads; tid++) {
449        commitStatus[tid] = Idle;
450        changedROBNumEntries[tid] = false;
451        trapSquash[tid] = false;
452        tcSquash[tid] = false;
453        squashAfterInst[tid] = NULL;
454    }
455    rob->takeOverFrom();
456}
457
458template <class Impl>
459void
460DefaultCommit<Impl>::deactivateThread(ThreadID tid)
461{
462    list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
463            priority_list.end(), tid);
464
465    if (thread_it != priority_list.end()) {
466        priority_list.erase(thread_it);
467    }
468}
469
470
471template <class Impl>
472void
473DefaultCommit<Impl>::updateStatus()
474{
475    // reset ROB changed variable
476    list<ThreadID>::iterator threads = activeThreads->begin();
477    list<ThreadID>::iterator end = activeThreads->end();
478
479    while (threads != end) {
480        ThreadID tid = *threads++;
481
482        changedROBNumEntries[tid] = false;
483
484        // Also check if any of the threads has a trap pending
485        if (commitStatus[tid] == TrapPending ||
486            commitStatus[tid] == FetchTrapPending) {
487            _nextStatus = Active;
488        }
489    }
490
491    if (_nextStatus == Inactive && _status == Active) {
492        DPRINTF(Activity, "Deactivating stage.\n");
493        cpu->deactivateStage(O3CPU::CommitIdx);
494    } else if (_nextStatus == Active && _status == Inactive) {
495        DPRINTF(Activity, "Activating stage.\n");
496        cpu->activateStage(O3CPU::CommitIdx);
497    }
498
499    _status = _nextStatus;
500}
501
502template <class Impl>
503bool
504DefaultCommit<Impl>::changedROBEntries()
505{
506    list<ThreadID>::iterator threads = activeThreads->begin();
507    list<ThreadID>::iterator end = activeThreads->end();
508
509    while (threads != end) {
510        ThreadID tid = *threads++;
511
512        if (changedROBNumEntries[tid]) {
513            return true;
514        }
515    }
516
517    return false;
518}
519
520template <class Impl>
521size_t
522DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
523{
524    return rob->numFreeEntries(tid);
525}
526
527template <class Impl>
528void
529DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
530{
531    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
532
533    TrapEvent *trap = new TrapEvent(this, tid);
534
535    cpu->schedule(trap, cpu->clockEdge(trapLatency));
536    trapInFlight[tid] = true;
537    thread[tid]->trapPending = true;
538}
539
540template <class Impl>
541void
542DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
543{
544    assert(!trapInFlight[tid]);
545    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
546
547    tcSquash[tid] = true;
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::squashAll(ThreadID tid)
553{
554    // If we want to include the squashing instruction in the squash,
555    // then use one older sequence number.
556    // Hopefully this doesn't mess things up.  Basically I want to squash
557    // all instructions of this thread.
558    InstSeqNum squashed_inst = rob->isEmpty(tid) ?
559        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
560
561    // All younger instructions will be squashed. Set the sequence
562    // number as the youngest instruction in the ROB (0 in this case.
563    // Hopefully nothing breaks.)
564    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
565
566    rob->squash(squashed_inst, tid);
567    changedROBNumEntries[tid] = true;
568
569    // Send back the sequence number of the squashed instruction.
570    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
571
572    // Send back the squash signal to tell stages that they should
573    // squash.
574    toIEW->commitInfo[tid].squash = true;
575
576    // Send back the rob squashing signal so other stages know that
577    // the ROB is in the process of squashing.
578    toIEW->commitInfo[tid].robSquashing = true;
579
580    toIEW->commitInfo[tid].mispredictInst = NULL;
581    toIEW->commitInfo[tid].squashInst = NULL;
582
583    toIEW->commitInfo[tid].pc = pc[tid];
584}
585
586template <class Impl>
587void
588DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
589{
590    squashAll(tid);
591
592    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
593
594    thread[tid]->trapPending = false;
595    thread[tid]->noSquashFromTC = false;
596    trapInFlight[tid] = false;
597
598    trapSquash[tid] = false;
599
600    commitStatus[tid] = ROBSquashing;
601    cpu->activityThisCycle();
602}
603
604template <class Impl>
605void
606DefaultCommit<Impl>::squashFromTC(ThreadID tid)
607{
608    squashAll(tid);
609
610    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
611
612    thread[tid]->noSquashFromTC = false;
613    assert(!thread[tid]->trapPending);
614
615    commitStatus[tid] = ROBSquashing;
616    cpu->activityThisCycle();
617
618    tcSquash[tid] = false;
619}
620
621template <class Impl>
622void
623DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
624{
625    DPRINTF(Commit, "Squashing after squash after request, "
626            "restarting at PC %s\n", pc[tid]);
627
628    squashAll(tid);
629    // Make sure to inform the fetch stage of which instruction caused
630    // the squash. It'll try to re-fetch an instruction executing in
631    // microcode unless this is set.
632    toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
633    squashAfterInst[tid] = NULL;
634
635    commitStatus[tid] = ROBSquashing;
636    cpu->activityThisCycle();
637}
638
639template <class Impl>
640void
641DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
642{
643    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
644            tid, head_inst->seqNum);
645
646    assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
647    commitStatus[tid] = SquashAfterPending;
648    squashAfterInst[tid] = head_inst;
649}
650
651template <class Impl>
652void
653DefaultCommit<Impl>::tick()
654{
655    wroteToTimeBuffer = false;
656    _nextStatus = Inactive;
657
658    if (activeThreads->empty())
659        return;
660
661    list<ThreadID>::iterator threads = activeThreads->begin();
662    list<ThreadID>::iterator end = activeThreads->end();
663
664    // Check if any of the threads are done squashing.  Change the
665    // status if they are done.
666    while (threads != end) {
667        ThreadID tid = *threads++;
668
669        // Clear the bit saying if the thread has committed stores
670        // this cycle.
671        committedStores[tid] = false;
672
673        if (commitStatus[tid] == ROBSquashing) {
674
675            if (rob->isDoneSquashing(tid)) {
676                commitStatus[tid] = Running;
677            } else {
678                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
679                        " insts this cycle.\n", tid);
680                rob->doSquash(tid);
681                toIEW->commitInfo[tid].robSquashing = true;
682                wroteToTimeBuffer = true;
683            }
684        }
685    }
686
687    commit();
688
689    markCompletedInsts();
690
691    threads = activeThreads->begin();
692
693    while (threads != end) {
694        ThreadID tid = *threads++;
695
696        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
697            // The ROB has more instructions it can commit. Its next status
698            // will be active.
699            _nextStatus = Active;
700
701            DynInstPtr inst = rob->readHeadInst(tid);
702
703            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
704                    " ROB and ready to commit\n",
705                    tid, inst->seqNum, inst->pcState());
706
707        } else if (!rob->isEmpty(tid)) {
708            DynInstPtr inst = rob->readHeadInst(tid);
709
710            ppCommitStall->notify(inst);
711
712            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
713                    "%s is head of ROB and not ready\n",
714                    tid, inst->seqNum, inst->pcState());
715        }
716
717        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
718                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
719    }
720
721
722    if (wroteToTimeBuffer) {
723        DPRINTF(Activity, "Activity This Cycle.\n");
724        cpu->activityThisCycle();
725    }
726
727    updateStatus();
728}
729
730template <class Impl>
731void
732DefaultCommit<Impl>::handleInterrupt()
733{
734    // Verify that we still have an interrupt to handle
735    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
736        DPRINTF(Commit, "Pending interrupt is cleared by master before "
737                "it got handled. Restart fetching from the orig path.\n");
738        toIEW->commitInfo[0].clearInterrupt = true;
739        interrupt = NoFault;
740        avoidQuiesceLiveLock = true;
741        return;
742    }
743
744    // Wait until all in flight instructions are finished before enterring
745    // the interrupt.
746    if (canHandleInterrupts && cpu->instList.empty()) {
747        // Squash or record that I need to squash this cycle if
748        // an interrupt needed to be handled.
749        DPRINTF(Commit, "Interrupt detected.\n");
750
751        // Clear the interrupt now that it's going to be handled
752        toIEW->commitInfo[0].clearInterrupt = true;
753
754        assert(!thread[0]->noSquashFromTC);
755        thread[0]->noSquashFromTC = true;
756
757        if (cpu->checker) {
758            cpu->checker->handlePendingInt();
759        }
760
761        // CPU will handle interrupt. Note that we ignore the local copy of
762        // interrupt. This is because the local copy may no longer be the
763        // interrupt that the interrupt controller thinks is being handled.
764        cpu->processInterrupts(cpu->getInterrupts());
765
766        thread[0]->noSquashFromTC = false;
767
768        commitStatus[0] = TrapPending;
769
770        // Generate trap squash event.
771        generateTrapEvent(0);
772
773        interrupt = NoFault;
774        avoidQuiesceLiveLock = false;
775    } else {
776        DPRINTF(Commit, "Interrupt pending: instruction is %sin "
777                "flight, ROB is %sempty\n",
778                canHandleInterrupts ? "not " : "",
779                cpu->instList.empty() ? "" : "not " );
780    }
781}
782
783template <class Impl>
784void
785DefaultCommit<Impl>::propagateInterrupt()
786{
787    // Don't propagate intterupts if we are currently handling a trap or
788    // in draining and the last observable instruction has been committed.
789    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
790            tcSquash[0] || drainImminent)
791        return;
792
793    // Process interrupts if interrupts are enabled, not in PAL
794    // mode, and no other traps or external squashes are currently
795    // pending.
796    // @todo: Allow other threads to handle interrupts.
797
798    // Get any interrupt that happened
799    interrupt = cpu->getInterrupts();
800
801    // Tell fetch that there is an interrupt pending.  This
802    // will make fetch wait until it sees a non PAL-mode PC,
803    // at which point it stops fetching instructions.
804    if (interrupt != NoFault)
805        toIEW->commitInfo[0].interruptPending = true;
806}
807
808template <class Impl>
809void
810DefaultCommit<Impl>::commit()
811{
812    if (FullSystem) {
813        // Check if we have a interrupt and get read to handle it
814        if (cpu->checkInterrupts(cpu->tcBase(0)))
815            propagateInterrupt();
816    }
817
818    ////////////////////////////////////
819    // Check for any possible squashes, handle them first
820    ////////////////////////////////////
821    list<ThreadID>::iterator threads = activeThreads->begin();
822    list<ThreadID>::iterator end = activeThreads->end();
823
824    int num_squashing_threads = 0;
825
826    while (threads != end) {
827        ThreadID tid = *threads++;
828
829        // Not sure which one takes priority.  I think if we have
830        // both, that's a bad sign.
831        if (trapSquash[tid]) {
832            assert(!tcSquash[tid]);
833            squashFromTrap(tid);
834        } else if (tcSquash[tid]) {
835            assert(commitStatus[tid] != TrapPending);
836            squashFromTC(tid);
837        } else if (commitStatus[tid] == SquashAfterPending) {
838            // A squash from the previous cycle of the commit stage (i.e.,
839            // commitInsts() called squashAfter) is pending. Squash the
840            // thread now.
841            squashFromSquashAfter(tid);
842        }
843
844        // Squashed sequence number must be older than youngest valid
845        // instruction in the ROB. This prevents squashes from younger
846        // instructions overriding squashes from older instructions.
847        if (fromIEW->squash[tid] &&
848            commitStatus[tid] != TrapPending &&
849            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
850
851            if (fromIEW->mispredictInst[tid]) {
852                DPRINTF(Commit,
853                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
854                    tid,
855                    fromIEW->mispredictInst[tid]->instAddr(),
856                    fromIEW->squashedSeqNum[tid]);
857            } else {
858                DPRINTF(Commit,
859                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
860                    tid, fromIEW->squashedSeqNum[tid]);
861            }
862
863            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
864                    tid,
865                    fromIEW->pc[tid].nextInstAddr());
866
867            commitStatus[tid] = ROBSquashing;
868
869            // If we want to include the squashing instruction in the squash,
870            // then use one older sequence number.
871            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
872
873            if (fromIEW->includeSquashInst[tid]) {
874                squashed_inst--;
875            }
876
877            // All younger instructions will be squashed. Set the sequence
878            // number as the youngest instruction in the ROB.
879            youngestSeqNum[tid] = squashed_inst;
880
881            rob->squash(squashed_inst, tid);
882            changedROBNumEntries[tid] = true;
883
884            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
885
886            toIEW->commitInfo[tid].squash = true;
887
888            // Send back the rob squashing signal so other stages know that
889            // the ROB is in the process of squashing.
890            toIEW->commitInfo[tid].robSquashing = true;
891
892            toIEW->commitInfo[tid].mispredictInst =
893                fromIEW->mispredictInst[tid];
894            toIEW->commitInfo[tid].branchTaken =
895                fromIEW->branchTaken[tid];
896            toIEW->commitInfo[tid].squashInst =
897                                    rob->findInst(tid, squashed_inst);
898            if (toIEW->commitInfo[tid].mispredictInst) {
899                if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
900                     toIEW->commitInfo[tid].branchTaken = true;
901                }
902                ++branchMispredicts;
903            }
904
905            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
906        }
907
908        if (commitStatus[tid] == ROBSquashing) {
909            num_squashing_threads++;
910        }
911    }
912
913    // If commit is currently squashing, then it will have activity for the
914    // next cycle. Set its next status as active.
915    if (num_squashing_threads) {
916        _nextStatus = Active;
917    }
918
919    if (num_squashing_threads != numThreads) {
920        // If we're not currently squashing, then get instructions.
921        getInsts();
922
923        // Try to commit any instructions.
924        commitInsts();
925    }
926
927    //Check for any activity
928    threads = activeThreads->begin();
929
930    while (threads != end) {
931        ThreadID tid = *threads++;
932
933        if (changedROBNumEntries[tid]) {
934            toIEW->commitInfo[tid].usedROB = true;
935            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
936
937            wroteToTimeBuffer = true;
938            changedROBNumEntries[tid] = false;
939            if (rob->isEmpty(tid))
940                checkEmptyROB[tid] = true;
941        }
942
943        // ROB is only considered "empty" for previous stages if: a)
944        // ROB is empty, b) there are no outstanding stores, c) IEW
945        // stage has received any information regarding stores that
946        // committed.
947        // c) is checked by making sure to not consider the ROB empty
948        // on the same cycle as when stores have been committed.
949        // @todo: Make this handle multi-cycle communication between
950        // commit and IEW.
951        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
952            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
953            checkEmptyROB[tid] = false;
954            toIEW->commitInfo[tid].usedROB = true;
955            toIEW->commitInfo[tid].emptyROB = true;
956            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
957            wroteToTimeBuffer = true;
958        }
959
960    }
961}
962
963template <class Impl>
964void
965DefaultCommit<Impl>::commitInsts()
966{
967    ////////////////////////////////////
968    // Handle commit
969    // Note that commit will be handled prior to putting new
970    // instructions in the ROB so that the ROB only tries to commit
971    // instructions it has in this current cycle, and not instructions
972    // it is writing in during this cycle.  Can't commit and squash
973    // things at the same time...
974    ////////////////////////////////////
975
976    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
977
978    unsigned num_committed = 0;
979
980    DynInstPtr head_inst;
981
982    // Commit as many instructions as possible until the commit bandwidth
983    // limit is reached, or it becomes impossible to commit any more.
984    while (num_committed < commitWidth) {
985        // Check for any interrupt that we've already squashed for
986        // and start processing it.
987        if (interrupt != NoFault)
988            handleInterrupt();
989
990        ThreadID commit_thread = getCommittingThread();
991
992        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
993            break;
994
995        head_inst = rob->readHeadInst(commit_thread);
996
997        ThreadID tid = head_inst->threadNumber;
998
999        assert(tid == commit_thread);
1000
1001        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1002                head_inst->seqNum, tid);
1003
1004        // If the head instruction is squashed, it is ready to retire
1005        // (be removed from the ROB) at any time.
1006        if (head_inst->isSquashed()) {
1007
1008            DPRINTF(Commit, "Retiring squashed instruction from "
1009                    "ROB.\n");
1010
1011            rob->retireHead(commit_thread);
1012
1013            ++commitSquashedInsts;
1014            // Notify potential listeners that this instruction is squashed
1015            ppSquash->notify(head_inst);
1016
1017            // Record that the number of ROB entries has changed.
1018            changedROBNumEntries[tid] = true;
1019        } else {
1020            pc[tid] = head_inst->pcState();
1021
1022            // Increment the total number of non-speculative instructions
1023            // executed.
1024            // Hack for now: it really shouldn't happen until after the
1025            // commit is deemed to be successful, but this count is needed
1026            // for syscalls.
1027            thread[tid]->funcExeInst++;
1028
1029            // Try to commit the head instruction.
1030            bool commit_success = commitHead(head_inst, num_committed);
1031
1032            if (commit_success) {
1033                ++num_committed;
1034                statCommittedInstType[tid][head_inst->opClass()]++;
1035                ppCommit->notify(head_inst);
1036
1037                changedROBNumEntries[tid] = true;
1038
1039                // Set the doneSeqNum to the youngest committed instruction.
1040                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1041
1042                if (tid == 0) {
1043                    canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
1044                                           ((THE_ISA != ALPHA_ISA) ||
1045                                             (!(pc[0].instAddr() & 0x3)));
1046                }
1047
1048                // Updates misc. registers.
1049                head_inst->updateMiscRegs();
1050
1051                // Check instruction execution if it successfully commits and
1052                // is not carrying a fault.
1053                if (cpu->checker) {
1054                    cpu->checker->verify(head_inst);
1055                }
1056
1057                cpu->traceFunctions(pc[tid].instAddr());
1058
1059                TheISA::advancePC(pc[tid], head_inst->staticInst);
1060
1061                // Keep track of the last sequence number commited
1062                lastCommitedSeqNum[tid] = head_inst->seqNum;
1063
1064                // If this is an instruction that doesn't play nicely with
1065                // others squash everything and restart fetch
1066                if (head_inst->isSquashAfter())
1067                    squashAfter(tid, head_inst);
1068
1069                if (drainPending) {
1070                    if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1071                        !thread[tid]->trapPending) {
1072                        // Last architectually committed instruction.
1073                        // Squash the pipeline, stall fetch, and use
1074                        // drainImminent to disable interrupts
1075                        DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1076                        squashAfter(tid, head_inst);
1077                        cpu->commitDrained(tid);
1078                        drainImminent = true;
1079                    }
1080                }
1081
1082                bool onInstBoundary = !head_inst->isMicroop() ||
1083                                      head_inst->isLastMicroop() ||
1084                                      !head_inst->isDelayedCommit();
1085
1086                if (onInstBoundary) {
1087                    int count = 0;
1088                    Addr oldpc;
1089                    // Make sure we're not currently updating state while
1090                    // handling PC events.
1091                    assert(!thread[tid]->noSquashFromTC &&
1092                           !thread[tid]->trapPending);
1093                    do {
1094                        oldpc = pc[tid].instAddr();
1095                        cpu->system->pcEventQueue.service(thread[tid]->getTC());
1096                        count++;
1097                    } while (oldpc != pc[tid].instAddr());
1098                    if (count > 1) {
1099                        DPRINTF(Commit,
1100                                "PC skip function event, stopping commit\n");
1101                        break;
1102                    }
1103                }
1104
1105                // Check if an instruction just enabled interrupts and we've
1106                // previously had an interrupt pending that was not handled
1107                // because interrupts were subsequently disabled before the
1108                // pipeline reached a place to handle the interrupt. In that
1109                // case squash now to make sure the interrupt is handled.
1110                //
1111                // If we don't do this, we might end up in a live lock situation
1112                if (!interrupt && avoidQuiesceLiveLock &&
1113                    onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1114                    squashAfter(tid, head_inst);
1115            } else {
1116                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1117                        "[tid:%i] [sn:%i].\n",
1118                        head_inst->pcState(), tid ,head_inst->seqNum);
1119                break;
1120            }
1121        }
1122    }
1123
1124    DPRINTF(CommitRate, "%i\n", num_committed);
1125    numCommittedDist.sample(num_committed);
1126
1127    if (num_committed == commitWidth) {
1128        commitEligibleSamples++;
1129    }
1130}
1131
1132template <class Impl>
1133bool
1134DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1135{
1136    assert(head_inst);
1137
1138    ThreadID tid = head_inst->threadNumber;
1139
1140    // If the instruction is not executed yet, then it will need extra
1141    // handling.  Signal backwards that it should be executed.
1142    if (!head_inst->isExecuted()) {
1143        // Keep this number correct.  We have not yet actually executed
1144        // and committed this instruction.
1145        thread[tid]->funcExeInst--;
1146
1147        // Make sure we are only trying to commit un-executed instructions we
1148        // think are possible.
1149        assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1150               || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1151               (head_inst->isLoad() && head_inst->strictlyOrdered()));
1152
1153        DPRINTF(Commit, "Encountered a barrier or non-speculative "
1154                "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1155                head_inst->seqNum, head_inst->pcState());
1156
1157        if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1158            DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1159            return false;
1160        }
1161
1162        toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1163
1164        // Change the instruction so it won't try to commit again until
1165        // it is executed.
1166        head_inst->clearCanCommit();
1167
1168        if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1169            DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n",
1170                    head_inst->seqNum, head_inst->pcState());
1171            toIEW->commitInfo[tid].strictlyOrdered = true;
1172            toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1173        } else {
1174            ++commitNonSpecStalls;
1175        }
1176
1177        return false;
1178    }
1179
1180    if (head_inst->isThreadSync()) {
1181        // Not handled for now.
1182        panic("Thread sync instructions are not handled yet.\n");
1183    }
1184
1185    // Check if the instruction caused a fault.  If so, trap.
1186    Fault inst_fault = head_inst->getFault();
1187
1188    // Stores mark themselves as completed.
1189    if (!head_inst->isStore() && inst_fault == NoFault) {
1190        head_inst->setCompleted();
1191    }
1192
1193    if (inst_fault != NoFault) {
1194        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1195                head_inst->seqNum, head_inst->pcState());
1196
1197        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1198            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1199            return false;
1200        }
1201
1202        head_inst->setCompleted();
1203
1204        // If instruction has faulted, let the checker execute it and
1205        // check if it sees the same fault and control flow.
1206        if (cpu->checker) {
1207            // Need to check the instruction before its fault is processed
1208            cpu->checker->verify(head_inst);
1209        }
1210
1211        assert(!thread[tid]->noSquashFromTC);
1212
1213        // Mark that we're in state update mode so that the trap's
1214        // execution doesn't generate extra squashes.
1215        thread[tid]->noSquashFromTC = true;
1216
1217        // Execute the trap.  Although it's slightly unrealistic in
1218        // terms of timing (as it doesn't wait for the full timing of
1219        // the trap event to complete before updating state), it's
1220        // needed to update the state as soon as possible.  This
1221        // prevents external agents from changing any specific state
1222        // that the trap need.
1223        cpu->trap(inst_fault, tid, head_inst->staticInst);
1224
1225        // Exit state update mode to avoid accidental updating.
1226        thread[tid]->noSquashFromTC = false;
1227
1228        commitStatus[tid] = TrapPending;
1229
1230        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1231            head_inst->seqNum);
1232        if (head_inst->traceData) {
1233            if (DTRACE(ExecFaulting)) {
1234                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1235                head_inst->traceData->setCPSeq(thread[tid]->numOp);
1236                head_inst->traceData->dump();
1237            }
1238            delete head_inst->traceData;
1239            head_inst->traceData = NULL;
1240        }
1241
1242        // Generate trap squash event.
1243        generateTrapEvent(tid);
1244        return false;
1245    }
1246
1247    updateComInstStats(head_inst);
1248
1249    if (FullSystem) {
1250        if (thread[tid]->profile) {
1251            thread[tid]->profilePC = head_inst->instAddr();
1252            ProfileNode *node = thread[tid]->profile->consume(
1253                    thread[tid]->getTC(), head_inst->staticInst);
1254
1255            if (node)
1256                thread[tid]->profileNode = node;
1257        }
1258        if (CPA::available()) {
1259            if (head_inst->isControl()) {
1260                ThreadContext *tc = thread[tid]->getTC();
1261                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1262            }
1263        }
1264    }
1265    DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1266            head_inst->seqNum, head_inst->pcState());
1267    if (head_inst->traceData) {
1268        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1269        head_inst->traceData->setCPSeq(thread[tid]->numOp);
1270        head_inst->traceData->dump();
1271        delete head_inst->traceData;
1272        head_inst->traceData = NULL;
1273    }
1274    if (head_inst->isReturn()) {
1275        DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1276                        head_inst->seqNum, head_inst->pcState());
1277    }
1278
1279    // Update the commit rename map
1280    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1281        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1282                                 head_inst->renamedDestRegIdx(i));
1283    }
1284
1285    // Finally clear the head ROB entry.
1286    rob->retireHead(tid);
1287
1288#if TRACING_ON
1289    if (DTRACE(O3PipeView)) {
1290        head_inst->commitTick = curTick() - head_inst->fetchTick;
1291    }
1292#endif
1293
1294    // If this was a store, record it for this cycle.
1295    if (head_inst->isStore())
1296        committedStores[tid] = true;
1297
1298    // Return true to indicate that we have committed an instruction.
1299    return true;
1300}
1301
1302template <class Impl>
1303void
1304DefaultCommit<Impl>::getInsts()
1305{
1306    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1307
1308    // Read any renamed instructions and place them into the ROB.
1309    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1310
1311    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1312        DynInstPtr inst;
1313
1314        inst = fromRename->insts[inst_num];
1315        ThreadID tid = inst->threadNumber;
1316
1317        if (!inst->isSquashed() &&
1318            commitStatus[tid] != ROBSquashing &&
1319            commitStatus[tid] != TrapPending) {
1320            changedROBNumEntries[tid] = true;
1321
1322            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1323                    inst->pcState(), inst->seqNum, tid);
1324
1325            rob->insertInst(inst);
1326
1327            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1328
1329            youngestSeqNum[tid] = inst->seqNum;
1330        } else {
1331            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1332                    "squashed, skipping.\n",
1333                    inst->pcState(), inst->seqNum, tid);
1334        }
1335    }
1336}
1337
1338template <class Impl>
1339void
1340DefaultCommit<Impl>::markCompletedInsts()
1341{
1342    // Grab completed insts out of the IEW instruction queue, and mark
1343    // instructions completed within the ROB.
1344    for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1345        assert(fromIEW->insts[inst_num]);
1346        if (!fromIEW->insts[inst_num]->isSquashed()) {
1347            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1348                    "within ROB.\n",
1349                    fromIEW->insts[inst_num]->threadNumber,
1350                    fromIEW->insts[inst_num]->pcState(),
1351                    fromIEW->insts[inst_num]->seqNum);
1352
1353            // Mark the instruction as ready to commit.
1354            fromIEW->insts[inst_num]->setCanCommit();
1355        }
1356    }
1357}
1358
1359template <class Impl>
1360void
1361DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1362{
1363    ThreadID tid = inst->threadNumber;
1364
1365    if (!inst->isMicroop() || inst->isLastMicroop())
1366        instsCommitted[tid]++;
1367    opsCommitted[tid]++;
1368
1369    // To match the old model, don't count nops and instruction
1370    // prefetches towards the total commit count.
1371    if (!inst->isNop() && !inst->isInstPrefetch()) {
1372        cpu->instDone(tid, inst);
1373    }
1374
1375    //
1376    //  Control Instructions
1377    //
1378    if (inst->isControl())
1379        statComBranches[tid]++;
1380
1381    //
1382    //  Memory references
1383    //
1384    if (inst->isMemRef()) {
1385        statComRefs[tid]++;
1386
1387        if (inst->isLoad()) {
1388            statComLoads[tid]++;
1389        }
1390    }
1391
1392    if (inst->isMemBarrier()) {
1393        statComMembars[tid]++;
1394    }
1395
1396    // Integer Instruction
1397    if (inst->isInteger())
1398        statComInteger[tid]++;
1399
1400    // Floating Point Instruction
1401    if (inst->isFloating())
1402        statComFloating[tid]++;
1403
1404    // Function Calls
1405    if (inst->isCall())
1406        statComFunctionCalls[tid]++;
1407
1408}
1409
1410////////////////////////////////////////
1411//                                    //
1412//  SMT COMMIT POLICY MAINTAINED HERE //
1413//                                    //
1414////////////////////////////////////////
1415template <class Impl>
1416ThreadID
1417DefaultCommit<Impl>::getCommittingThread()
1418{
1419    if (numThreads > 1) {
1420        switch (commitPolicy) {
1421
1422          case Aggressive:
1423            //If Policy is Aggressive, commit will call
1424            //this function multiple times per
1425            //cycle
1426            return oldestReady();
1427
1428          case RoundRobin:
1429            return roundRobin();
1430
1431          case OldestReady:
1432            return oldestReady();
1433
1434          default:
1435            return InvalidThreadID;
1436        }
1437    } else {
1438        assert(!activeThreads->empty());
1439        ThreadID tid = activeThreads->front();
1440
1441        if (commitStatus[tid] == Running ||
1442            commitStatus[tid] == Idle ||
1443            commitStatus[tid] == FetchTrapPending) {
1444            return tid;
1445        } else {
1446            return InvalidThreadID;
1447        }
1448    }
1449}
1450
1451template<class Impl>
1452ThreadID
1453DefaultCommit<Impl>::roundRobin()
1454{
1455    list<ThreadID>::iterator pri_iter = priority_list.begin();
1456    list<ThreadID>::iterator end      = priority_list.end();
1457
1458    while (pri_iter != end) {
1459        ThreadID tid = *pri_iter;
1460
1461        if (commitStatus[tid] == Running ||
1462            commitStatus[tid] == Idle ||
1463            commitStatus[tid] == FetchTrapPending) {
1464
1465            if (rob->isHeadReady(tid)) {
1466                priority_list.erase(pri_iter);
1467                priority_list.push_back(tid);
1468
1469                return tid;
1470            }
1471        }
1472
1473        pri_iter++;
1474    }
1475
1476    return InvalidThreadID;
1477}
1478
1479template<class Impl>
1480ThreadID
1481DefaultCommit<Impl>::oldestReady()
1482{
1483    unsigned oldest = 0;
1484    bool first = true;
1485
1486    list<ThreadID>::iterator threads = activeThreads->begin();
1487    list<ThreadID>::iterator end = activeThreads->end();
1488
1489    while (threads != end) {
1490        ThreadID tid = *threads++;
1491
1492        if (!rob->isEmpty(tid) &&
1493            (commitStatus[tid] == Running ||
1494             commitStatus[tid] == Idle ||
1495             commitStatus[tid] == FetchTrapPending)) {
1496
1497            if (rob->isHeadReady(tid)) {
1498
1499                DynInstPtr head_inst = rob->readHeadInst(tid);
1500
1501                if (first) {
1502                    oldest = tid;
1503                    first = false;
1504                } else if (head_inst->seqNum < oldest) {
1505                    oldest = tid;
1506                }
1507            }
1508        }
1509    }
1510
1511    if (!first) {
1512        return oldest;
1513    } else {
1514        return InvalidThreadID;
1515    }
1516}
1517
1518#endif//__CPU_O3_COMMIT_IMPL_HH__
1519