commit_impl.hh revision 10730:11cb85883e6a
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2014 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44#ifndef __CPU_O3_COMMIT_IMPL_HH__ 45#define __CPU_O3_COMMIT_IMPL_HH__ 46 47#include <algorithm> 48#include <set> 49#include <string> 50 51#include "arch/utility.hh" 52#include "base/loader/symtab.hh" 53#include "base/cp_annotate.hh" 54#include "config/the_isa.hh" 55#include "cpu/checker/cpu.hh" 56#include "cpu/o3/commit.hh" 57#include "cpu/o3/thread_state.hh" 58#include "cpu/base.hh" 59#include "cpu/exetrace.hh" 60#include "cpu/timebuf.hh" 61#include "debug/Activity.hh" 62#include "debug/Commit.hh" 63#include "debug/CommitRate.hh" 64#include "debug/Drain.hh" 65#include "debug/ExecFaulting.hh" 66#include "debug/O3PipeView.hh" 67#include "params/DerivO3CPU.hh" 68#include "sim/faults.hh" 69#include "sim/full_system.hh" 70 71using namespace std; 72 73template <class Impl> 74DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 75 ThreadID _tid) 76 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 77{ 78} 79 80template <class Impl> 81void 82DefaultCommit<Impl>::TrapEvent::process() 83{ 84 // This will get reset by commit if it was switched out at the 85 // time of this event processing. 86 commit->trapSquash[tid] = true; 87} 88 89template <class Impl> 90const char * 91DefaultCommit<Impl>::TrapEvent::description() const 92{ 93 return "Trap"; 94} 95 96template <class Impl> 97DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 98 : cpu(_cpu), 99 iewToCommitDelay(params->iewToCommitDelay), 100 commitToIEWDelay(params->commitToIEWDelay), 101 renameToROBDelay(params->renameToROBDelay), 102 fetchToCommitDelay(params->commitToFetchDelay), 103 renameWidth(params->renameWidth), 104 commitWidth(params->commitWidth), 105 numThreads(params->numThreads), 106 drainPending(false), 107 drainImminent(false), 108 trapLatency(params->trapLatency), 109 canHandleInterrupts(true), 110 avoidQuiesceLiveLock(false) 111{ 112 if (commitWidth > Impl::MaxWidth) 113 fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 114 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 115 commitWidth, static_cast<int>(Impl::MaxWidth)); 116 117 _status = Active; 118 _nextStatus = Inactive; 119 std::string policy = params->smtCommitPolicy; 120 121 //Convert string to lowercase 122 std::transform(policy.begin(), policy.end(), policy.begin(), 123 (int(*)(int)) tolower); 124 125 //Assign commit policy 126 if (policy == "aggressive"){ 127 commitPolicy = Aggressive; 128 129 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 130 } else if (policy == "roundrobin"){ 131 commitPolicy = RoundRobin; 132 133 //Set-Up Priority List 134 for (ThreadID tid = 0; tid < numThreads; tid++) { 135 priority_list.push_back(tid); 136 } 137 138 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 139 } else if (policy == "oldestready"){ 140 commitPolicy = OldestReady; 141 142 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 143 } else { 144 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 145 "RoundRobin,OldestReady}"); 146 } 147 148 for (ThreadID tid = 0; tid < numThreads; tid++) { 149 commitStatus[tid] = Idle; 150 changedROBNumEntries[tid] = false; 151 checkEmptyROB[tid] = false; 152 trapInFlight[tid] = false; 153 committedStores[tid] = false; 154 trapSquash[tid] = false; 155 tcSquash[tid] = false; 156 pc[tid].set(0); 157 lastCommitedSeqNum[tid] = 0; 158 squashAfterInst[tid] = NULL; 159 } 160 interrupt = NoFault; 161} 162 163template <class Impl> 164std::string 165DefaultCommit<Impl>::name() const 166{ 167 return cpu->name() + ".commit"; 168} 169 170template <class Impl> 171void 172DefaultCommit<Impl>::regProbePoints() 173{ 174 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 175 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 176} 177 178template <class Impl> 179void 180DefaultCommit<Impl>::regStats() 181{ 182 using namespace Stats; 183 commitSquashedInsts 184 .name(name() + ".commitSquashedInsts") 185 .desc("The number of squashed insts skipped by commit") 186 .prereq(commitSquashedInsts); 187 commitSquashEvents 188 .name(name() + ".commitSquashEvents") 189 .desc("The number of times commit is told to squash") 190 .prereq(commitSquashEvents); 191 commitNonSpecStalls 192 .name(name() + ".commitNonSpecStalls") 193 .desc("The number of times commit has been forced to stall to " 194 "communicate backwards") 195 .prereq(commitNonSpecStalls); 196 branchMispredicts 197 .name(name() + ".branchMispredicts") 198 .desc("The number of times a branch was mispredicted") 199 .prereq(branchMispredicts); 200 numCommittedDist 201 .init(0,commitWidth,1) 202 .name(name() + ".committed_per_cycle") 203 .desc("Number of insts commited each cycle") 204 .flags(Stats::pdf) 205 ; 206 207 instsCommitted 208 .init(cpu->numThreads) 209 .name(name() + ".committedInsts") 210 .desc("Number of instructions committed") 211 .flags(total) 212 ; 213 214 opsCommitted 215 .init(cpu->numThreads) 216 .name(name() + ".committedOps") 217 .desc("Number of ops (including micro ops) committed") 218 .flags(total) 219 ; 220 221 statComSwp 222 .init(cpu->numThreads) 223 .name(name() + ".swp_count") 224 .desc("Number of s/w prefetches committed") 225 .flags(total) 226 ; 227 228 statComRefs 229 .init(cpu->numThreads) 230 .name(name() + ".refs") 231 .desc("Number of memory references committed") 232 .flags(total) 233 ; 234 235 statComLoads 236 .init(cpu->numThreads) 237 .name(name() + ".loads") 238 .desc("Number of loads committed") 239 .flags(total) 240 ; 241 242 statComMembars 243 .init(cpu->numThreads) 244 .name(name() + ".membars") 245 .desc("Number of memory barriers committed") 246 .flags(total) 247 ; 248 249 statComBranches 250 .init(cpu->numThreads) 251 .name(name() + ".branches") 252 .desc("Number of branches committed") 253 .flags(total) 254 ; 255 256 statComFloating 257 .init(cpu->numThreads) 258 .name(name() + ".fp_insts") 259 .desc("Number of committed floating point instructions.") 260 .flags(total) 261 ; 262 263 statComInteger 264 .init(cpu->numThreads) 265 .name(name()+".int_insts") 266 .desc("Number of committed integer instructions.") 267 .flags(total) 268 ; 269 270 statComFunctionCalls 271 .init(cpu->numThreads) 272 .name(name()+".function_calls") 273 .desc("Number of function calls committed.") 274 .flags(total) 275 ; 276 277 statCommittedInstType 278 .init(numThreads,Enums::Num_OpClass) 279 .name(name() + ".op_class") 280 .desc("Class of committed instruction") 281 .flags(total | pdf | dist) 282 ; 283 statCommittedInstType.ysubnames(Enums::OpClassStrings); 284 285 commitEligible 286 .init(cpu->numThreads) 287 .name(name() + ".bw_limited") 288 .desc("number of insts not committed due to BW limits") 289 .flags(total) 290 ; 291 292 commitEligibleSamples 293 .name(name() + ".bw_lim_events") 294 .desc("number cycles where commit BW limit reached") 295 ; 296} 297 298template <class Impl> 299void 300DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 301{ 302 thread = threads; 303} 304 305template <class Impl> 306void 307DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 308{ 309 timeBuffer = tb_ptr; 310 311 // Setup wire to send information back to IEW. 312 toIEW = timeBuffer->getWire(0); 313 314 // Setup wire to read data from IEW (for the ROB). 315 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 316} 317 318template <class Impl> 319void 320DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 321{ 322 fetchQueue = fq_ptr; 323 324 // Setup wire to get instructions from rename (for the ROB). 325 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 326} 327 328template <class Impl> 329void 330DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 331{ 332 renameQueue = rq_ptr; 333 334 // Setup wire to get instructions from rename (for the ROB). 335 fromRename = renameQueue->getWire(-renameToROBDelay); 336} 337 338template <class Impl> 339void 340DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 341{ 342 iewQueue = iq_ptr; 343 344 // Setup wire to get instructions from IEW. 345 fromIEW = iewQueue->getWire(-iewToCommitDelay); 346} 347 348template <class Impl> 349void 350DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 351{ 352 iewStage = iew_stage; 353} 354 355template<class Impl> 356void 357DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 358{ 359 activeThreads = at_ptr; 360} 361 362template <class Impl> 363void 364DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 365{ 366 for (ThreadID tid = 0; tid < numThreads; tid++) 367 renameMap[tid] = &rm_ptr[tid]; 368} 369 370template <class Impl> 371void 372DefaultCommit<Impl>::setROB(ROB *rob_ptr) 373{ 374 rob = rob_ptr; 375} 376 377template <class Impl> 378void 379DefaultCommit<Impl>::startupStage() 380{ 381 rob->setActiveThreads(activeThreads); 382 rob->resetEntries(); 383 384 // Broadcast the number of free entries. 385 for (ThreadID tid = 0; tid < numThreads; tid++) { 386 toIEW->commitInfo[tid].usedROB = true; 387 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 388 toIEW->commitInfo[tid].emptyROB = true; 389 } 390 391 // Commit must broadcast the number of free entries it has at the 392 // start of the simulation, so it starts as active. 393 cpu->activateStage(O3CPU::CommitIdx); 394 395 cpu->activityThisCycle(); 396} 397 398template <class Impl> 399void 400DefaultCommit<Impl>::drain() 401{ 402 drainPending = true; 403} 404 405template <class Impl> 406void 407DefaultCommit<Impl>::drainResume() 408{ 409 drainPending = false; 410 drainImminent = false; 411} 412 413template <class Impl> 414void 415DefaultCommit<Impl>::drainSanityCheck() const 416{ 417 assert(isDrained()); 418 rob->drainSanityCheck(); 419} 420 421template <class Impl> 422bool 423DefaultCommit<Impl>::isDrained() const 424{ 425 /* Make sure no one is executing microcode. There are two reasons 426 * for this: 427 * - Hardware virtualized CPUs can't switch into the middle of a 428 * microcode sequence. 429 * - The current fetch implementation will most likely get very 430 * confused if it tries to start fetching an instruction that 431 * is executing in the middle of a ucode sequence that changes 432 * address mappings. This can happen on for example x86. 433 */ 434 for (ThreadID tid = 0; tid < numThreads; tid++) { 435 if (pc[tid].microPC() != 0) 436 return false; 437 } 438 439 /* Make sure that all instructions have finished committing before 440 * declaring the system as drained. We want the pipeline to be 441 * completely empty when we declare the CPU to be drained. This 442 * makes debugging easier since CPU handover and restoring from a 443 * checkpoint with a different CPU should have the same timing. 444 */ 445 return rob->isEmpty() && 446 interrupt == NoFault; 447} 448 449template <class Impl> 450void 451DefaultCommit<Impl>::takeOverFrom() 452{ 453 _status = Active; 454 _nextStatus = Inactive; 455 for (ThreadID tid = 0; tid < numThreads; tid++) { 456 commitStatus[tid] = Idle; 457 changedROBNumEntries[tid] = false; 458 trapSquash[tid] = false; 459 tcSquash[tid] = false; 460 squashAfterInst[tid] = NULL; 461 } 462 rob->takeOverFrom(); 463} 464 465template <class Impl> 466void 467DefaultCommit<Impl>::deactivateThread(ThreadID tid) 468{ 469 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(), 470 priority_list.end(), tid); 471 472 if (thread_it != priority_list.end()) { 473 priority_list.erase(thread_it); 474 } 475} 476 477 478template <class Impl> 479void 480DefaultCommit<Impl>::updateStatus() 481{ 482 // reset ROB changed variable 483 list<ThreadID>::iterator threads = activeThreads->begin(); 484 list<ThreadID>::iterator end = activeThreads->end(); 485 486 while (threads != end) { 487 ThreadID tid = *threads++; 488 489 changedROBNumEntries[tid] = false; 490 491 // Also check if any of the threads has a trap pending 492 if (commitStatus[tid] == TrapPending || 493 commitStatus[tid] == FetchTrapPending) { 494 _nextStatus = Active; 495 } 496 } 497 498 if (_nextStatus == Inactive && _status == Active) { 499 DPRINTF(Activity, "Deactivating stage.\n"); 500 cpu->deactivateStage(O3CPU::CommitIdx); 501 } else if (_nextStatus == Active && _status == Inactive) { 502 DPRINTF(Activity, "Activating stage.\n"); 503 cpu->activateStage(O3CPU::CommitIdx); 504 } 505 506 _status = _nextStatus; 507} 508 509template <class Impl> 510bool 511DefaultCommit<Impl>::changedROBEntries() 512{ 513 list<ThreadID>::iterator threads = activeThreads->begin(); 514 list<ThreadID>::iterator end = activeThreads->end(); 515 516 while (threads != end) { 517 ThreadID tid = *threads++; 518 519 if (changedROBNumEntries[tid]) { 520 return true; 521 } 522 } 523 524 return false; 525} 526 527template <class Impl> 528size_t 529DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 530{ 531 return rob->numFreeEntries(tid); 532} 533 534template <class Impl> 535void 536DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 537{ 538 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 539 540 TrapEvent *trap = new TrapEvent(this, tid); 541 542 cpu->schedule(trap, cpu->clockEdge(trapLatency)); 543 trapInFlight[tid] = true; 544 thread[tid]->trapPending = true; 545} 546 547template <class Impl> 548void 549DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 550{ 551 assert(!trapInFlight[tid]); 552 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 553 554 tcSquash[tid] = true; 555} 556 557template <class Impl> 558void 559DefaultCommit<Impl>::squashAll(ThreadID tid) 560{ 561 // If we want to include the squashing instruction in the squash, 562 // then use one older sequence number. 563 // Hopefully this doesn't mess things up. Basically I want to squash 564 // all instructions of this thread. 565 InstSeqNum squashed_inst = rob->isEmpty(tid) ? 566 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 567 568 // All younger instructions will be squashed. Set the sequence 569 // number as the youngest instruction in the ROB (0 in this case. 570 // Hopefully nothing breaks.) 571 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 572 573 rob->squash(squashed_inst, tid); 574 changedROBNumEntries[tid] = true; 575 576 // Send back the sequence number of the squashed instruction. 577 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 578 579 // Send back the squash signal to tell stages that they should 580 // squash. 581 toIEW->commitInfo[tid].squash = true; 582 583 // Send back the rob squashing signal so other stages know that 584 // the ROB is in the process of squashing. 585 toIEW->commitInfo[tid].robSquashing = true; 586 587 toIEW->commitInfo[tid].mispredictInst = NULL; 588 toIEW->commitInfo[tid].squashInst = NULL; 589 590 toIEW->commitInfo[tid].pc = pc[tid]; 591} 592 593template <class Impl> 594void 595DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 596{ 597 squashAll(tid); 598 599 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 600 601 thread[tid]->trapPending = false; 602 thread[tid]->noSquashFromTC = false; 603 trapInFlight[tid] = false; 604 605 trapSquash[tid] = false; 606 607 commitStatus[tid] = ROBSquashing; 608 cpu->activityThisCycle(); 609} 610 611template <class Impl> 612void 613DefaultCommit<Impl>::squashFromTC(ThreadID tid) 614{ 615 squashAll(tid); 616 617 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 618 619 thread[tid]->noSquashFromTC = false; 620 assert(!thread[tid]->trapPending); 621 622 commitStatus[tid] = ROBSquashing; 623 cpu->activityThisCycle(); 624 625 tcSquash[tid] = false; 626} 627 628template <class Impl> 629void 630DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 631{ 632 DPRINTF(Commit, "Squashing after squash after request, " 633 "restarting at PC %s\n", pc[tid]); 634 635 squashAll(tid); 636 // Make sure to inform the fetch stage of which instruction caused 637 // the squash. It'll try to re-fetch an instruction executing in 638 // microcode unless this is set. 639 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 640 squashAfterInst[tid] = NULL; 641 642 commitStatus[tid] = ROBSquashing; 643 cpu->activityThisCycle(); 644} 645 646template <class Impl> 647void 648DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 649{ 650 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 651 tid, head_inst->seqNum); 652 653 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 654 commitStatus[tid] = SquashAfterPending; 655 squashAfterInst[tid] = head_inst; 656} 657 658template <class Impl> 659void 660DefaultCommit<Impl>::tick() 661{ 662 wroteToTimeBuffer = false; 663 _nextStatus = Inactive; 664 665 if (activeThreads->empty()) 666 return; 667 668 list<ThreadID>::iterator threads = activeThreads->begin(); 669 list<ThreadID>::iterator end = activeThreads->end(); 670 671 // Check if any of the threads are done squashing. Change the 672 // status if they are done. 673 while (threads != end) { 674 ThreadID tid = *threads++; 675 676 // Clear the bit saying if the thread has committed stores 677 // this cycle. 678 committedStores[tid] = false; 679 680 if (commitStatus[tid] == ROBSquashing) { 681 682 if (rob->isDoneSquashing(tid)) { 683 commitStatus[tid] = Running; 684 } else { 685 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 686 " insts this cycle.\n", tid); 687 rob->doSquash(tid); 688 toIEW->commitInfo[tid].robSquashing = true; 689 wroteToTimeBuffer = true; 690 } 691 } 692 } 693 694 commit(); 695 696 markCompletedInsts(); 697 698 threads = activeThreads->begin(); 699 700 while (threads != end) { 701 ThreadID tid = *threads++; 702 703 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 704 // The ROB has more instructions it can commit. Its next status 705 // will be active. 706 _nextStatus = Active; 707 708 DynInstPtr inst = rob->readHeadInst(tid); 709 710 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 711 " ROB and ready to commit\n", 712 tid, inst->seqNum, inst->pcState()); 713 714 } else if (!rob->isEmpty(tid)) { 715 DynInstPtr inst = rob->readHeadInst(tid); 716 717 ppCommitStall->notify(inst); 718 719 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 720 "%s is head of ROB and not ready\n", 721 tid, inst->seqNum, inst->pcState()); 722 } 723 724 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 725 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 726 } 727 728 729 if (wroteToTimeBuffer) { 730 DPRINTF(Activity, "Activity This Cycle.\n"); 731 cpu->activityThisCycle(); 732 } 733 734 updateStatus(); 735} 736 737template <class Impl> 738void 739DefaultCommit<Impl>::handleInterrupt() 740{ 741 // Verify that we still have an interrupt to handle 742 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 743 DPRINTF(Commit, "Pending interrupt is cleared by master before " 744 "it got handled. Restart fetching from the orig path.\n"); 745 toIEW->commitInfo[0].clearInterrupt = true; 746 interrupt = NoFault; 747 avoidQuiesceLiveLock = true; 748 return; 749 } 750 751 // Wait until all in flight instructions are finished before enterring 752 // the interrupt. 753 if (canHandleInterrupts && cpu->instList.empty()) { 754 // Squash or record that I need to squash this cycle if 755 // an interrupt needed to be handled. 756 DPRINTF(Commit, "Interrupt detected.\n"); 757 758 // Clear the interrupt now that it's going to be handled 759 toIEW->commitInfo[0].clearInterrupt = true; 760 761 assert(!thread[0]->noSquashFromTC); 762 thread[0]->noSquashFromTC = true; 763 764 if (cpu->checker) { 765 cpu->checker->handlePendingInt(); 766 } 767 768 // CPU will handle interrupt. Note that we ignore the local copy of 769 // interrupt. This is because the local copy may no longer be the 770 // interrupt that the interrupt controller thinks is being handled. 771 cpu->processInterrupts(cpu->getInterrupts()); 772 773 thread[0]->noSquashFromTC = false; 774 775 commitStatus[0] = TrapPending; 776 777 // Generate trap squash event. 778 generateTrapEvent(0); 779 780 interrupt = NoFault; 781 avoidQuiesceLiveLock = false; 782 } else { 783 DPRINTF(Commit, "Interrupt pending: instruction is %sin " 784 "flight, ROB is %sempty\n", 785 canHandleInterrupts ? "not " : "", 786 cpu->instList.empty() ? "" : "not " ); 787 } 788} 789 790template <class Impl> 791void 792DefaultCommit<Impl>::propagateInterrupt() 793{ 794 // Don't propagate intterupts if we are currently handling a trap or 795 // in draining and the last observable instruction has been committed. 796 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 797 tcSquash[0] || drainImminent) 798 return; 799 800 // Process interrupts if interrupts are enabled, not in PAL 801 // mode, and no other traps or external squashes are currently 802 // pending. 803 // @todo: Allow other threads to handle interrupts. 804 805 // Get any interrupt that happened 806 interrupt = cpu->getInterrupts(); 807 808 // Tell fetch that there is an interrupt pending. This 809 // will make fetch wait until it sees a non PAL-mode PC, 810 // at which point it stops fetching instructions. 811 if (interrupt != NoFault) 812 toIEW->commitInfo[0].interruptPending = true; 813} 814 815template <class Impl> 816void 817DefaultCommit<Impl>::commit() 818{ 819 if (FullSystem) { 820 // Check if we have a interrupt and get read to handle it 821 if (cpu->checkInterrupts(cpu->tcBase(0))) 822 propagateInterrupt(); 823 } 824 825 //////////////////////////////////// 826 // Check for any possible squashes, handle them first 827 //////////////////////////////////// 828 list<ThreadID>::iterator threads = activeThreads->begin(); 829 list<ThreadID>::iterator end = activeThreads->end(); 830 831 int num_squashing_threads = 0; 832 833 while (threads != end) { 834 ThreadID tid = *threads++; 835 836 // Not sure which one takes priority. I think if we have 837 // both, that's a bad sign. 838 if (trapSquash[tid]) { 839 assert(!tcSquash[tid]); 840 squashFromTrap(tid); 841 } else if (tcSquash[tid]) { 842 assert(commitStatus[tid] != TrapPending); 843 squashFromTC(tid); 844 } else if (commitStatus[tid] == SquashAfterPending) { 845 // A squash from the previous cycle of the commit stage (i.e., 846 // commitInsts() called squashAfter) is pending. Squash the 847 // thread now. 848 squashFromSquashAfter(tid); 849 } 850 851 // Squashed sequence number must be older than youngest valid 852 // instruction in the ROB. This prevents squashes from younger 853 // instructions overriding squashes from older instructions. 854 if (fromIEW->squash[tid] && 855 commitStatus[tid] != TrapPending && 856 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 857 858 if (fromIEW->mispredictInst[tid]) { 859 DPRINTF(Commit, 860 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 861 tid, 862 fromIEW->mispredictInst[tid]->instAddr(), 863 fromIEW->squashedSeqNum[tid]); 864 } else { 865 DPRINTF(Commit, 866 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 867 tid, fromIEW->squashedSeqNum[tid]); 868 } 869 870 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 871 tid, 872 fromIEW->pc[tid].nextInstAddr()); 873 874 commitStatus[tid] = ROBSquashing; 875 876 // If we want to include the squashing instruction in the squash, 877 // then use one older sequence number. 878 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 879 880 if (fromIEW->includeSquashInst[tid]) { 881 squashed_inst--; 882 } 883 884 // All younger instructions will be squashed. Set the sequence 885 // number as the youngest instruction in the ROB. 886 youngestSeqNum[tid] = squashed_inst; 887 888 rob->squash(squashed_inst, tid); 889 changedROBNumEntries[tid] = true; 890 891 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 892 893 toIEW->commitInfo[tid].squash = true; 894 895 // Send back the rob squashing signal so other stages know that 896 // the ROB is in the process of squashing. 897 toIEW->commitInfo[tid].robSquashing = true; 898 899 toIEW->commitInfo[tid].mispredictInst = 900 fromIEW->mispredictInst[tid]; 901 toIEW->commitInfo[tid].branchTaken = 902 fromIEW->branchTaken[tid]; 903 toIEW->commitInfo[tid].squashInst = 904 rob->findInst(tid, squashed_inst); 905 if (toIEW->commitInfo[tid].mispredictInst) { 906 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 907 toIEW->commitInfo[tid].branchTaken = true; 908 } 909 ++branchMispredicts; 910 } 911 912 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 913 } 914 915 if (commitStatus[tid] == ROBSquashing) { 916 num_squashing_threads++; 917 } 918 } 919 920 // If commit is currently squashing, then it will have activity for the 921 // next cycle. Set its next status as active. 922 if (num_squashing_threads) { 923 _nextStatus = Active; 924 } 925 926 if (num_squashing_threads != numThreads) { 927 // If we're not currently squashing, then get instructions. 928 getInsts(); 929 930 // Try to commit any instructions. 931 commitInsts(); 932 } 933 934 //Check for any activity 935 threads = activeThreads->begin(); 936 937 while (threads != end) { 938 ThreadID tid = *threads++; 939 940 if (changedROBNumEntries[tid]) { 941 toIEW->commitInfo[tid].usedROB = true; 942 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 943 944 wroteToTimeBuffer = true; 945 changedROBNumEntries[tid] = false; 946 if (rob->isEmpty(tid)) 947 checkEmptyROB[tid] = true; 948 } 949 950 // ROB is only considered "empty" for previous stages if: a) 951 // ROB is empty, b) there are no outstanding stores, c) IEW 952 // stage has received any information regarding stores that 953 // committed. 954 // c) is checked by making sure to not consider the ROB empty 955 // on the same cycle as when stores have been committed. 956 // @todo: Make this handle multi-cycle communication between 957 // commit and IEW. 958 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 959 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 960 checkEmptyROB[tid] = false; 961 toIEW->commitInfo[tid].usedROB = true; 962 toIEW->commitInfo[tid].emptyROB = true; 963 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 964 wroteToTimeBuffer = true; 965 } 966 967 } 968} 969 970template <class Impl> 971void 972DefaultCommit<Impl>::commitInsts() 973{ 974 //////////////////////////////////// 975 // Handle commit 976 // Note that commit will be handled prior to putting new 977 // instructions in the ROB so that the ROB only tries to commit 978 // instructions it has in this current cycle, and not instructions 979 // it is writing in during this cycle. Can't commit and squash 980 // things at the same time... 981 //////////////////////////////////// 982 983 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 984 985 unsigned num_committed = 0; 986 987 DynInstPtr head_inst; 988 989 // Commit as many instructions as possible until the commit bandwidth 990 // limit is reached, or it becomes impossible to commit any more. 991 while (num_committed < commitWidth) { 992 // Check for any interrupt that we've already squashed for 993 // and start processing it. 994 if (interrupt != NoFault) 995 handleInterrupt(); 996 997 int commit_thread = getCommittingThread(); 998 999 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 1000 break; 1001 1002 head_inst = rob->readHeadInst(commit_thread); 1003 1004 ThreadID tid = head_inst->threadNumber; 1005 1006 assert(tid == commit_thread); 1007 1008 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 1009 head_inst->seqNum, tid); 1010 1011 // If the head instruction is squashed, it is ready to retire 1012 // (be removed from the ROB) at any time. 1013 if (head_inst->isSquashed()) { 1014 1015 DPRINTF(Commit, "Retiring squashed instruction from " 1016 "ROB.\n"); 1017 1018 rob->retireHead(commit_thread); 1019 1020 ++commitSquashedInsts; 1021 1022 // Record that the number of ROB entries has changed. 1023 changedROBNumEntries[tid] = true; 1024 } else { 1025 pc[tid] = head_inst->pcState(); 1026 1027 // Increment the total number of non-speculative instructions 1028 // executed. 1029 // Hack for now: it really shouldn't happen until after the 1030 // commit is deemed to be successful, but this count is needed 1031 // for syscalls. 1032 thread[tid]->funcExeInst++; 1033 1034 // Try to commit the head instruction. 1035 bool commit_success = commitHead(head_inst, num_committed); 1036 1037 if (commit_success) { 1038 ++num_committed; 1039 statCommittedInstType[tid][head_inst->opClass()]++; 1040 ppCommit->notify(head_inst); 1041 1042 changedROBNumEntries[tid] = true; 1043 1044 // Set the doneSeqNum to the youngest committed instruction. 1045 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 1046 1047 if (tid == 0) { 1048 canHandleInterrupts = (!head_inst->isDelayedCommit()) && 1049 ((THE_ISA != ALPHA_ISA) || 1050 (!(pc[0].instAddr() & 0x3))); 1051 } 1052 1053 // Updates misc. registers. 1054 head_inst->updateMiscRegs(); 1055 1056 // Check instruction execution if it successfully commits and 1057 // is not carrying a fault. 1058 if (cpu->checker) { 1059 cpu->checker->verify(head_inst); 1060 } 1061 1062 cpu->traceFunctions(pc[tid].instAddr()); 1063 1064 TheISA::advancePC(pc[tid], head_inst->staticInst); 1065 1066 // Keep track of the last sequence number commited 1067 lastCommitedSeqNum[tid] = head_inst->seqNum; 1068 1069 // If this is an instruction that doesn't play nicely with 1070 // others squash everything and restart fetch 1071 if (head_inst->isSquashAfter()) 1072 squashAfter(tid, head_inst); 1073 1074 if (drainPending) { 1075 if (pc[tid].microPC() == 0 && interrupt == NoFault && 1076 !thread[tid]->trapPending) { 1077 // Last architectually committed instruction. 1078 // Squash the pipeline, stall fetch, and use 1079 // drainImminent to disable interrupts 1080 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 1081 squashAfter(tid, head_inst); 1082 cpu->commitDrained(tid); 1083 drainImminent = true; 1084 } 1085 } 1086 1087 bool onInstBoundary = !head_inst->isMicroop() || 1088 head_inst->isLastMicroop() || 1089 !head_inst->isDelayedCommit(); 1090 1091 if (onInstBoundary) { 1092 int count = 0; 1093 Addr oldpc; 1094 // Make sure we're not currently updating state while 1095 // handling PC events. 1096 assert(!thread[tid]->noSquashFromTC && 1097 !thread[tid]->trapPending); 1098 do { 1099 oldpc = pc[tid].instAddr(); 1100 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1101 count++; 1102 } while (oldpc != pc[tid].instAddr()); 1103 if (count > 1) { 1104 DPRINTF(Commit, 1105 "PC skip function event, stopping commit\n"); 1106 break; 1107 } 1108 } 1109 1110 // Check if an instruction just enabled interrupts and we've 1111 // previously had an interrupt pending that was not handled 1112 // because interrupts were subsequently disabled before the 1113 // pipeline reached a place to handle the interrupt. In that 1114 // case squash now to make sure the interrupt is handled. 1115 // 1116 // If we don't do this, we might end up in a live lock situation 1117 if (!interrupt && avoidQuiesceLiveLock && 1118 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0))) 1119 squashAfter(tid, head_inst); 1120 } else { 1121 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1122 "[tid:%i] [sn:%i].\n", 1123 head_inst->pcState(), tid ,head_inst->seqNum); 1124 break; 1125 } 1126 } 1127 } 1128 1129 DPRINTF(CommitRate, "%i\n", num_committed); 1130 numCommittedDist.sample(num_committed); 1131 1132 if (num_committed == commitWidth) { 1133 commitEligibleSamples++; 1134 } 1135} 1136 1137template <class Impl> 1138bool 1139DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1140{ 1141 assert(head_inst); 1142 1143 ThreadID tid = head_inst->threadNumber; 1144 1145 // If the instruction is not executed yet, then it will need extra 1146 // handling. Signal backwards that it should be executed. 1147 if (!head_inst->isExecuted()) { 1148 // Keep this number correct. We have not yet actually executed 1149 // and committed this instruction. 1150 thread[tid]->funcExeInst--; 1151 1152 // Make sure we are only trying to commit un-executed instructions we 1153 // think are possible. 1154 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 1155 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 1156 (head_inst->isLoad() && head_inst->uncacheable())); 1157 1158 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1159 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1160 head_inst->seqNum, head_inst->pcState()); 1161 1162 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1163 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1164 return false; 1165 } 1166 1167 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1168 1169 // Change the instruction so it won't try to commit again until 1170 // it is executed. 1171 head_inst->clearCanCommit(); 1172 1173 if (head_inst->isLoad() && head_inst->uncacheable()) { 1174 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1175 head_inst->seqNum, head_inst->pcState()); 1176 toIEW->commitInfo[tid].uncached = true; 1177 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1178 } else { 1179 ++commitNonSpecStalls; 1180 } 1181 1182 return false; 1183 } 1184 1185 if (head_inst->isThreadSync()) { 1186 // Not handled for now. 1187 panic("Thread sync instructions are not handled yet.\n"); 1188 } 1189 1190 // Check if the instruction caused a fault. If so, trap. 1191 Fault inst_fault = head_inst->getFault(); 1192 1193 // Stores mark themselves as completed. 1194 if (!head_inst->isStore() && inst_fault == NoFault) { 1195 head_inst->setCompleted(); 1196 } 1197 1198 if (inst_fault != NoFault) { 1199 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1200 head_inst->seqNum, head_inst->pcState()); 1201 1202 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1203 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1204 return false; 1205 } 1206 1207 head_inst->setCompleted(); 1208 1209 // If instruction has faulted, let the checker execute it and 1210 // check if it sees the same fault and control flow. 1211 if (cpu->checker) { 1212 // Need to check the instruction before its fault is processed 1213 cpu->checker->verify(head_inst); 1214 } 1215 1216 assert(!thread[tid]->noSquashFromTC); 1217 1218 // Mark that we're in state update mode so that the trap's 1219 // execution doesn't generate extra squashes. 1220 thread[tid]->noSquashFromTC = true; 1221 1222 // Execute the trap. Although it's slightly unrealistic in 1223 // terms of timing (as it doesn't wait for the full timing of 1224 // the trap event to complete before updating state), it's 1225 // needed to update the state as soon as possible. This 1226 // prevents external agents from changing any specific state 1227 // that the trap need. 1228 cpu->trap(inst_fault, tid, head_inst->staticInst); 1229 1230 // Exit state update mode to avoid accidental updating. 1231 thread[tid]->noSquashFromTC = false; 1232 1233 commitStatus[tid] = TrapPending; 1234 1235 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1236 head_inst->seqNum); 1237 if (head_inst->traceData) { 1238 if (DTRACE(ExecFaulting)) { 1239 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1240 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1241 head_inst->traceData->dump(); 1242 } 1243 delete head_inst->traceData; 1244 head_inst->traceData = NULL; 1245 } 1246 1247 // Generate trap squash event. 1248 generateTrapEvent(tid); 1249 return false; 1250 } 1251 1252 updateComInstStats(head_inst); 1253 1254 if (FullSystem) { 1255 if (thread[tid]->profile) { 1256 thread[tid]->profilePC = head_inst->instAddr(); 1257 ProfileNode *node = thread[tid]->profile->consume( 1258 thread[tid]->getTC(), head_inst->staticInst); 1259 1260 if (node) 1261 thread[tid]->profileNode = node; 1262 } 1263 if (CPA::available()) { 1264 if (head_inst->isControl()) { 1265 ThreadContext *tc = thread[tid]->getTC(); 1266 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1267 } 1268 } 1269 } 1270 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1271 head_inst->seqNum, head_inst->pcState()); 1272 if (head_inst->traceData) { 1273 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1274 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1275 head_inst->traceData->dump(); 1276 delete head_inst->traceData; 1277 head_inst->traceData = NULL; 1278 } 1279 if (head_inst->isReturn()) { 1280 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 1281 head_inst->seqNum, head_inst->pcState()); 1282 } 1283 1284 // Update the commit rename map 1285 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1286 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1287 head_inst->renamedDestRegIdx(i)); 1288 } 1289 1290 // Finally clear the head ROB entry. 1291 rob->retireHead(tid); 1292 1293#if TRACING_ON 1294 if (DTRACE(O3PipeView)) { 1295 head_inst->commitTick = curTick() - head_inst->fetchTick; 1296 } 1297#endif 1298 1299 // If this was a store, record it for this cycle. 1300 if (head_inst->isStore()) 1301 committedStores[tid] = true; 1302 1303 // Return true to indicate that we have committed an instruction. 1304 return true; 1305} 1306 1307template <class Impl> 1308void 1309DefaultCommit<Impl>::getInsts() 1310{ 1311 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1312 1313 // Read any renamed instructions and place them into the ROB. 1314 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1315 1316 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1317 DynInstPtr inst; 1318 1319 inst = fromRename->insts[inst_num]; 1320 ThreadID tid = inst->threadNumber; 1321 1322 if (!inst->isSquashed() && 1323 commitStatus[tid] != ROBSquashing && 1324 commitStatus[tid] != TrapPending) { 1325 changedROBNumEntries[tid] = true; 1326 1327 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1328 inst->pcState(), inst->seqNum, tid); 1329 1330 rob->insertInst(inst); 1331 1332 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1333 1334 youngestSeqNum[tid] = inst->seqNum; 1335 } else { 1336 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1337 "squashed, skipping.\n", 1338 inst->pcState(), inst->seqNum, tid); 1339 } 1340 } 1341} 1342 1343template <class Impl> 1344void 1345DefaultCommit<Impl>::markCompletedInsts() 1346{ 1347 // Grab completed insts out of the IEW instruction queue, and mark 1348 // instructions completed within the ROB. 1349 for (int inst_num = 0; 1350 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1351 ++inst_num) 1352 { 1353 if (!fromIEW->insts[inst_num]->isSquashed()) { 1354 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1355 "within ROB.\n", 1356 fromIEW->insts[inst_num]->threadNumber, 1357 fromIEW->insts[inst_num]->pcState(), 1358 fromIEW->insts[inst_num]->seqNum); 1359 1360 // Mark the instruction as ready to commit. 1361 fromIEW->insts[inst_num]->setCanCommit(); 1362 } 1363 } 1364} 1365 1366template <class Impl> 1367void 1368DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1369{ 1370 ThreadID tid = inst->threadNumber; 1371 1372 if (!inst->isMicroop() || inst->isLastMicroop()) 1373 instsCommitted[tid]++; 1374 opsCommitted[tid]++; 1375 1376 // To match the old model, don't count nops and instruction 1377 // prefetches towards the total commit count. 1378 if (!inst->isNop() && !inst->isInstPrefetch()) { 1379 cpu->instDone(tid, inst); 1380 } 1381 1382 // 1383 // Control Instructions 1384 // 1385 if (inst->isControl()) 1386 statComBranches[tid]++; 1387 1388 // 1389 // Memory references 1390 // 1391 if (inst->isMemRef()) { 1392 statComRefs[tid]++; 1393 1394 if (inst->isLoad()) { 1395 statComLoads[tid]++; 1396 } 1397 } 1398 1399 if (inst->isMemBarrier()) { 1400 statComMembars[tid]++; 1401 } 1402 1403 // Integer Instruction 1404 if (inst->isInteger()) 1405 statComInteger[tid]++; 1406 1407 // Floating Point Instruction 1408 if (inst->isFloating()) 1409 statComFloating[tid]++; 1410 1411 // Function Calls 1412 if (inst->isCall()) 1413 statComFunctionCalls[tid]++; 1414 1415} 1416 1417//////////////////////////////////////// 1418// // 1419// SMT COMMIT POLICY MAINTAINED HERE // 1420// // 1421//////////////////////////////////////// 1422template <class Impl> 1423ThreadID 1424DefaultCommit<Impl>::getCommittingThread() 1425{ 1426 if (numThreads > 1) { 1427 switch (commitPolicy) { 1428 1429 case Aggressive: 1430 //If Policy is Aggressive, commit will call 1431 //this function multiple times per 1432 //cycle 1433 return oldestReady(); 1434 1435 case RoundRobin: 1436 return roundRobin(); 1437 1438 case OldestReady: 1439 return oldestReady(); 1440 1441 default: 1442 return InvalidThreadID; 1443 } 1444 } else { 1445 assert(!activeThreads->empty()); 1446 ThreadID tid = activeThreads->front(); 1447 1448 if (commitStatus[tid] == Running || 1449 commitStatus[tid] == Idle || 1450 commitStatus[tid] == FetchTrapPending) { 1451 return tid; 1452 } else { 1453 return InvalidThreadID; 1454 } 1455 } 1456} 1457 1458template<class Impl> 1459ThreadID 1460DefaultCommit<Impl>::roundRobin() 1461{ 1462 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1463 list<ThreadID>::iterator end = priority_list.end(); 1464 1465 while (pri_iter != end) { 1466 ThreadID tid = *pri_iter; 1467 1468 if (commitStatus[tid] == Running || 1469 commitStatus[tid] == Idle || 1470 commitStatus[tid] == FetchTrapPending) { 1471 1472 if (rob->isHeadReady(tid)) { 1473 priority_list.erase(pri_iter); 1474 priority_list.push_back(tid); 1475 1476 return tid; 1477 } 1478 } 1479 1480 pri_iter++; 1481 } 1482 1483 return InvalidThreadID; 1484} 1485 1486template<class Impl> 1487ThreadID 1488DefaultCommit<Impl>::oldestReady() 1489{ 1490 unsigned oldest = 0; 1491 bool first = true; 1492 1493 list<ThreadID>::iterator threads = activeThreads->begin(); 1494 list<ThreadID>::iterator end = activeThreads->end(); 1495 1496 while (threads != end) { 1497 ThreadID tid = *threads++; 1498 1499 if (!rob->isEmpty(tid) && 1500 (commitStatus[tid] == Running || 1501 commitStatus[tid] == Idle || 1502 commitStatus[tid] == FetchTrapPending)) { 1503 1504 if (rob->isHeadReady(tid)) { 1505 1506 DynInstPtr head_inst = rob->readHeadInst(tid); 1507 1508 if (first) { 1509 oldest = tid; 1510 first = false; 1511 } else if (head_inst->seqNum < oldest) { 1512 oldest = tid; 1513 } 1514 } 1515 } 1516 } 1517 1518 if (!first) { 1519 return oldest; 1520 } else { 1521 return InvalidThreadID; 1522 } 1523} 1524 1525#endif//__CPU_O3_COMMIT_IMPL_HH__ 1526