commit_impl.hh revision 10596:1eec33d2fc52 
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2014 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44#ifndef __CPU_O3_COMMIT_IMPL_HH__
45#define __CPU_O3_COMMIT_IMPL_HH__
46
47#include <algorithm>
48#include <set>
49#include <string>
50
51#include "arch/utility.hh"
52#include "base/loader/symtab.hh"
53#include "base/cp_annotate.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/commit.hh"
57#include "cpu/o3/thread_state.hh"
58#include "cpu/base.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/timebuf.hh"
61#include "debug/Activity.hh"
62#include "debug/Commit.hh"
63#include "debug/CommitRate.hh"
64#include "debug/Drain.hh"
65#include "debug/ExecFaulting.hh"
66#include "debug/O3PipeView.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/faults.hh"
69#include "sim/full_system.hh"
70
71using namespace std;
72
73template <class Impl>
74DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
75                                          ThreadID _tid)
76    : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
77{
78}
79
80template <class Impl>
81void
82DefaultCommit<Impl>::TrapEvent::process()
83{
84    // This will get reset by commit if it was switched out at the
85    // time of this event processing.
86    commit->trapSquash[tid] = true;
87}
88
89template <class Impl>
90const char *
91DefaultCommit<Impl>::TrapEvent::description() const
92{
93    return "Trap";
94}
95
96template <class Impl>
97DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
98    : cpu(_cpu),
99      squashCounter(0),
100      iewToCommitDelay(params->iewToCommitDelay),
101      commitToIEWDelay(params->commitToIEWDelay),
102      renameToROBDelay(params->renameToROBDelay),
103      fetchToCommitDelay(params->commitToFetchDelay),
104      renameWidth(params->renameWidth),
105      commitWidth(params->commitWidth),
106      numThreads(params->numThreads),
107      drainPending(false),
108      drainImminent(false),
109      trapLatency(params->trapLatency),
110      canHandleInterrupts(true),
111      avoidQuiesceLiveLock(false)
112{
113    if (commitWidth > Impl::MaxWidth)
114        fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
115             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
116             commitWidth, static_cast<int>(Impl::MaxWidth));
117
118    _status = Active;
119    _nextStatus = Inactive;
120    std::string policy = params->smtCommitPolicy;
121
122    //Convert string to lowercase
123    std::transform(policy.begin(), policy.end(), policy.begin(),
124                   (int(*)(int)) tolower);
125
126    //Assign commit policy
127    if (policy == "aggressive"){
128        commitPolicy = Aggressive;
129
130        DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
131    } else if (policy == "roundrobin"){
132        commitPolicy = RoundRobin;
133
134        //Set-Up Priority List
135        for (ThreadID tid = 0; tid < numThreads; tid++) {
136            priority_list.push_back(tid);
137        }
138
139        DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
140    } else if (policy == "oldestready"){
141        commitPolicy = OldestReady;
142
143        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
144    } else {
145        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
146               "RoundRobin,OldestReady}");
147    }
148
149    for (ThreadID tid = 0; tid < numThreads; tid++) {
150        commitStatus[tid] = Idle;
151        changedROBNumEntries[tid] = false;
152        checkEmptyROB[tid] = false;
153        trapInFlight[tid] = false;
154        committedStores[tid] = false;
155        trapSquash[tid] = false;
156        tcSquash[tid] = false;
157        pc[tid].set(0);
158        lastCommitedSeqNum[tid] = 0;
159        squashAfterInst[tid] = NULL;
160    }
161    interrupt = NoFault;
162}
163
164template <class Impl>
165std::string
166DefaultCommit<Impl>::name() const
167{
168    return cpu->name() + ".commit";
169}
170
171template <class Impl>
172void
173DefaultCommit<Impl>::regProbePoints()
174{
175    ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
176    ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
177}
178
179template <class Impl>
180void
181DefaultCommit<Impl>::regStats()
182{
183    using namespace Stats;
184    commitSquashedInsts
185        .name(name() + ".commitSquashedInsts")
186        .desc("The number of squashed insts skipped by commit")
187        .prereq(commitSquashedInsts);
188    commitSquashEvents
189        .name(name() + ".commitSquashEvents")
190        .desc("The number of times commit is told to squash")
191        .prereq(commitSquashEvents);
192    commitNonSpecStalls
193        .name(name() + ".commitNonSpecStalls")
194        .desc("The number of times commit has been forced to stall to "
195              "communicate backwards")
196        .prereq(commitNonSpecStalls);
197    branchMispredicts
198        .name(name() + ".branchMispredicts")
199        .desc("The number of times a branch was mispredicted")
200        .prereq(branchMispredicts);
201    numCommittedDist
202        .init(0,commitWidth,1)
203        .name(name() + ".committed_per_cycle")
204        .desc("Number of insts commited each cycle")
205        .flags(Stats::pdf)
206        ;
207
208    instsCommitted
209        .init(cpu->numThreads)
210        .name(name() + ".committedInsts")
211        .desc("Number of instructions committed")
212        .flags(total)
213        ;
214
215    opsCommitted
216        .init(cpu->numThreads)
217        .name(name() + ".committedOps")
218        .desc("Number of ops (including micro ops) committed")
219        .flags(total)
220        ;
221
222    statComSwp
223        .init(cpu->numThreads)
224        .name(name() + ".swp_count")
225        .desc("Number of s/w prefetches committed")
226        .flags(total)
227        ;
228
229    statComRefs
230        .init(cpu->numThreads)
231        .name(name() +  ".refs")
232        .desc("Number of memory references committed")
233        .flags(total)
234        ;
235
236    statComLoads
237        .init(cpu->numThreads)
238        .name(name() +  ".loads")
239        .desc("Number of loads committed")
240        .flags(total)
241        ;
242
243    statComMembars
244        .init(cpu->numThreads)
245        .name(name() +  ".membars")
246        .desc("Number of memory barriers committed")
247        .flags(total)
248        ;
249
250    statComBranches
251        .init(cpu->numThreads)
252        .name(name() + ".branches")
253        .desc("Number of branches committed")
254        .flags(total)
255        ;
256
257    statComFloating
258        .init(cpu->numThreads)
259        .name(name() + ".fp_insts")
260        .desc("Number of committed floating point instructions.")
261        .flags(total)
262        ;
263
264    statComInteger
265        .init(cpu->numThreads)
266        .name(name()+".int_insts")
267        .desc("Number of committed integer instructions.")
268        .flags(total)
269        ;
270
271    statComFunctionCalls
272        .init(cpu->numThreads)
273        .name(name()+".function_calls")
274        .desc("Number of function calls committed.")
275        .flags(total)
276        ;
277
278    statCommittedInstType
279        .init(numThreads,Enums::Num_OpClass)
280        .name(name() + ".op_class")
281        .desc("Class of committed instruction")
282        .flags(total | pdf | dist)
283        ;
284    statCommittedInstType.ysubnames(Enums::OpClassStrings);
285
286    commitEligible
287        .init(cpu->numThreads)
288        .name(name() + ".bw_limited")
289        .desc("number of insts not committed due to BW limits")
290        .flags(total)
291        ;
292
293    commitEligibleSamples
294        .name(name() + ".bw_lim_events")
295        .desc("number cycles where commit BW limit reached")
296        ;
297}
298
299template <class Impl>
300void
301DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
302{
303    thread = threads;
304}
305
306template <class Impl>
307void
308DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
309{
310    timeBuffer = tb_ptr;
311
312    // Setup wire to send information back to IEW.
313    toIEW = timeBuffer->getWire(0);
314
315    // Setup wire to read data from IEW (for the ROB).
316    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
322{
323    fetchQueue = fq_ptr;
324
325    // Setup wire to get instructions from rename (for the ROB).
326    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
327}
328
329template <class Impl>
330void
331DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
332{
333    renameQueue = rq_ptr;
334
335    // Setup wire to get instructions from rename (for the ROB).
336    fromRename = renameQueue->getWire(-renameToROBDelay);
337}
338
339template <class Impl>
340void
341DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
342{
343    iewQueue = iq_ptr;
344
345    // Setup wire to get instructions from IEW.
346    fromIEW = iewQueue->getWire(-iewToCommitDelay);
347}
348
349template <class Impl>
350void
351DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
352{
353    iewStage = iew_stage;
354}
355
356template<class Impl>
357void
358DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
359{
360    activeThreads = at_ptr;
361}
362
363template <class Impl>
364void
365DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
366{
367    for (ThreadID tid = 0; tid < numThreads; tid++)
368        renameMap[tid] = &rm_ptr[tid];
369}
370
371template <class Impl>
372void
373DefaultCommit<Impl>::setROB(ROB *rob_ptr)
374{
375    rob = rob_ptr;
376}
377
378template <class Impl>
379void
380DefaultCommit<Impl>::startupStage()
381{
382    rob->setActiveThreads(activeThreads);
383    rob->resetEntries();
384
385    // Broadcast the number of free entries.
386    for (ThreadID tid = 0; tid < numThreads; tid++) {
387        toIEW->commitInfo[tid].usedROB = true;
388        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
389        toIEW->commitInfo[tid].emptyROB = true;
390    }
391
392    // Commit must broadcast the number of free entries it has at the
393    // start of the simulation, so it starts as active.
394    cpu->activateStage(O3CPU::CommitIdx);
395
396    cpu->activityThisCycle();
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::drain()
402{
403    drainPending = true;
404}
405
406template <class Impl>
407void
408DefaultCommit<Impl>::drainResume()
409{
410    drainPending = false;
411    drainImminent = false;
412}
413
414template <class Impl>
415void
416DefaultCommit<Impl>::drainSanityCheck() const
417{
418    assert(isDrained());
419    rob->drainSanityCheck();
420}
421
422template <class Impl>
423bool
424DefaultCommit<Impl>::isDrained() const
425{
426    /* Make sure no one is executing microcode. There are two reasons
427     * for this:
428     * - Hardware virtualized CPUs can't switch into the middle of a
429     *   microcode sequence.
430     * - The current fetch implementation will most likely get very
431     *   confused if it tries to start fetching an instruction that
432     *   is executing in the middle of a ucode sequence that changes
433     *   address mappings. This can happen on for example x86.
434     */
435    for (ThreadID tid = 0; tid < numThreads; tid++) {
436        if (pc[tid].microPC() != 0)
437            return false;
438    }
439
440    /* Make sure that all instructions have finished committing before
441     * declaring the system as drained. We want the pipeline to be
442     * completely empty when we declare the CPU to be drained. This
443     * makes debugging easier since CPU handover and restoring from a
444     * checkpoint with a different CPU should have the same timing.
445     */
446    return rob->isEmpty() &&
447        interrupt == NoFault;
448}
449
450template <class Impl>
451void
452DefaultCommit<Impl>::takeOverFrom()
453{
454    _status = Active;
455    _nextStatus = Inactive;
456    for (ThreadID tid = 0; tid < numThreads; tid++) {
457        commitStatus[tid] = Idle;
458        changedROBNumEntries[tid] = false;
459        trapSquash[tid] = false;
460        tcSquash[tid] = false;
461        squashAfterInst[tid] = NULL;
462    }
463    squashCounter = 0;
464    rob->takeOverFrom();
465}
466
467template <class Impl>
468void
469DefaultCommit<Impl>::deactivateThread(ThreadID tid)
470{
471    list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
472            priority_list.end(), tid);
473
474    if (thread_it != priority_list.end()) {
475        priority_list.erase(thread_it);
476    }
477}
478
479
480template <class Impl>
481void
482DefaultCommit<Impl>::updateStatus()
483{
484    // reset ROB changed variable
485    list<ThreadID>::iterator threads = activeThreads->begin();
486    list<ThreadID>::iterator end = activeThreads->end();
487
488    while (threads != end) {
489        ThreadID tid = *threads++;
490
491        changedROBNumEntries[tid] = false;
492
493        // Also check if any of the threads has a trap pending
494        if (commitStatus[tid] == TrapPending ||
495            commitStatus[tid] == FetchTrapPending) {
496            _nextStatus = Active;
497        }
498    }
499
500    if (_nextStatus == Inactive && _status == Active) {
501        DPRINTF(Activity, "Deactivating stage.\n");
502        cpu->deactivateStage(O3CPU::CommitIdx);
503    } else if (_nextStatus == Active && _status == Inactive) {
504        DPRINTF(Activity, "Activating stage.\n");
505        cpu->activateStage(O3CPU::CommitIdx);
506    }
507
508    _status = _nextStatus;
509}
510
511template <class Impl>
512void
513DefaultCommit<Impl>::setNextStatus()
514{
515    int squashes = 0;
516
517    list<ThreadID>::iterator threads = activeThreads->begin();
518    list<ThreadID>::iterator end = activeThreads->end();
519
520    while (threads != end) {
521        ThreadID tid = *threads++;
522
523        if (commitStatus[tid] == ROBSquashing) {
524            squashes++;
525        }
526    }
527
528    squashCounter = squashes;
529
530    // If commit is currently squashing, then it will have activity for the
531    // next cycle. Set its next status as active.
532    if (squashCounter) {
533        _nextStatus = Active;
534    }
535}
536
537template <class Impl>
538bool
539DefaultCommit<Impl>::changedROBEntries()
540{
541    list<ThreadID>::iterator threads = activeThreads->begin();
542    list<ThreadID>::iterator end = activeThreads->end();
543
544    while (threads != end) {
545        ThreadID tid = *threads++;
546
547        if (changedROBNumEntries[tid]) {
548            return true;
549        }
550    }
551
552    return false;
553}
554
555template <class Impl>
556size_t
557DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
558{
559    return rob->numFreeEntries(tid);
560}
561
562template <class Impl>
563void
564DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
565{
566    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
567
568    TrapEvent *trap = new TrapEvent(this, tid);
569
570    cpu->schedule(trap, cpu->clockEdge(trapLatency));
571    trapInFlight[tid] = true;
572    thread[tid]->trapPending = true;
573}
574
575template <class Impl>
576void
577DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
578{
579    assert(!trapInFlight[tid]);
580    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
581
582    tcSquash[tid] = true;
583}
584
585template <class Impl>
586void
587DefaultCommit<Impl>::squashAll(ThreadID tid)
588{
589    // If we want to include the squashing instruction in the squash,
590    // then use one older sequence number.
591    // Hopefully this doesn't mess things up.  Basically I want to squash
592    // all instructions of this thread.
593    InstSeqNum squashed_inst = rob->isEmpty(tid) ?
594        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
595
596    // All younger instructions will be squashed. Set the sequence
597    // number as the youngest instruction in the ROB (0 in this case.
598    // Hopefully nothing breaks.)
599    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
600
601    rob->squash(squashed_inst, tid);
602    changedROBNumEntries[tid] = true;
603
604    // Send back the sequence number of the squashed instruction.
605    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
606
607    // Send back the squash signal to tell stages that they should
608    // squash.
609    toIEW->commitInfo[tid].squash = true;
610
611    // Send back the rob squashing signal so other stages know that
612    // the ROB is in the process of squashing.
613    toIEW->commitInfo[tid].robSquashing = true;
614
615    toIEW->commitInfo[tid].mispredictInst = NULL;
616    toIEW->commitInfo[tid].squashInst = NULL;
617
618    toIEW->commitInfo[tid].pc = pc[tid];
619}
620
621template <class Impl>
622void
623DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
624{
625    squashAll(tid);
626
627    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
628
629    thread[tid]->trapPending = false;
630    thread[tid]->noSquashFromTC = false;
631    trapInFlight[tid] = false;
632
633    trapSquash[tid] = false;
634
635    commitStatus[tid] = ROBSquashing;
636    cpu->activityThisCycle();
637}
638
639template <class Impl>
640void
641DefaultCommit<Impl>::squashFromTC(ThreadID tid)
642{
643    squashAll(tid);
644
645    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
646
647    thread[tid]->noSquashFromTC = false;
648    assert(!thread[tid]->trapPending);
649
650    commitStatus[tid] = ROBSquashing;
651    cpu->activityThisCycle();
652
653    tcSquash[tid] = false;
654}
655
656template <class Impl>
657void
658DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
659{
660    DPRINTF(Commit, "Squashing after squash after request, "
661            "restarting at PC %s\n", pc[tid]);
662
663    squashAll(tid);
664    // Make sure to inform the fetch stage of which instruction caused
665    // the squash. It'll try to re-fetch an instruction executing in
666    // microcode unless this is set.
667    toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
668    squashAfterInst[tid] = NULL;
669
670    commitStatus[tid] = ROBSquashing;
671    cpu->activityThisCycle();
672}
673
674template <class Impl>
675void
676DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
677{
678    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
679            tid, head_inst->seqNum);
680
681    assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
682    commitStatus[tid] = SquashAfterPending;
683    squashAfterInst[tid] = head_inst;
684}
685
686template <class Impl>
687void
688DefaultCommit<Impl>::tick()
689{
690    wroteToTimeBuffer = false;
691    _nextStatus = Inactive;
692
693    if (activeThreads->empty())
694        return;
695
696    list<ThreadID>::iterator threads = activeThreads->begin();
697    list<ThreadID>::iterator end = activeThreads->end();
698
699    // Check if any of the threads are done squashing.  Change the
700    // status if they are done.
701    while (threads != end) {
702        ThreadID tid = *threads++;
703
704        // Clear the bit saying if the thread has committed stores
705        // this cycle.
706        committedStores[tid] = false;
707
708        if (commitStatus[tid] == ROBSquashing) {
709
710            if (rob->isDoneSquashing(tid)) {
711                commitStatus[tid] = Running;
712            } else {
713                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
714                        " insts this cycle.\n", tid);
715                rob->doSquash(tid);
716                toIEW->commitInfo[tid].robSquashing = true;
717                wroteToTimeBuffer = true;
718            }
719        }
720    }
721
722    commit();
723
724    markCompletedInsts();
725
726    threads = activeThreads->begin();
727
728    while (threads != end) {
729        ThreadID tid = *threads++;
730
731        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
732            // The ROB has more instructions it can commit. Its next status
733            // will be active.
734            _nextStatus = Active;
735
736            DynInstPtr inst = rob->readHeadInst(tid);
737
738            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
739                    " ROB and ready to commit\n",
740                    tid, inst->seqNum, inst->pcState());
741
742        } else if (!rob->isEmpty(tid)) {
743            DynInstPtr inst = rob->readHeadInst(tid);
744
745            ppCommitStall->notify(inst);
746
747            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
748                    "%s is head of ROB and not ready\n",
749                    tid, inst->seqNum, inst->pcState());
750        }
751
752        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
753                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
754    }
755
756
757    if (wroteToTimeBuffer) {
758        DPRINTF(Activity, "Activity This Cycle.\n");
759        cpu->activityThisCycle();
760    }
761
762    updateStatus();
763}
764
765template <class Impl>
766void
767DefaultCommit<Impl>::handleInterrupt()
768{
769    // Verify that we still have an interrupt to handle
770    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
771        DPRINTF(Commit, "Pending interrupt is cleared by master before "
772                "it got handled. Restart fetching from the orig path.\n");
773        toIEW->commitInfo[0].clearInterrupt = true;
774        interrupt = NoFault;
775        avoidQuiesceLiveLock = true;
776        return;
777    }
778
779    // Wait until all in flight instructions are finished before enterring
780    // the interrupt.
781    if (canHandleInterrupts && cpu->instList.empty()) {
782        // Squash or record that I need to squash this cycle if
783        // an interrupt needed to be handled.
784        DPRINTF(Commit, "Interrupt detected.\n");
785
786        // Clear the interrupt now that it's going to be handled
787        toIEW->commitInfo[0].clearInterrupt = true;
788
789        assert(!thread[0]->noSquashFromTC);
790        thread[0]->noSquashFromTC = true;
791
792        if (cpu->checker) {
793            cpu->checker->handlePendingInt();
794        }
795
796        // CPU will handle interrupt. Note that we ignore the local copy of
797        // interrupt. This is because the local copy may no longer be the
798        // interrupt that the interrupt controller thinks is being handled.
799        cpu->processInterrupts(cpu->getInterrupts());
800
801        thread[0]->noSquashFromTC = false;
802
803        commitStatus[0] = TrapPending;
804
805        // Generate trap squash event.
806        generateTrapEvent(0);
807
808        interrupt = NoFault;
809        avoidQuiesceLiveLock = false;
810    } else {
811        DPRINTF(Commit, "Interrupt pending: instruction is %sin "
812                "flight, ROB is %sempty\n",
813                canHandleInterrupts ? "not " : "",
814                cpu->instList.empty() ? "" : "not " );
815    }
816}
817
818template <class Impl>
819void
820DefaultCommit<Impl>::propagateInterrupt()
821{
822    // Don't propagate intterupts if we are currently handling a trap or
823    // in draining and the last observable instruction has been committed.
824    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
825            tcSquash[0] || drainImminent)
826        return;
827
828    // Process interrupts if interrupts are enabled, not in PAL
829    // mode, and no other traps or external squashes are currently
830    // pending.
831    // @todo: Allow other threads to handle interrupts.
832
833    // Get any interrupt that happened
834    interrupt = cpu->getInterrupts();
835
836    // Tell fetch that there is an interrupt pending.  This
837    // will make fetch wait until it sees a non PAL-mode PC,
838    // at which point it stops fetching instructions.
839    if (interrupt != NoFault)
840        toIEW->commitInfo[0].interruptPending = true;
841}
842
843template <class Impl>
844void
845DefaultCommit<Impl>::commit()
846{
847    if (FullSystem) {
848        // Check if we have a interrupt and get read to handle it
849        if (cpu->checkInterrupts(cpu->tcBase(0)))
850            propagateInterrupt();
851    }
852
853    ////////////////////////////////////
854    // Check for any possible squashes, handle them first
855    ////////////////////////////////////
856    list<ThreadID>::iterator threads = activeThreads->begin();
857    list<ThreadID>::iterator end = activeThreads->end();
858
859    while (threads != end) {
860        ThreadID tid = *threads++;
861
862        // Not sure which one takes priority.  I think if we have
863        // both, that's a bad sign.
864        if (trapSquash[tid]) {
865            assert(!tcSquash[tid]);
866            squashFromTrap(tid);
867        } else if (tcSquash[tid]) {
868            assert(commitStatus[tid] != TrapPending);
869            squashFromTC(tid);
870        } else if (commitStatus[tid] == SquashAfterPending) {
871            // A squash from the previous cycle of the commit stage (i.e.,
872            // commitInsts() called squashAfter) is pending. Squash the
873            // thread now.
874            squashFromSquashAfter(tid);
875        }
876
877        // Squashed sequence number must be older than youngest valid
878        // instruction in the ROB. This prevents squashes from younger
879        // instructions overriding squashes from older instructions.
880        if (fromIEW->squash[tid] &&
881            commitStatus[tid] != TrapPending &&
882            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
883
884            if (fromIEW->mispredictInst[tid]) {
885                DPRINTF(Commit,
886                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
887                    tid,
888                    fromIEW->mispredictInst[tid]->instAddr(),
889                    fromIEW->squashedSeqNum[tid]);
890            } else {
891                DPRINTF(Commit,
892                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
893                    tid, fromIEW->squashedSeqNum[tid]);
894            }
895
896            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
897                    tid,
898                    fromIEW->pc[tid].nextInstAddr());
899
900            commitStatus[tid] = ROBSquashing;
901
902            // If we want to include the squashing instruction in the squash,
903            // then use one older sequence number.
904            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
905
906            if (fromIEW->includeSquashInst[tid]) {
907                squashed_inst--;
908            }
909
910            // All younger instructions will be squashed. Set the sequence
911            // number as the youngest instruction in the ROB.
912            youngestSeqNum[tid] = squashed_inst;
913
914            rob->squash(squashed_inst, tid);
915            changedROBNumEntries[tid] = true;
916
917            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
918
919            toIEW->commitInfo[tid].squash = true;
920
921            // Send back the rob squashing signal so other stages know that
922            // the ROB is in the process of squashing.
923            toIEW->commitInfo[tid].robSquashing = true;
924
925            toIEW->commitInfo[tid].mispredictInst =
926                fromIEW->mispredictInst[tid];
927            toIEW->commitInfo[tid].branchTaken =
928                fromIEW->branchTaken[tid];
929            toIEW->commitInfo[tid].squashInst =
930                                    rob->findInst(tid, squashed_inst);
931            if (toIEW->commitInfo[tid].mispredictInst) {
932                if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
933                     toIEW->commitInfo[tid].branchTaken = true;
934                }
935            }
936
937            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
938
939            if (toIEW->commitInfo[tid].mispredictInst) {
940                ++branchMispredicts;
941            }
942        }
943
944    }
945
946    setNextStatus();
947
948    if (squashCounter != numThreads) {
949        // If we're not currently squashing, then get instructions.
950        getInsts();
951
952        // Try to commit any instructions.
953        commitInsts();
954    }
955
956    //Check for any activity
957    threads = activeThreads->begin();
958
959    while (threads != end) {
960        ThreadID tid = *threads++;
961
962        if (changedROBNumEntries[tid]) {
963            toIEW->commitInfo[tid].usedROB = true;
964            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
965
966            wroteToTimeBuffer = true;
967            changedROBNumEntries[tid] = false;
968            if (rob->isEmpty(tid))
969                checkEmptyROB[tid] = true;
970        }
971
972        // ROB is only considered "empty" for previous stages if: a)
973        // ROB is empty, b) there are no outstanding stores, c) IEW
974        // stage has received any information regarding stores that
975        // committed.
976        // c) is checked by making sure to not consider the ROB empty
977        // on the same cycle as when stores have been committed.
978        // @todo: Make this handle multi-cycle communication between
979        // commit and IEW.
980        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
981            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
982            checkEmptyROB[tid] = false;
983            toIEW->commitInfo[tid].usedROB = true;
984            toIEW->commitInfo[tid].emptyROB = true;
985            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
986            wroteToTimeBuffer = true;
987        }
988
989    }
990}
991
992template <class Impl>
993void
994DefaultCommit<Impl>::commitInsts()
995{
996    ////////////////////////////////////
997    // Handle commit
998    // Note that commit will be handled prior to putting new
999    // instructions in the ROB so that the ROB only tries to commit
1000    // instructions it has in this current cycle, and not instructions
1001    // it is writing in during this cycle.  Can't commit and squash
1002    // things at the same time...
1003    ////////////////////////////////////
1004
1005    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
1006
1007    unsigned num_committed = 0;
1008
1009    DynInstPtr head_inst;
1010
1011    // Commit as many instructions as possible until the commit bandwidth
1012    // limit is reached, or it becomes impossible to commit any more.
1013    while (num_committed < commitWidth) {
1014        // Check for any interrupt that we've already squashed for
1015        // and start processing it.
1016        if (interrupt != NoFault)
1017            handleInterrupt();
1018
1019        int commit_thread = getCommittingThread();
1020
1021        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
1022            break;
1023
1024        head_inst = rob->readHeadInst(commit_thread);
1025
1026        ThreadID tid = head_inst->threadNumber;
1027
1028        assert(tid == commit_thread);
1029
1030        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1031                head_inst->seqNum, tid);
1032
1033        // If the head instruction is squashed, it is ready to retire
1034        // (be removed from the ROB) at any time.
1035        if (head_inst->isSquashed()) {
1036
1037            DPRINTF(Commit, "Retiring squashed instruction from "
1038                    "ROB.\n");
1039
1040            rob->retireHead(commit_thread);
1041
1042            ++commitSquashedInsts;
1043
1044            // Record that the number of ROB entries has changed.
1045            changedROBNumEntries[tid] = true;
1046        } else {
1047            pc[tid] = head_inst->pcState();
1048
1049            // Increment the total number of non-speculative instructions
1050            // executed.
1051            // Hack for now: it really shouldn't happen until after the
1052            // commit is deemed to be successful, but this count is needed
1053            // for syscalls.
1054            thread[tid]->funcExeInst++;
1055
1056            // Try to commit the head instruction.
1057            bool commit_success = commitHead(head_inst, num_committed);
1058
1059            if (commit_success) {
1060                ++num_committed;
1061                statCommittedInstType[tid][head_inst->opClass()]++;
1062                ppCommit->notify(head_inst);
1063
1064                changedROBNumEntries[tid] = true;
1065
1066                // Set the doneSeqNum to the youngest committed instruction.
1067                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1068
1069                if (tid == 0) {
1070                    canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
1071                                           ((THE_ISA != ALPHA_ISA) ||
1072                                             (!(pc[0].instAddr() & 0x3)));
1073                }
1074
1075                // Updates misc. registers.
1076                head_inst->updateMiscRegs();
1077
1078                // Check instruction execution if it successfully commits and
1079                // is not carrying a fault.
1080                if (cpu->checker) {
1081                    cpu->checker->verify(head_inst);
1082                }
1083
1084                cpu->traceFunctions(pc[tid].instAddr());
1085
1086                TheISA::advancePC(pc[tid], head_inst->staticInst);
1087
1088                // Keep track of the last sequence number commited
1089                lastCommitedSeqNum[tid] = head_inst->seqNum;
1090
1091                // If this is an instruction that doesn't play nicely with
1092                // others squash everything and restart fetch
1093                if (head_inst->isSquashAfter())
1094                    squashAfter(tid, head_inst);
1095
1096                if (drainPending) {
1097                    if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1098                        !thread[tid]->trapPending) {
1099                        // Last architectually committed instruction.
1100                        // Squash the pipeline, stall fetch, and use
1101                        // drainImminent to disable interrupts
1102                        DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1103                        squashAfter(tid, head_inst);
1104                        cpu->commitDrained(tid);
1105                        drainImminent = true;
1106                    }
1107                }
1108
1109                bool onInstBoundary = !head_inst->isMicroop() ||
1110                                      head_inst->isLastMicroop() ||
1111                                      !head_inst->isDelayedCommit();
1112
1113                if (onInstBoundary) {
1114                    int count = 0;
1115                    Addr oldpc;
1116                    // Make sure we're not currently updating state while
1117                    // handling PC events.
1118                    assert(!thread[tid]->noSquashFromTC &&
1119                           !thread[tid]->trapPending);
1120                    do {
1121                        oldpc = pc[tid].instAddr();
1122                        cpu->system->pcEventQueue.service(thread[tid]->getTC());
1123                        count++;
1124                    } while (oldpc != pc[tid].instAddr());
1125                    if (count > 1) {
1126                        DPRINTF(Commit,
1127                                "PC skip function event, stopping commit\n");
1128                        break;
1129                    }
1130                }
1131
1132                // Check if an instruction just enabled interrupts and we've
1133                // previously had an interrupt pending that was not handled
1134                // because interrupts were subsequently disabled before the
1135                // pipeline reached a place to handle the interrupt. In that
1136                // case squash now to make sure the interrupt is handled.
1137                //
1138                // If we don't do this, we might end up in a live lock situation
1139                if (!interrupt && avoidQuiesceLiveLock &&
1140                    onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1141                    squashAfter(tid, head_inst);
1142            } else {
1143                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1144                        "[tid:%i] [sn:%i].\n",
1145                        head_inst->pcState(), tid ,head_inst->seqNum);
1146                break;
1147            }
1148        }
1149    }
1150
1151    DPRINTF(CommitRate, "%i\n", num_committed);
1152    numCommittedDist.sample(num_committed);
1153
1154    if (num_committed == commitWidth) {
1155        commitEligibleSamples++;
1156    }
1157}
1158
1159template <class Impl>
1160bool
1161DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1162{
1163    assert(head_inst);
1164
1165    ThreadID tid = head_inst->threadNumber;
1166
1167    // If the instruction is not executed yet, then it will need extra
1168    // handling.  Signal backwards that it should be executed.
1169    if (!head_inst->isExecuted()) {
1170        // Keep this number correct.  We have not yet actually executed
1171        // and committed this instruction.
1172        thread[tid]->funcExeInst--;
1173
1174        // Make sure we are only trying to commit un-executed instructions we
1175        // think are possible.
1176        assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1177               || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1178               (head_inst->isLoad() && head_inst->uncacheable()));
1179
1180        DPRINTF(Commit, "Encountered a barrier or non-speculative "
1181                "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1182                head_inst->seqNum, head_inst->pcState());
1183
1184        if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1185            DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1186            return false;
1187        }
1188
1189        toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1190
1191        // Change the instruction so it won't try to commit again until
1192        // it is executed.
1193        head_inst->clearCanCommit();
1194
1195        if (head_inst->isLoad() && head_inst->uncacheable()) {
1196            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1197                    head_inst->seqNum, head_inst->pcState());
1198            toIEW->commitInfo[tid].uncached = true;
1199            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1200        } else {
1201            ++commitNonSpecStalls;
1202        }
1203
1204        return false;
1205    }
1206
1207    if (head_inst->isThreadSync()) {
1208        // Not handled for now.
1209        panic("Thread sync instructions are not handled yet.\n");
1210    }
1211
1212    // Check if the instruction caused a fault.  If so, trap.
1213    Fault inst_fault = head_inst->getFault();
1214
1215    // Stores mark themselves as completed.
1216    if (!head_inst->isStore() && inst_fault == NoFault) {
1217        head_inst->setCompleted();
1218    }
1219
1220    if (inst_fault != NoFault) {
1221        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1222                head_inst->seqNum, head_inst->pcState());
1223
1224        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1225            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1226            return false;
1227        }
1228
1229        head_inst->setCompleted();
1230
1231        // If instruction has faulted, let the checker execute it and
1232        // check if it sees the same fault and control flow.
1233        if (cpu->checker) {
1234            // Need to check the instruction before its fault is processed
1235            cpu->checker->verify(head_inst);
1236        }
1237
1238        assert(!thread[tid]->noSquashFromTC);
1239
1240        // Mark that we're in state update mode so that the trap's
1241        // execution doesn't generate extra squashes.
1242        thread[tid]->noSquashFromTC = true;
1243
1244        // Execute the trap.  Although it's slightly unrealistic in
1245        // terms of timing (as it doesn't wait for the full timing of
1246        // the trap event to complete before updating state), it's
1247        // needed to update the state as soon as possible.  This
1248        // prevents external agents from changing any specific state
1249        // that the trap need.
1250        cpu->trap(inst_fault, tid, head_inst->staticInst);
1251
1252        // Exit state update mode to avoid accidental updating.
1253        thread[tid]->noSquashFromTC = false;
1254
1255        commitStatus[tid] = TrapPending;
1256
1257        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1258            head_inst->seqNum);
1259        if (head_inst->traceData) {
1260            if (DTRACE(ExecFaulting)) {
1261                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1262                head_inst->traceData->setCPSeq(thread[tid]->numOp);
1263                head_inst->traceData->dump();
1264            }
1265            delete head_inst->traceData;
1266            head_inst->traceData = NULL;
1267        }
1268
1269        // Generate trap squash event.
1270        generateTrapEvent(tid);
1271        return false;
1272    }
1273
1274    updateComInstStats(head_inst);
1275
1276    if (FullSystem) {
1277        if (thread[tid]->profile) {
1278            thread[tid]->profilePC = head_inst->instAddr();
1279            ProfileNode *node = thread[tid]->profile->consume(
1280                    thread[tid]->getTC(), head_inst->staticInst);
1281
1282            if (node)
1283                thread[tid]->profileNode = node;
1284        }
1285        if (CPA::available()) {
1286            if (head_inst->isControl()) {
1287                ThreadContext *tc = thread[tid]->getTC();
1288                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1289            }
1290        }
1291    }
1292    DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1293            head_inst->seqNum, head_inst->pcState());
1294    if (head_inst->traceData) {
1295        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1296        head_inst->traceData->setCPSeq(thread[tid]->numOp);
1297        head_inst->traceData->dump();
1298        delete head_inst->traceData;
1299        head_inst->traceData = NULL;
1300    }
1301    if (head_inst->isReturn()) {
1302        DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1303                        head_inst->seqNum, head_inst->pcState());
1304    }
1305
1306    // Update the commit rename map
1307    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1308        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1309                                 head_inst->renamedDestRegIdx(i));
1310    }
1311
1312    // Finally clear the head ROB entry.
1313    rob->retireHead(tid);
1314
1315#if TRACING_ON
1316    if (DTRACE(O3PipeView)) {
1317        head_inst->commitTick = curTick() - head_inst->fetchTick;
1318    }
1319#endif
1320
1321    // If this was a store, record it for this cycle.
1322    if (head_inst->isStore())
1323        committedStores[tid] = true;
1324
1325    // Return true to indicate that we have committed an instruction.
1326    return true;
1327}
1328
1329template <class Impl>
1330void
1331DefaultCommit<Impl>::getInsts()
1332{
1333    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1334
1335    // Read any renamed instructions and place them into the ROB.
1336    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1337
1338    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1339        DynInstPtr inst;
1340
1341        inst = fromRename->insts[inst_num];
1342        ThreadID tid = inst->threadNumber;
1343
1344        if (!inst->isSquashed() &&
1345            commitStatus[tid] != ROBSquashing &&
1346            commitStatus[tid] != TrapPending) {
1347            changedROBNumEntries[tid] = true;
1348
1349            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1350                    inst->pcState(), inst->seqNum, tid);
1351
1352            rob->insertInst(inst);
1353
1354            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1355
1356            youngestSeqNum[tid] = inst->seqNum;
1357        } else {
1358            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1359                    "squashed, skipping.\n",
1360                    inst->pcState(), inst->seqNum, tid);
1361        }
1362    }
1363}
1364
1365template <class Impl>
1366void
1367DefaultCommit<Impl>::markCompletedInsts()
1368{
1369    // Grab completed insts out of the IEW instruction queue, and mark
1370    // instructions completed within the ROB.
1371    for (int inst_num = 0;
1372         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1373         ++inst_num)
1374    {
1375        if (!fromIEW->insts[inst_num]->isSquashed()) {
1376            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1377                    "within ROB.\n",
1378                    fromIEW->insts[inst_num]->threadNumber,
1379                    fromIEW->insts[inst_num]->pcState(),
1380                    fromIEW->insts[inst_num]->seqNum);
1381
1382            // Mark the instruction as ready to commit.
1383            fromIEW->insts[inst_num]->setCanCommit();
1384        }
1385    }
1386}
1387
1388template <class Impl>
1389void
1390DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1391{
1392    ThreadID tid = inst->threadNumber;
1393
1394    if (!inst->isMicroop() || inst->isLastMicroop())
1395        instsCommitted[tid]++;
1396    opsCommitted[tid]++;
1397
1398    // To match the old model, don't count nops and instruction
1399    // prefetches towards the total commit count.
1400    if (!inst->isNop() && !inst->isInstPrefetch()) {
1401        cpu->instDone(tid, inst);
1402    }
1403
1404    //
1405    //  Control Instructions
1406    //
1407    if (inst->isControl())
1408        statComBranches[tid]++;
1409
1410    //
1411    //  Memory references
1412    //
1413    if (inst->isMemRef()) {
1414        statComRefs[tid]++;
1415
1416        if (inst->isLoad()) {
1417            statComLoads[tid]++;
1418        }
1419    }
1420
1421    if (inst->isMemBarrier()) {
1422        statComMembars[tid]++;
1423    }
1424
1425    // Integer Instruction
1426    if (inst->isInteger())
1427        statComInteger[tid]++;
1428
1429    // Floating Point Instruction
1430    if (inst->isFloating())
1431        statComFloating[tid]++;
1432
1433    // Function Calls
1434    if (inst->isCall())
1435        statComFunctionCalls[tid]++;
1436
1437}
1438
1439////////////////////////////////////////
1440//                                    //
1441//  SMT COMMIT POLICY MAINTAINED HERE //
1442//                                    //
1443////////////////////////////////////////
1444template <class Impl>
1445ThreadID
1446DefaultCommit<Impl>::getCommittingThread()
1447{
1448    if (numThreads > 1) {
1449        switch (commitPolicy) {
1450
1451          case Aggressive:
1452            //If Policy is Aggressive, commit will call
1453            //this function multiple times per
1454            //cycle
1455            return oldestReady();
1456
1457          case RoundRobin:
1458            return roundRobin();
1459
1460          case OldestReady:
1461            return oldestReady();
1462
1463          default:
1464            return InvalidThreadID;
1465        }
1466    } else {
1467        assert(!activeThreads->empty());
1468        ThreadID tid = activeThreads->front();
1469
1470        if (commitStatus[tid] == Running ||
1471            commitStatus[tid] == Idle ||
1472            commitStatus[tid] == FetchTrapPending) {
1473            return tid;
1474        } else {
1475            return InvalidThreadID;
1476        }
1477    }
1478}
1479
1480template<class Impl>
1481ThreadID
1482DefaultCommit<Impl>::roundRobin()
1483{
1484    list<ThreadID>::iterator pri_iter = priority_list.begin();
1485    list<ThreadID>::iterator end      = priority_list.end();
1486
1487    while (pri_iter != end) {
1488        ThreadID tid = *pri_iter;
1489
1490        if (commitStatus[tid] == Running ||
1491            commitStatus[tid] == Idle ||
1492            commitStatus[tid] == FetchTrapPending) {
1493
1494            if (rob->isHeadReady(tid)) {
1495                priority_list.erase(pri_iter);
1496                priority_list.push_back(tid);
1497
1498                return tid;
1499            }
1500        }
1501
1502        pri_iter++;
1503    }
1504
1505    return InvalidThreadID;
1506}
1507
1508template<class Impl>
1509ThreadID
1510DefaultCommit<Impl>::oldestReady()
1511{
1512    unsigned oldest = 0;
1513    bool first = true;
1514
1515    list<ThreadID>::iterator threads = activeThreads->begin();
1516    list<ThreadID>::iterator end = activeThreads->end();
1517
1518    while (threads != end) {
1519        ThreadID tid = *threads++;
1520
1521        if (!rob->isEmpty(tid) &&
1522            (commitStatus[tid] == Running ||
1523             commitStatus[tid] == Idle ||
1524             commitStatus[tid] == FetchTrapPending)) {
1525
1526            if (rob->isHeadReady(tid)) {
1527
1528                DynInstPtr head_inst = rob->readHeadInst(tid);
1529
1530                if (first) {
1531                    oldest = tid;
1532                    first = false;
1533                } else if (head_inst->seqNum < oldest) {
1534                    oldest = tid;
1535                }
1536            }
1537        }
1538    }
1539
1540    if (!first) {
1541        return oldest;
1542    } else {
1543        return InvalidThreadID;
1544    }
1545}
1546
1547#endif//__CPU_O3_COMMIT_IMPL_HH__
1548