commit_impl.hh revision 10331:ed05298e8566
1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43#ifndef __CPU_O3_COMMIT_IMPL_HH__ 44#define __CPU_O3_COMMIT_IMPL_HH__ 45 46#include <algorithm> 47#include <set> 48#include <string> 49 50#include "arch/utility.hh" 51#include "base/loader/symtab.hh" 52#include "base/cp_annotate.hh" 53#include "config/the_isa.hh" 54#include "cpu/checker/cpu.hh" 55#include "cpu/o3/commit.hh" 56#include "cpu/o3/thread_state.hh" 57#include "cpu/base.hh" 58#include "cpu/exetrace.hh" 59#include "cpu/timebuf.hh" 60#include "debug/Activity.hh" 61#include "debug/Commit.hh" 62#include "debug/CommitRate.hh" 63#include "debug/Drain.hh" 64#include "debug/ExecFaulting.hh" 65#include "debug/O3PipeView.hh" 66#include "params/DerivO3CPU.hh" 67#include "sim/faults.hh" 68#include "sim/full_system.hh" 69 70using namespace std; 71 72template <class Impl> 73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 74 ThreadID _tid) 75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 76{ 77} 78 79template <class Impl> 80void 81DefaultCommit<Impl>::TrapEvent::process() 82{ 83 // This will get reset by commit if it was switched out at the 84 // time of this event processing. 85 commit->trapSquash[tid] = true; 86} 87 88template <class Impl> 89const char * 90DefaultCommit<Impl>::TrapEvent::description() const 91{ 92 return "Trap"; 93} 94 95template <class Impl> 96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 97 : cpu(_cpu), 98 squashCounter(0), 99 iewToCommitDelay(params->iewToCommitDelay), 100 commitToIEWDelay(params->commitToIEWDelay), 101 renameToROBDelay(params->renameToROBDelay), 102 fetchToCommitDelay(params->commitToFetchDelay), 103 renameWidth(params->renameWidth), 104 commitWidth(params->commitWidth), 105 numThreads(params->numThreads), 106 drainPending(false), 107 trapLatency(params->trapLatency), 108 canHandleInterrupts(true), 109 avoidQuiesceLiveLock(false) 110{ 111 if (commitWidth > Impl::MaxWidth) 112 fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 113 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 114 commitWidth, static_cast<int>(Impl::MaxWidth)); 115 116 _status = Active; 117 _nextStatus = Inactive; 118 std::string policy = params->smtCommitPolicy; 119 120 //Convert string to lowercase 121 std::transform(policy.begin(), policy.end(), policy.begin(), 122 (int(*)(int)) tolower); 123 124 //Assign commit policy 125 if (policy == "aggressive"){ 126 commitPolicy = Aggressive; 127 128 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 129 } else if (policy == "roundrobin"){ 130 commitPolicy = RoundRobin; 131 132 //Set-Up Priority List 133 for (ThreadID tid = 0; tid < numThreads; tid++) { 134 priority_list.push_back(tid); 135 } 136 137 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 138 } else if (policy == "oldestready"){ 139 commitPolicy = OldestReady; 140 141 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 142 } else { 143 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 144 "RoundRobin,OldestReady}"); 145 } 146 147 for (ThreadID tid = 0; tid < numThreads; tid++) { 148 commitStatus[tid] = Idle; 149 changedROBNumEntries[tid] = false; 150 checkEmptyROB[tid] = false; 151 trapInFlight[tid] = false; 152 committedStores[tid] = false; 153 trapSquash[tid] = false; 154 tcSquash[tid] = false; 155 pc[tid].set(0); 156 lastCommitedSeqNum[tid] = 0; 157 squashAfterInst[tid] = NULL; 158 } 159 interrupt = NoFault; 160} 161 162template <class Impl> 163std::string 164DefaultCommit<Impl>::name() const 165{ 166 return cpu->name() + ".commit"; 167} 168 169template <class Impl> 170void 171DefaultCommit<Impl>::regProbePoints() 172{ 173 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 174 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 175} 176 177template <class Impl> 178void 179DefaultCommit<Impl>::regStats() 180{ 181 using namespace Stats; 182 commitSquashedInsts 183 .name(name() + ".commitSquashedInsts") 184 .desc("The number of squashed insts skipped by commit") 185 .prereq(commitSquashedInsts); 186 commitSquashEvents 187 .name(name() + ".commitSquashEvents") 188 .desc("The number of times commit is told to squash") 189 .prereq(commitSquashEvents); 190 commitNonSpecStalls 191 .name(name() + ".commitNonSpecStalls") 192 .desc("The number of times commit has been forced to stall to " 193 "communicate backwards") 194 .prereq(commitNonSpecStalls); 195 branchMispredicts 196 .name(name() + ".branchMispredicts") 197 .desc("The number of times a branch was mispredicted") 198 .prereq(branchMispredicts); 199 numCommittedDist 200 .init(0,commitWidth,1) 201 .name(name() + ".committed_per_cycle") 202 .desc("Number of insts commited each cycle") 203 .flags(Stats::pdf) 204 ; 205 206 instsCommitted 207 .init(cpu->numThreads) 208 .name(name() + ".committedInsts") 209 .desc("Number of instructions committed") 210 .flags(total) 211 ; 212 213 opsCommitted 214 .init(cpu->numThreads) 215 .name(name() + ".committedOps") 216 .desc("Number of ops (including micro ops) committed") 217 .flags(total) 218 ; 219 220 statComSwp 221 .init(cpu->numThreads) 222 .name(name() + ".swp_count") 223 .desc("Number of s/w prefetches committed") 224 .flags(total) 225 ; 226 227 statComRefs 228 .init(cpu->numThreads) 229 .name(name() + ".refs") 230 .desc("Number of memory references committed") 231 .flags(total) 232 ; 233 234 statComLoads 235 .init(cpu->numThreads) 236 .name(name() + ".loads") 237 .desc("Number of loads committed") 238 .flags(total) 239 ; 240 241 statComMembars 242 .init(cpu->numThreads) 243 .name(name() + ".membars") 244 .desc("Number of memory barriers committed") 245 .flags(total) 246 ; 247 248 statComBranches 249 .init(cpu->numThreads) 250 .name(name() + ".branches") 251 .desc("Number of branches committed") 252 .flags(total) 253 ; 254 255 statComFloating 256 .init(cpu->numThreads) 257 .name(name() + ".fp_insts") 258 .desc("Number of committed floating point instructions.") 259 .flags(total) 260 ; 261 262 statComInteger 263 .init(cpu->numThreads) 264 .name(name()+".int_insts") 265 .desc("Number of committed integer instructions.") 266 .flags(total) 267 ; 268 269 statComFunctionCalls 270 .init(cpu->numThreads) 271 .name(name()+".function_calls") 272 .desc("Number of function calls committed.") 273 .flags(total) 274 ; 275 276 statCommittedInstType 277 .init(numThreads,Enums::Num_OpClass) 278 .name(name() + ".op_class") 279 .desc("Class of committed instruction") 280 .flags(total | pdf | dist) 281 ; 282 statCommittedInstType.ysubnames(Enums::OpClassStrings); 283 284 commitEligible 285 .init(cpu->numThreads) 286 .name(name() + ".bw_limited") 287 .desc("number of insts not committed due to BW limits") 288 .flags(total) 289 ; 290 291 commitEligibleSamples 292 .name(name() + ".bw_lim_events") 293 .desc("number cycles where commit BW limit reached") 294 ; 295} 296 297template <class Impl> 298void 299DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 300{ 301 thread = threads; 302} 303 304template <class Impl> 305void 306DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 307{ 308 timeBuffer = tb_ptr; 309 310 // Setup wire to send information back to IEW. 311 toIEW = timeBuffer->getWire(0); 312 313 // Setup wire to read data from IEW (for the ROB). 314 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 315} 316 317template <class Impl> 318void 319DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 320{ 321 fetchQueue = fq_ptr; 322 323 // Setup wire to get instructions from rename (for the ROB). 324 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 325} 326 327template <class Impl> 328void 329DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 330{ 331 renameQueue = rq_ptr; 332 333 // Setup wire to get instructions from rename (for the ROB). 334 fromRename = renameQueue->getWire(-renameToROBDelay); 335} 336 337template <class Impl> 338void 339DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 340{ 341 iewQueue = iq_ptr; 342 343 // Setup wire to get instructions from IEW. 344 fromIEW = iewQueue->getWire(-iewToCommitDelay); 345} 346 347template <class Impl> 348void 349DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 350{ 351 iewStage = iew_stage; 352} 353 354template<class Impl> 355void 356DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 357{ 358 activeThreads = at_ptr; 359} 360 361template <class Impl> 362void 363DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 364{ 365 for (ThreadID tid = 0; tid < numThreads; tid++) 366 renameMap[tid] = &rm_ptr[tid]; 367} 368 369template <class Impl> 370void 371DefaultCommit<Impl>::setROB(ROB *rob_ptr) 372{ 373 rob = rob_ptr; 374} 375 376template <class Impl> 377void 378DefaultCommit<Impl>::startupStage() 379{ 380 rob->setActiveThreads(activeThreads); 381 rob->resetEntries(); 382 383 // Broadcast the number of free entries. 384 for (ThreadID tid = 0; tid < numThreads; tid++) { 385 toIEW->commitInfo[tid].usedROB = true; 386 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 387 toIEW->commitInfo[tid].emptyROB = true; 388 } 389 390 // Commit must broadcast the number of free entries it has at the 391 // start of the simulation, so it starts as active. 392 cpu->activateStage(O3CPU::CommitIdx); 393 394 cpu->activityThisCycle(); 395} 396 397template <class Impl> 398void 399DefaultCommit<Impl>::drain() 400{ 401 drainPending = true; 402} 403 404template <class Impl> 405void 406DefaultCommit<Impl>::drainResume() 407{ 408 drainPending = false; 409} 410 411template <class Impl> 412void 413DefaultCommit<Impl>::drainSanityCheck() const 414{ 415 assert(isDrained()); 416 rob->drainSanityCheck(); 417} 418 419template <class Impl> 420bool 421DefaultCommit<Impl>::isDrained() const 422{ 423 /* Make sure no one is executing microcode. There are two reasons 424 * for this: 425 * - Hardware virtualized CPUs can't switch into the middle of a 426 * microcode sequence. 427 * - The current fetch implementation will most likely get very 428 * confused if it tries to start fetching an instruction that 429 * is executing in the middle of a ucode sequence that changes 430 * address mappings. This can happen on for example x86. 431 */ 432 for (ThreadID tid = 0; tid < numThreads; tid++) { 433 if (pc[tid].microPC() != 0) 434 return false; 435 } 436 437 /* Make sure that all instructions have finished committing before 438 * declaring the system as drained. We want the pipeline to be 439 * completely empty when we declare the CPU to be drained. This 440 * makes debugging easier since CPU handover and restoring from a 441 * checkpoint with a different CPU should have the same timing. 442 */ 443 return rob->isEmpty() && 444 interrupt == NoFault; 445} 446 447template <class Impl> 448void 449DefaultCommit<Impl>::takeOverFrom() 450{ 451 _status = Active; 452 _nextStatus = Inactive; 453 for (ThreadID tid = 0; tid < numThreads; tid++) { 454 commitStatus[tid] = Idle; 455 changedROBNumEntries[tid] = false; 456 trapSquash[tid] = false; 457 tcSquash[tid] = false; 458 squashAfterInst[tid] = NULL; 459 } 460 squashCounter = 0; 461 rob->takeOverFrom(); 462} 463 464template <class Impl> 465void 466DefaultCommit<Impl>::deactivateThread(ThreadID tid) 467{ 468 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(), 469 priority_list.end(), tid); 470 471 if (thread_it != priority_list.end()) { 472 priority_list.erase(thread_it); 473 } 474} 475 476 477template <class Impl> 478void 479DefaultCommit<Impl>::updateStatus() 480{ 481 // reset ROB changed variable 482 list<ThreadID>::iterator threads = activeThreads->begin(); 483 list<ThreadID>::iterator end = activeThreads->end(); 484 485 while (threads != end) { 486 ThreadID tid = *threads++; 487 488 changedROBNumEntries[tid] = false; 489 490 // Also check if any of the threads has a trap pending 491 if (commitStatus[tid] == TrapPending || 492 commitStatus[tid] == FetchTrapPending) { 493 _nextStatus = Active; 494 } 495 } 496 497 if (_nextStatus == Inactive && _status == Active) { 498 DPRINTF(Activity, "Deactivating stage.\n"); 499 cpu->deactivateStage(O3CPU::CommitIdx); 500 } else if (_nextStatus == Active && _status == Inactive) { 501 DPRINTF(Activity, "Activating stage.\n"); 502 cpu->activateStage(O3CPU::CommitIdx); 503 } 504 505 _status = _nextStatus; 506} 507 508template <class Impl> 509void 510DefaultCommit<Impl>::setNextStatus() 511{ 512 int squashes = 0; 513 514 list<ThreadID>::iterator threads = activeThreads->begin(); 515 list<ThreadID>::iterator end = activeThreads->end(); 516 517 while (threads != end) { 518 ThreadID tid = *threads++; 519 520 if (commitStatus[tid] == ROBSquashing) { 521 squashes++; 522 } 523 } 524 525 squashCounter = squashes; 526 527 // If commit is currently squashing, then it will have activity for the 528 // next cycle. Set its next status as active. 529 if (squashCounter) { 530 _nextStatus = Active; 531 } 532} 533 534template <class Impl> 535bool 536DefaultCommit<Impl>::changedROBEntries() 537{ 538 list<ThreadID>::iterator threads = activeThreads->begin(); 539 list<ThreadID>::iterator end = activeThreads->end(); 540 541 while (threads != end) { 542 ThreadID tid = *threads++; 543 544 if (changedROBNumEntries[tid]) { 545 return true; 546 } 547 } 548 549 return false; 550} 551 552template <class Impl> 553size_t 554DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 555{ 556 return rob->numFreeEntries(tid); 557} 558 559template <class Impl> 560void 561DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 562{ 563 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 564 565 TrapEvent *trap = new TrapEvent(this, tid); 566 567 cpu->schedule(trap, cpu->clockEdge(trapLatency)); 568 trapInFlight[tid] = true; 569 thread[tid]->trapPending = true; 570} 571 572template <class Impl> 573void 574DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 575{ 576 assert(!trapInFlight[tid]); 577 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 578 579 tcSquash[tid] = true; 580} 581 582template <class Impl> 583void 584DefaultCommit<Impl>::squashAll(ThreadID tid) 585{ 586 // If we want to include the squashing instruction in the squash, 587 // then use one older sequence number. 588 // Hopefully this doesn't mess things up. Basically I want to squash 589 // all instructions of this thread. 590 InstSeqNum squashed_inst = rob->isEmpty(tid) ? 591 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 592 593 // All younger instructions will be squashed. Set the sequence 594 // number as the youngest instruction in the ROB (0 in this case. 595 // Hopefully nothing breaks.) 596 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 597 598 rob->squash(squashed_inst, tid); 599 changedROBNumEntries[tid] = true; 600 601 // Send back the sequence number of the squashed instruction. 602 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 603 604 // Send back the squash signal to tell stages that they should 605 // squash. 606 toIEW->commitInfo[tid].squash = true; 607 608 // Send back the rob squashing signal so other stages know that 609 // the ROB is in the process of squashing. 610 toIEW->commitInfo[tid].robSquashing = true; 611 612 toIEW->commitInfo[tid].mispredictInst = NULL; 613 toIEW->commitInfo[tid].squashInst = NULL; 614 615 toIEW->commitInfo[tid].pc = pc[tid]; 616} 617 618template <class Impl> 619void 620DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 621{ 622 squashAll(tid); 623 624 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 625 626 thread[tid]->trapPending = false; 627 thread[tid]->noSquashFromTC = false; 628 trapInFlight[tid] = false; 629 630 trapSquash[tid] = false; 631 632 commitStatus[tid] = ROBSquashing; 633 cpu->activityThisCycle(); 634} 635 636template <class Impl> 637void 638DefaultCommit<Impl>::squashFromTC(ThreadID tid) 639{ 640 squashAll(tid); 641 642 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 643 644 thread[tid]->noSquashFromTC = false; 645 assert(!thread[tid]->trapPending); 646 647 commitStatus[tid] = ROBSquashing; 648 cpu->activityThisCycle(); 649 650 tcSquash[tid] = false; 651} 652 653template <class Impl> 654void 655DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 656{ 657 DPRINTF(Commit, "Squashing after squash after request, " 658 "restarting at PC %s\n", pc[tid]); 659 660 squashAll(tid); 661 // Make sure to inform the fetch stage of which instruction caused 662 // the squash. It'll try to re-fetch an instruction executing in 663 // microcode unless this is set. 664 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 665 squashAfterInst[tid] = NULL; 666 667 commitStatus[tid] = ROBSquashing; 668 cpu->activityThisCycle(); 669} 670 671template <class Impl> 672void 673DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 674{ 675 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 676 tid, head_inst->seqNum); 677 678 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 679 commitStatus[tid] = SquashAfterPending; 680 squashAfterInst[tid] = head_inst; 681} 682 683template <class Impl> 684void 685DefaultCommit<Impl>::tick() 686{ 687 wroteToTimeBuffer = false; 688 _nextStatus = Inactive; 689 690 if (activeThreads->empty()) 691 return; 692 693 list<ThreadID>::iterator threads = activeThreads->begin(); 694 list<ThreadID>::iterator end = activeThreads->end(); 695 696 // Check if any of the threads are done squashing. Change the 697 // status if they are done. 698 while (threads != end) { 699 ThreadID tid = *threads++; 700 701 // Clear the bit saying if the thread has committed stores 702 // this cycle. 703 committedStores[tid] = false; 704 705 if (commitStatus[tid] == ROBSquashing) { 706 707 if (rob->isDoneSquashing(tid)) { 708 commitStatus[tid] = Running; 709 } else { 710 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 711 " insts this cycle.\n", tid); 712 rob->doSquash(tid); 713 toIEW->commitInfo[tid].robSquashing = true; 714 wroteToTimeBuffer = true; 715 } 716 } 717 } 718 719 commit(); 720 721 markCompletedInsts(); 722 723 threads = activeThreads->begin(); 724 725 while (threads != end) { 726 ThreadID tid = *threads++; 727 728 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 729 // The ROB has more instructions it can commit. Its next status 730 // will be active. 731 _nextStatus = Active; 732 733 DynInstPtr inst = rob->readHeadInst(tid); 734 735 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 736 " ROB and ready to commit\n", 737 tid, inst->seqNum, inst->pcState()); 738 739 } else if (!rob->isEmpty(tid)) { 740 DynInstPtr inst = rob->readHeadInst(tid); 741 742 ppCommitStall->notify(inst); 743 744 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 745 "%s is head of ROB and not ready\n", 746 tid, inst->seqNum, inst->pcState()); 747 } 748 749 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 750 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 751 } 752 753 754 if (wroteToTimeBuffer) { 755 DPRINTF(Activity, "Activity This Cycle.\n"); 756 cpu->activityThisCycle(); 757 } 758 759 updateStatus(); 760} 761 762template <class Impl> 763void 764DefaultCommit<Impl>::handleInterrupt() 765{ 766 // Verify that we still have an interrupt to handle 767 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 768 DPRINTF(Commit, "Pending interrupt is cleared by master before " 769 "it got handled. Restart fetching from the orig path.\n"); 770 toIEW->commitInfo[0].clearInterrupt = true; 771 interrupt = NoFault; 772 avoidQuiesceLiveLock = true; 773 return; 774 } 775 776 // Wait until all in flight instructions are finished before enterring 777 // the interrupt. 778 if (canHandleInterrupts && cpu->instList.empty()) { 779 // Squash or record that I need to squash this cycle if 780 // an interrupt needed to be handled. 781 DPRINTF(Commit, "Interrupt detected.\n"); 782 783 // Clear the interrupt now that it's going to be handled 784 toIEW->commitInfo[0].clearInterrupt = true; 785 786 assert(!thread[0]->noSquashFromTC); 787 thread[0]->noSquashFromTC = true; 788 789 if (cpu->checker) { 790 cpu->checker->handlePendingInt(); 791 } 792 793 // CPU will handle interrupt. Note that we ignore the local copy of 794 // interrupt. This is because the local copy may no longer be the 795 // interrupt that the interrupt controller thinks is being handled. 796 cpu->processInterrupts(cpu->getInterrupts()); 797 798 thread[0]->noSquashFromTC = false; 799 800 commitStatus[0] = TrapPending; 801 802 // Generate trap squash event. 803 generateTrapEvent(0); 804 805 interrupt = NoFault; 806 avoidQuiesceLiveLock = false; 807 } else { 808 DPRINTF(Commit, "Interrupt pending: instruction is %sin " 809 "flight, ROB is %sempty\n", 810 canHandleInterrupts ? "not " : "", 811 cpu->instList.empty() ? "" : "not " ); 812 } 813} 814 815template <class Impl> 816void 817DefaultCommit<Impl>::propagateInterrupt() 818{ 819 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 820 tcSquash[0]) 821 return; 822 823 // Process interrupts if interrupts are enabled, not in PAL 824 // mode, and no other traps or external squashes are currently 825 // pending. 826 // @todo: Allow other threads to handle interrupts. 827 828 // Get any interrupt that happened 829 interrupt = cpu->getInterrupts(); 830 831 // Tell fetch that there is an interrupt pending. This 832 // will make fetch wait until it sees a non PAL-mode PC, 833 // at which point it stops fetching instructions. 834 if (interrupt != NoFault) 835 toIEW->commitInfo[0].interruptPending = true; 836} 837 838template <class Impl> 839void 840DefaultCommit<Impl>::commit() 841{ 842 if (FullSystem) { 843 // Check if we have a interrupt and get read to handle it 844 if (cpu->checkInterrupts(cpu->tcBase(0))) 845 propagateInterrupt(); 846 } 847 848 //////////////////////////////////// 849 // Check for any possible squashes, handle them first 850 //////////////////////////////////// 851 list<ThreadID>::iterator threads = activeThreads->begin(); 852 list<ThreadID>::iterator end = activeThreads->end(); 853 854 while (threads != end) { 855 ThreadID tid = *threads++; 856 857 // Not sure which one takes priority. I think if we have 858 // both, that's a bad sign. 859 if (trapSquash[tid]) { 860 assert(!tcSquash[tid]); 861 squashFromTrap(tid); 862 } else if (tcSquash[tid]) { 863 assert(commitStatus[tid] != TrapPending); 864 squashFromTC(tid); 865 } else if (commitStatus[tid] == SquashAfterPending) { 866 // A squash from the previous cycle of the commit stage (i.e., 867 // commitInsts() called squashAfter) is pending. Squash the 868 // thread now. 869 squashFromSquashAfter(tid); 870 } 871 872 // Squashed sequence number must be older than youngest valid 873 // instruction in the ROB. This prevents squashes from younger 874 // instructions overriding squashes from older instructions. 875 if (fromIEW->squash[tid] && 876 commitStatus[tid] != TrapPending && 877 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 878 879 if (fromIEW->mispredictInst[tid]) { 880 DPRINTF(Commit, 881 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 882 tid, 883 fromIEW->mispredictInst[tid]->instAddr(), 884 fromIEW->squashedSeqNum[tid]); 885 } else { 886 DPRINTF(Commit, 887 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 888 tid, fromIEW->squashedSeqNum[tid]); 889 } 890 891 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 892 tid, 893 fromIEW->pc[tid].nextInstAddr()); 894 895 commitStatus[tid] = ROBSquashing; 896 897 // If we want to include the squashing instruction in the squash, 898 // then use one older sequence number. 899 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 900 901 if (fromIEW->includeSquashInst[tid]) { 902 squashed_inst--; 903 } 904 905 // All younger instructions will be squashed. Set the sequence 906 // number as the youngest instruction in the ROB. 907 youngestSeqNum[tid] = squashed_inst; 908 909 rob->squash(squashed_inst, tid); 910 changedROBNumEntries[tid] = true; 911 912 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 913 914 toIEW->commitInfo[tid].squash = true; 915 916 // Send back the rob squashing signal so other stages know that 917 // the ROB is in the process of squashing. 918 toIEW->commitInfo[tid].robSquashing = true; 919 920 toIEW->commitInfo[tid].mispredictInst = 921 fromIEW->mispredictInst[tid]; 922 toIEW->commitInfo[tid].branchTaken = 923 fromIEW->branchTaken[tid]; 924 toIEW->commitInfo[tid].squashInst = 925 rob->findInst(tid, squashed_inst); 926 if (toIEW->commitInfo[tid].mispredictInst) { 927 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 928 toIEW->commitInfo[tid].branchTaken = true; 929 } 930 } 931 932 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 933 934 if (toIEW->commitInfo[tid].mispredictInst) { 935 ++branchMispredicts; 936 } 937 } 938 939 } 940 941 setNextStatus(); 942 943 if (squashCounter != numThreads) { 944 // If we're not currently squashing, then get instructions. 945 getInsts(); 946 947 // Try to commit any instructions. 948 commitInsts(); 949 } 950 951 //Check for any activity 952 threads = activeThreads->begin(); 953 954 while (threads != end) { 955 ThreadID tid = *threads++; 956 957 if (changedROBNumEntries[tid]) { 958 toIEW->commitInfo[tid].usedROB = true; 959 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 960 961 wroteToTimeBuffer = true; 962 changedROBNumEntries[tid] = false; 963 if (rob->isEmpty(tid)) 964 checkEmptyROB[tid] = true; 965 } 966 967 // ROB is only considered "empty" for previous stages if: a) 968 // ROB is empty, b) there are no outstanding stores, c) IEW 969 // stage has received any information regarding stores that 970 // committed. 971 // c) is checked by making sure to not consider the ROB empty 972 // on the same cycle as when stores have been committed. 973 // @todo: Make this handle multi-cycle communication between 974 // commit and IEW. 975 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 976 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 977 checkEmptyROB[tid] = false; 978 toIEW->commitInfo[tid].usedROB = true; 979 toIEW->commitInfo[tid].emptyROB = true; 980 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 981 wroteToTimeBuffer = true; 982 } 983 984 } 985} 986 987template <class Impl> 988void 989DefaultCommit<Impl>::commitInsts() 990{ 991 //////////////////////////////////// 992 // Handle commit 993 // Note that commit will be handled prior to putting new 994 // instructions in the ROB so that the ROB only tries to commit 995 // instructions it has in this current cycle, and not instructions 996 // it is writing in during this cycle. Can't commit and squash 997 // things at the same time... 998 //////////////////////////////////// 999 1000 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 1001 1002 unsigned num_committed = 0; 1003 1004 DynInstPtr head_inst; 1005 1006 // Commit as many instructions as possible until the commit bandwidth 1007 // limit is reached, or it becomes impossible to commit any more. 1008 while (num_committed < commitWidth) { 1009 // Check for any interrupt that we've already squashed for 1010 // and start processing it. 1011 if (interrupt != NoFault) 1012 handleInterrupt(); 1013 1014 int commit_thread = getCommittingThread(); 1015 1016 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 1017 break; 1018 1019 head_inst = rob->readHeadInst(commit_thread); 1020 1021 ThreadID tid = head_inst->threadNumber; 1022 1023 assert(tid == commit_thread); 1024 1025 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 1026 head_inst->seqNum, tid); 1027 1028 // If the head instruction is squashed, it is ready to retire 1029 // (be removed from the ROB) at any time. 1030 if (head_inst->isSquashed()) { 1031 1032 DPRINTF(Commit, "Retiring squashed instruction from " 1033 "ROB.\n"); 1034 1035 rob->retireHead(commit_thread); 1036 1037 ++commitSquashedInsts; 1038 1039 // Record that the number of ROB entries has changed. 1040 changedROBNumEntries[tid] = true; 1041 } else { 1042 pc[tid] = head_inst->pcState(); 1043 1044 // Increment the total number of non-speculative instructions 1045 // executed. 1046 // Hack for now: it really shouldn't happen until after the 1047 // commit is deemed to be successful, but this count is needed 1048 // for syscalls. 1049 thread[tid]->funcExeInst++; 1050 1051 // Try to commit the head instruction. 1052 bool commit_success = commitHead(head_inst, num_committed); 1053 1054 if (commit_success) { 1055 ++num_committed; 1056 statCommittedInstType[tid][head_inst->opClass()]++; 1057 ppCommit->notify(head_inst); 1058 1059 changedROBNumEntries[tid] = true; 1060 1061 // Set the doneSeqNum to the youngest committed instruction. 1062 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 1063 1064 if (tid == 0) { 1065 canHandleInterrupts = (!head_inst->isDelayedCommit()) && 1066 ((THE_ISA != ALPHA_ISA) || 1067 (!(pc[0].instAddr() & 0x3))); 1068 } 1069 1070 // Updates misc. registers. 1071 head_inst->updateMiscRegs(); 1072 1073 // Check instruction execution if it successfully commits and 1074 // is not carrying a fault. 1075 if (cpu->checker) { 1076 cpu->checker->verify(head_inst); 1077 } 1078 1079 cpu->traceFunctions(pc[tid].instAddr()); 1080 1081 TheISA::advancePC(pc[tid], head_inst->staticInst); 1082 1083 // Keep track of the last sequence number commited 1084 lastCommitedSeqNum[tid] = head_inst->seqNum; 1085 1086 // If this is an instruction that doesn't play nicely with 1087 // others squash everything and restart fetch 1088 if (head_inst->isSquashAfter()) 1089 squashAfter(tid, head_inst); 1090 1091 if (drainPending) { 1092 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 1093 if (pc[tid].microPC() == 0 && interrupt == NoFault) { 1094 squashAfter(tid, head_inst); 1095 cpu->commitDrained(tid); 1096 } 1097 } 1098 1099 int count = 0; 1100 Addr oldpc; 1101 // Debug statement. Checks to make sure we're not 1102 // currently updating state while handling PC events. 1103 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending); 1104 do { 1105 oldpc = pc[tid].instAddr(); 1106 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1107 count++; 1108 } while (oldpc != pc[tid].instAddr()); 1109 if (count > 1) { 1110 DPRINTF(Commit, 1111 "PC skip function event, stopping commit\n"); 1112 break; 1113 } 1114 1115 // Check if an instruction just enabled interrupts and we've 1116 // previously had an interrupt pending that was not handled 1117 // because interrupts were subsequently disabled before the 1118 // pipeline reached a place to handle the interrupt. In that 1119 // case squash now to make sure the interrupt is handled. 1120 // 1121 // If we don't do this, we might end up in a live lock situation 1122 if (!interrupt && avoidQuiesceLiveLock && 1123 (!head_inst->isMicroop() || head_inst->isLastMicroop()) && 1124 cpu->checkInterrupts(cpu->tcBase(0))) 1125 squashAfter(tid, head_inst); 1126 } else { 1127 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1128 "[tid:%i] [sn:%i].\n", 1129 head_inst->pcState(), tid ,head_inst->seqNum); 1130 break; 1131 } 1132 } 1133 } 1134 1135 DPRINTF(CommitRate, "%i\n", num_committed); 1136 numCommittedDist.sample(num_committed); 1137 1138 if (num_committed == commitWidth) { 1139 commitEligibleSamples++; 1140 } 1141} 1142 1143template <class Impl> 1144bool 1145DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1146{ 1147 assert(head_inst); 1148 1149 ThreadID tid = head_inst->threadNumber; 1150 1151 // If the instruction is not executed yet, then it will need extra 1152 // handling. Signal backwards that it should be executed. 1153 if (!head_inst->isExecuted()) { 1154 // Keep this number correct. We have not yet actually executed 1155 // and committed this instruction. 1156 thread[tid]->funcExeInst--; 1157 1158 // Make sure we are only trying to commit un-executed instructions we 1159 // think are possible. 1160 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 1161 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 1162 (head_inst->isLoad() && head_inst->uncacheable())); 1163 1164 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1165 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1166 head_inst->seqNum, head_inst->pcState()); 1167 1168 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1169 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1170 return false; 1171 } 1172 1173 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1174 1175 // Change the instruction so it won't try to commit again until 1176 // it is executed. 1177 head_inst->clearCanCommit(); 1178 1179 if (head_inst->isLoad() && head_inst->uncacheable()) { 1180 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1181 head_inst->seqNum, head_inst->pcState()); 1182 toIEW->commitInfo[tid].uncached = true; 1183 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1184 } else { 1185 ++commitNonSpecStalls; 1186 } 1187 1188 return false; 1189 } 1190 1191 if (head_inst->isThreadSync()) { 1192 // Not handled for now. 1193 panic("Thread sync instructions are not handled yet.\n"); 1194 } 1195 1196 // Check if the instruction caused a fault. If so, trap. 1197 Fault inst_fault = head_inst->getFault(); 1198 1199 // Stores mark themselves as completed. 1200 if (!head_inst->isStore() && inst_fault == NoFault) { 1201 head_inst->setCompleted(); 1202 } 1203 1204 if (inst_fault != NoFault) { 1205 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1206 head_inst->seqNum, head_inst->pcState()); 1207 1208 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1209 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1210 return false; 1211 } 1212 1213 head_inst->setCompleted(); 1214 1215 // If instruction has faulted, let the checker execute it and 1216 // check if it sees the same fault and control flow. 1217 if (cpu->checker) { 1218 // Need to check the instruction before its fault is processed 1219 cpu->checker->verify(head_inst); 1220 } 1221 1222 assert(!thread[tid]->noSquashFromTC); 1223 1224 // Mark that we're in state update mode so that the trap's 1225 // execution doesn't generate extra squashes. 1226 thread[tid]->noSquashFromTC = true; 1227 1228 // Execute the trap. Although it's slightly unrealistic in 1229 // terms of timing (as it doesn't wait for the full timing of 1230 // the trap event to complete before updating state), it's 1231 // needed to update the state as soon as possible. This 1232 // prevents external agents from changing any specific state 1233 // that the trap need. 1234 cpu->trap(inst_fault, tid, head_inst->staticInst); 1235 1236 // Exit state update mode to avoid accidental updating. 1237 thread[tid]->noSquashFromTC = false; 1238 1239 commitStatus[tid] = TrapPending; 1240 1241 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1242 head_inst->seqNum); 1243 if (head_inst->traceData) { 1244 if (DTRACE(ExecFaulting)) { 1245 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1246 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1247 head_inst->traceData->dump(); 1248 } 1249 delete head_inst->traceData; 1250 head_inst->traceData = NULL; 1251 } 1252 1253 // Generate trap squash event. 1254 generateTrapEvent(tid); 1255 return false; 1256 } 1257 1258 updateComInstStats(head_inst); 1259 1260 if (FullSystem) { 1261 if (thread[tid]->profile) { 1262 thread[tid]->profilePC = head_inst->instAddr(); 1263 ProfileNode *node = thread[tid]->profile->consume( 1264 thread[tid]->getTC(), head_inst->staticInst); 1265 1266 if (node) 1267 thread[tid]->profileNode = node; 1268 } 1269 if (CPA::available()) { 1270 if (head_inst->isControl()) { 1271 ThreadContext *tc = thread[tid]->getTC(); 1272 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1273 } 1274 } 1275 } 1276 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1277 head_inst->seqNum, head_inst->pcState()); 1278 if (head_inst->traceData) { 1279 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1280 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1281 head_inst->traceData->dump(); 1282 delete head_inst->traceData; 1283 head_inst->traceData = NULL; 1284 } 1285 if (head_inst->isReturn()) { 1286 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 1287 head_inst->seqNum, head_inst->pcState()); 1288 } 1289 1290 // Update the commit rename map 1291 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1292 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1293 head_inst->renamedDestRegIdx(i)); 1294 } 1295 1296 // Finally clear the head ROB entry. 1297 rob->retireHead(tid); 1298 1299#if TRACING_ON 1300 if (DTRACE(O3PipeView)) { 1301 head_inst->commitTick = curTick() - head_inst->fetchTick; 1302 } 1303#endif 1304 1305 // If this was a store, record it for this cycle. 1306 if (head_inst->isStore()) 1307 committedStores[tid] = true; 1308 1309 // Return true to indicate that we have committed an instruction. 1310 return true; 1311} 1312 1313template <class Impl> 1314void 1315DefaultCommit<Impl>::getInsts() 1316{ 1317 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1318 1319 // Read any renamed instructions and place them into the ROB. 1320 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1321 1322 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1323 DynInstPtr inst; 1324 1325 inst = fromRename->insts[inst_num]; 1326 ThreadID tid = inst->threadNumber; 1327 1328 if (!inst->isSquashed() && 1329 commitStatus[tid] != ROBSquashing && 1330 commitStatus[tid] != TrapPending) { 1331 changedROBNumEntries[tid] = true; 1332 1333 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1334 inst->pcState(), inst->seqNum, tid); 1335 1336 rob->insertInst(inst); 1337 1338 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1339 1340 youngestSeqNum[tid] = inst->seqNum; 1341 } else { 1342 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1343 "squashed, skipping.\n", 1344 inst->pcState(), inst->seqNum, tid); 1345 } 1346 } 1347} 1348 1349template <class Impl> 1350void 1351DefaultCommit<Impl>::markCompletedInsts() 1352{ 1353 // Grab completed insts out of the IEW instruction queue, and mark 1354 // instructions completed within the ROB. 1355 for (int inst_num = 0; 1356 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1357 ++inst_num) 1358 { 1359 if (!fromIEW->insts[inst_num]->isSquashed()) { 1360 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1361 "within ROB.\n", 1362 fromIEW->insts[inst_num]->threadNumber, 1363 fromIEW->insts[inst_num]->pcState(), 1364 fromIEW->insts[inst_num]->seqNum); 1365 1366 // Mark the instruction as ready to commit. 1367 fromIEW->insts[inst_num]->setCanCommit(); 1368 } 1369 } 1370} 1371 1372template <class Impl> 1373void 1374DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1375{ 1376 ThreadID tid = inst->threadNumber; 1377 1378 if (!inst->isMicroop() || inst->isLastMicroop()) 1379 instsCommitted[tid]++; 1380 opsCommitted[tid]++; 1381 1382 // To match the old model, don't count nops and instruction 1383 // prefetches towards the total commit count. 1384 if (!inst->isNop() && !inst->isInstPrefetch()) { 1385 cpu->instDone(tid, inst); 1386 } 1387 1388 // 1389 // Control Instructions 1390 // 1391 if (inst->isControl()) 1392 statComBranches[tid]++; 1393 1394 // 1395 // Memory references 1396 // 1397 if (inst->isMemRef()) { 1398 statComRefs[tid]++; 1399 1400 if (inst->isLoad()) { 1401 statComLoads[tid]++; 1402 } 1403 } 1404 1405 if (inst->isMemBarrier()) { 1406 statComMembars[tid]++; 1407 } 1408 1409 // Integer Instruction 1410 if (inst->isInteger()) 1411 statComInteger[tid]++; 1412 1413 // Floating Point Instruction 1414 if (inst->isFloating()) 1415 statComFloating[tid]++; 1416 1417 // Function Calls 1418 if (inst->isCall()) 1419 statComFunctionCalls[tid]++; 1420 1421} 1422 1423//////////////////////////////////////// 1424// // 1425// SMT COMMIT POLICY MAINTAINED HERE // 1426// // 1427//////////////////////////////////////// 1428template <class Impl> 1429ThreadID 1430DefaultCommit<Impl>::getCommittingThread() 1431{ 1432 if (numThreads > 1) { 1433 switch (commitPolicy) { 1434 1435 case Aggressive: 1436 //If Policy is Aggressive, commit will call 1437 //this function multiple times per 1438 //cycle 1439 return oldestReady(); 1440 1441 case RoundRobin: 1442 return roundRobin(); 1443 1444 case OldestReady: 1445 return oldestReady(); 1446 1447 default: 1448 return InvalidThreadID; 1449 } 1450 } else { 1451 assert(!activeThreads->empty()); 1452 ThreadID tid = activeThreads->front(); 1453 1454 if (commitStatus[tid] == Running || 1455 commitStatus[tid] == Idle || 1456 commitStatus[tid] == FetchTrapPending) { 1457 return tid; 1458 } else { 1459 return InvalidThreadID; 1460 } 1461 } 1462} 1463 1464template<class Impl> 1465ThreadID 1466DefaultCommit<Impl>::roundRobin() 1467{ 1468 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1469 list<ThreadID>::iterator end = priority_list.end(); 1470 1471 while (pri_iter != end) { 1472 ThreadID tid = *pri_iter; 1473 1474 if (commitStatus[tid] == Running || 1475 commitStatus[tid] == Idle || 1476 commitStatus[tid] == FetchTrapPending) { 1477 1478 if (rob->isHeadReady(tid)) { 1479 priority_list.erase(pri_iter); 1480 priority_list.push_back(tid); 1481 1482 return tid; 1483 } 1484 } 1485 1486 pri_iter++; 1487 } 1488 1489 return InvalidThreadID; 1490} 1491 1492template<class Impl> 1493ThreadID 1494DefaultCommit<Impl>::oldestReady() 1495{ 1496 unsigned oldest = 0; 1497 bool first = true; 1498 1499 list<ThreadID>::iterator threads = activeThreads->begin(); 1500 list<ThreadID>::iterator end = activeThreads->end(); 1501 1502 while (threads != end) { 1503 ThreadID tid = *threads++; 1504 1505 if (!rob->isEmpty(tid) && 1506 (commitStatus[tid] == Running || 1507 commitStatus[tid] == Idle || 1508 commitStatus[tid] == FetchTrapPending)) { 1509 1510 if (rob->isHeadReady(tid)) { 1511 1512 DynInstPtr head_inst = rob->readHeadInst(tid); 1513 1514 if (first) { 1515 oldest = tid; 1516 first = false; 1517 } else if (head_inst->seqNum < oldest) { 1518 oldest = tid; 1519 } 1520 } 1521 } 1522 } 1523 1524 if (!first) { 1525 return oldest; 1526 } else { 1527 return InvalidThreadID; 1528 } 1529} 1530 1531#endif//__CPU_O3_COMMIT_IMPL_HH__ 1532