commit.hh revision 9437:8088e94a9de0
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#ifndef __CPU_O3_COMMIT_HH__ 45#define __CPU_O3_COMMIT_HH__ 46 47#include <queue> 48 49#include "base/statistics.hh" 50#include "cpu/exetrace.hh" 51#include "cpu/inst_seq.hh" 52#include "cpu/timebuf.hh" 53 54struct DerivO3CPUParams; 55 56template <class> 57struct O3ThreadState; 58 59/** 60 * DefaultCommit handles single threaded and SMT commit. Its width is 61 * specified by the parameters; each cycle it tries to commit that 62 * many instructions. The SMT policy decides which thread it tries to 63 * commit instructions from. Non- speculative instructions must reach 64 * the head of the ROB before they are ready to execute; once they 65 * reach the head, commit will broadcast the instruction's sequence 66 * number to the previous stages so that they can issue/ execute the 67 * instruction. Only one non-speculative instruction is handled per 68 * cycle. Commit is responsible for handling all back-end initiated 69 * redirects. It receives the redirect, and then broadcasts it to all 70 * stages, indicating the sequence number they should squash until, 71 * and any necessary branch misprediction information as well. It 72 * priortizes redirects by instruction's age, only broadcasting a 73 * redirect if it corresponds to an instruction that should currently 74 * be in the ROB. This is done by tracking the sequence number of the 75 * youngest instruction in the ROB, which gets updated to any 76 * squashing instruction's sequence number, and only broadcasting a 77 * redirect if it corresponds to an older instruction. Commit also 78 * supports multiple cycle squashing, to model a ROB that can only 79 * remove a certain number of instructions per cycle. 80 */ 81template<class Impl> 82class DefaultCommit 83{ 84 public: 85 // Typedefs from the Impl. 86 typedef typename Impl::O3CPU O3CPU; 87 typedef typename Impl::DynInstPtr DynInstPtr; 88 typedef typename Impl::CPUPol CPUPol; 89 90 typedef typename CPUPol::RenameMap RenameMap; 91 typedef typename CPUPol::ROB ROB; 92 93 typedef typename CPUPol::TimeStruct TimeStruct; 94 typedef typename CPUPol::FetchStruct FetchStruct; 95 typedef typename CPUPol::IEWStruct IEWStruct; 96 typedef typename CPUPol::RenameStruct RenameStruct; 97 98 typedef typename CPUPol::Fetch Fetch; 99 typedef typename CPUPol::IEW IEW; 100 101 typedef O3ThreadState<Impl> Thread; 102 103 /** Event class used to schedule a squash due to a trap (fault or 104 * interrupt) to happen on a specific cycle. 105 */ 106 class TrapEvent : public Event { 107 private: 108 DefaultCommit<Impl> *commit; 109 ThreadID tid; 110 111 public: 112 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 113 114 void process(); 115 const char *description() const; 116 }; 117 118 /** Overall commit status. Used to determine if the CPU can deschedule 119 * itself due to a lack of activity. 120 */ 121 enum CommitStatus{ 122 Active, 123 Inactive 124 }; 125 126 /** Individual thread status. */ 127 enum ThreadStatus { 128 Running, 129 Idle, 130 ROBSquashing, 131 TrapPending, 132 FetchTrapPending, 133 SquashAfterPending, //< Committing instructions before a squash. 134 }; 135 136 /** Commit policy for SMT mode. */ 137 enum CommitPolicy { 138 Aggressive, 139 RoundRobin, 140 OldestReady 141 }; 142 143 private: 144 /** Overall commit status. */ 145 CommitStatus _status; 146 /** Next commit status, to be set at the end of the cycle. */ 147 CommitStatus _nextStatus; 148 /** Per-thread status. */ 149 ThreadStatus commitStatus[Impl::MaxThreads]; 150 /** Commit policy used in SMT mode. */ 151 CommitPolicy commitPolicy; 152 153 public: 154 /** Construct a DefaultCommit with the given parameters. */ 155 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 156 157 /** Returns the name of the DefaultCommit. */ 158 std::string name() const; 159 160 /** Registers statistics. */ 161 void regStats(); 162 163 /** Sets the list of threads. */ 164 void setThreads(std::vector<Thread *> &threads); 165 166 /** Sets the main time buffer pointer, used for backwards communication. */ 167 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 168 169 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 170 171 /** Sets the pointer to the queue coming from rename. */ 172 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 173 174 /** Sets the pointer to the queue coming from IEW. */ 175 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 176 177 /** Sets the pointer to the IEW stage. */ 178 void setIEWStage(IEW *iew_stage); 179 180 /** Skid buffer between rename and commit. */ 181 std::queue<DynInstPtr> skidBuffer; 182 183 /** The pointer to the IEW stage. Used solely to ensure that 184 * various events (traps, interrupts, syscalls) do not occur until 185 * all stores have written back. 186 */ 187 IEW *iewStage; 188 189 /** Sets pointer to list of active threads. */ 190 void setActiveThreads(std::list<ThreadID> *at_ptr); 191 192 /** Sets pointer to the commited state rename map. */ 193 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 194 195 /** Sets pointer to the ROB. */ 196 void setROB(ROB *rob_ptr); 197 198 /** Initializes stage by sending back the number of free entries. */ 199 void startupStage(); 200 201 /** Initializes the draining of commit. */ 202 bool drain(); 203 204 /** Resumes execution after draining. */ 205 void resume(); 206 207 /** Completes the switch out of commit. */ 208 void switchOut(); 209 210 /** Takes over from another CPU's thread. */ 211 void takeOverFrom(); 212 213 /** Ticks the commit stage, which tries to commit instructions. */ 214 void tick(); 215 216 /** Handles any squashes that are sent from IEW, and adds instructions 217 * to the ROB and tries to commit instructions. 218 */ 219 void commit(); 220 221 /** Returns the number of free ROB entries for a specific thread. */ 222 size_t numROBFreeEntries(ThreadID tid); 223 224 /** Generates an event to schedule a squash due to a trap. */ 225 void generateTrapEvent(ThreadID tid); 226 227 /** Records that commit needs to initiate a squash due to an 228 * external state update through the TC. 229 */ 230 void generateTCEvent(ThreadID tid); 231 232 private: 233 /** Updates the overall status of commit with the nextStatus, and 234 * tell the CPU if commit is active/inactive. 235 */ 236 void updateStatus(); 237 238 /** Sets the next status based on threads' statuses, which becomes the 239 * current status at the end of the cycle. 240 */ 241 void setNextStatus(); 242 243 /** Checks if the ROB is completed with squashing. This is for the case 244 * where the ROB can take multiple cycles to complete squashing. 245 */ 246 bool robDoneSquashing(); 247 248 /** Returns if any of the threads have the number of ROB entries changed 249 * on this cycle. Used to determine if the number of free ROB entries needs 250 * to be sent back to previous stages. 251 */ 252 bool changedROBEntries(); 253 254 /** Squashes all in flight instructions. */ 255 void squashAll(ThreadID tid); 256 257 /** Handles squashing due to a trap. */ 258 void squashFromTrap(ThreadID tid); 259 260 /** Handles squashing due to an TC write. */ 261 void squashFromTC(ThreadID tid); 262 263 /** Handles a squash from a squashAfter() request. */ 264 void squashFromSquashAfter(ThreadID tid); 265 266 /** 267 * Handle squashing from instruction with SquashAfter set. 268 * 269 * This differs from the other squashes as it squashes following 270 * instructions instead of the current instruction and doesn't 271 * clean up various status bits about traps/tc writes 272 * pending. Since there might have been instructions committed by 273 * the commit stage before the squashing instruction was reached 274 * and we can't commit and squash in the same cycle, we have to 275 * squash in two steps: 276 * 277 * <ol> 278 * <li>Immediately set the commit status of the thread of 279 * SquashAfterPending. This forces the thread to stop 280 * committing instructions in this cycle. The last 281 * instruction to be committed in this cycle will be the 282 * SquashAfter instruction. 283 * <li>In the next cycle, commit() checks for the 284 * SquashAfterPending state and squashes <i>all</i> 285 * in-flight instructions. Since the SquashAfter instruction 286 * was the last instruction to be committed in the previous 287 * cycle, this causes all subsequent instructions to be 288 * squashed. 289 * </ol> 290 * 291 * @param tid ID of the thread to squash. 292 * @param head_inst Instruction that requested the squash. 293 */ 294 void squashAfter(ThreadID tid, DynInstPtr &head_inst); 295 296 /** Handles processing an interrupt. */ 297 void handleInterrupt(); 298 299 /** Get fetch redirecting so we can handle an interrupt */ 300 void propagateInterrupt(); 301 302 /** Commits as many instructions as possible. */ 303 void commitInsts(); 304 305 /** Tries to commit the head ROB instruction passed in. 306 * @param head_inst The instruction to be committed. 307 */ 308 bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 309 310 /** Gets instructions from rename and inserts them into the ROB. */ 311 void getInsts(); 312 313 /** Insert all instructions from rename into skidBuffer */ 314 void skidInsert(); 315 316 /** Marks completed instructions using information sent from IEW. */ 317 void markCompletedInsts(); 318 319 /** Gets the thread to commit, based on the SMT policy. */ 320 ThreadID getCommittingThread(); 321 322 /** Returns the thread ID to use based on a round robin policy. */ 323 ThreadID roundRobin(); 324 325 /** Returns the thread ID to use based on an oldest instruction policy. */ 326 ThreadID oldestReady(); 327 328 public: 329 /** Reads the PC of a specific thread. */ 330 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 331 332 /** Sets the PC of a specific thread. */ 333 void pcState(const TheISA::PCState &val, ThreadID tid) 334 { pc[tid] = val; } 335 336 /** Returns the PC of a specific thread. */ 337 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 338 339 /** Returns the next PC of a specific thread. */ 340 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 341 342 /** Reads the micro PC of a specific thread. */ 343 Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 344 345 private: 346 /** Time buffer interface. */ 347 TimeBuffer<TimeStruct> *timeBuffer; 348 349 /** Wire to write information heading to previous stages. */ 350 typename TimeBuffer<TimeStruct>::wire toIEW; 351 352 /** Wire to read information from IEW (for ROB). */ 353 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 354 355 TimeBuffer<FetchStruct> *fetchQueue; 356 357 typename TimeBuffer<FetchStruct>::wire fromFetch; 358 359 /** IEW instruction queue interface. */ 360 TimeBuffer<IEWStruct> *iewQueue; 361 362 /** Wire to read information from IEW queue. */ 363 typename TimeBuffer<IEWStruct>::wire fromIEW; 364 365 /** Rename instruction queue interface, for ROB. */ 366 TimeBuffer<RenameStruct> *renameQueue; 367 368 /** Wire to read information from rename queue. */ 369 typename TimeBuffer<RenameStruct>::wire fromRename; 370 371 public: 372 /** ROB interface. */ 373 ROB *rob; 374 375 private: 376 /** Pointer to O3CPU. */ 377 O3CPU *cpu; 378 379 /** Vector of all of the threads. */ 380 std::vector<Thread *> thread; 381 382 /** Records that commit has written to the time buffer this cycle. Used for 383 * the CPU to determine if it can deschedule itself if there is no activity. 384 */ 385 bool wroteToTimeBuffer; 386 387 /** Records if the number of ROB entries has changed this cycle. If it has, 388 * then the number of free entries must be re-broadcast. 389 */ 390 bool changedROBNumEntries[Impl::MaxThreads]; 391 392 /** A counter of how many threads are currently squashing. */ 393 ThreadID squashCounter; 394 395 /** Records if a thread has to squash this cycle due to a trap. */ 396 bool trapSquash[Impl::MaxThreads]; 397 398 /** Records if a thread has to squash this cycle due to an XC write. */ 399 bool tcSquash[Impl::MaxThreads]; 400 401 /** 402 * Instruction passed to squashAfter(). 403 * 404 * The squash after implementation needs to buffer the instruction 405 * that caused a squash since this needs to be passed to the fetch 406 * stage once squashing starts. 407 */ 408 DynInstPtr squashAfterInst[Impl::MaxThreads]; 409 410 /** Priority List used for Commit Policy */ 411 std::list<ThreadID> priority_list; 412 413 /** IEW to Commit delay. */ 414 Cycles iewToCommitDelay; 415 416 /** Commit to IEW delay. */ 417 Cycles commitToIEWDelay; 418 419 /** Rename to ROB delay. */ 420 Cycles renameToROBDelay; 421 422 Cycles fetchToCommitDelay; 423 424 /** Rename width, in instructions. Used so ROB knows how many 425 * instructions to get from the rename instruction queue. 426 */ 427 unsigned renameWidth; 428 429 /** Commit width, in instructions. */ 430 unsigned commitWidth; 431 432 /** Number of Reorder Buffers */ 433 unsigned numRobs; 434 435 /** Number of Active Threads */ 436 ThreadID numThreads; 437 438 /** Is a drain pending. */ 439 bool drainPending; 440 441 /** Is commit switched out. */ 442 bool switchedOut; 443 444 /** The latency to handle a trap. Used when scheduling trap 445 * squash event. 446 */ 447 Cycles trapLatency; 448 449 /** The interrupt fault. */ 450 Fault interrupt; 451 452 /** The commit PC state of each thread. Refers to the instruction that 453 * is currently being processed/committed. 454 */ 455 TheISA::PCState pc[Impl::MaxThreads]; 456 457 /** The sequence number of the youngest valid instruction in the ROB. */ 458 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 459 460 /** The sequence number of the last commited instruction. */ 461 InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 462 463 /** Records if there is a trap currently in flight. */ 464 bool trapInFlight[Impl::MaxThreads]; 465 466 /** Records if there were any stores committed this cycle. */ 467 bool committedStores[Impl::MaxThreads]; 468 469 /** Records if commit should check if the ROB is truly empty (see 470 commit_impl.hh). */ 471 bool checkEmptyROB[Impl::MaxThreads]; 472 473 /** Pointer to the list of active threads. */ 474 std::list<ThreadID> *activeThreads; 475 476 /** Rename map interface. */ 477 RenameMap *renameMap[Impl::MaxThreads]; 478 479 /** True if last committed microop can be followed by an interrupt */ 480 bool canHandleInterrupts; 481 482 /** Updates commit stats based on this instruction. */ 483 void updateComInstStats(DynInstPtr &inst); 484 485 /** Stat for the total number of squashed instructions discarded by commit. 486 */ 487 Stats::Scalar commitSquashedInsts; 488 /** Stat for the total number of times commit is told to squash. 489 * @todo: Actually increment this stat. 490 */ 491 Stats::Scalar commitSquashEvents; 492 /** Stat for the total number of times commit has had to stall due to a non- 493 * speculative instruction reaching the head of the ROB. 494 */ 495 Stats::Scalar commitNonSpecStalls; 496 /** Stat for the total number of branch mispredicts that caused a squash. */ 497 Stats::Scalar branchMispredicts; 498 /** Distribution of the number of committed instructions each cycle. */ 499 Stats::Distribution numCommittedDist; 500 501 /** Total number of instructions committed. */ 502 Stats::Vector instsCommitted; 503 /** Total number of ops (including micro ops) committed. */ 504 Stats::Vector opsCommitted; 505 /** Total number of software prefetches committed. */ 506 Stats::Vector statComSwp; 507 /** Stat for the total number of committed memory references. */ 508 Stats::Vector statComRefs; 509 /** Stat for the total number of committed loads. */ 510 Stats::Vector statComLoads; 511 /** Total number of committed memory barriers. */ 512 Stats::Vector statComMembars; 513 /** Total number of committed branches. */ 514 Stats::Vector statComBranches; 515 /** Total number of floating point instructions */ 516 Stats::Vector statComFloating; 517 /** Total number of integer instructions */ 518 Stats::Vector statComInteger; 519 /** Total number of function calls */ 520 Stats::Vector statComFunctionCalls; 521 522 /** Number of cycles where the commit bandwidth limit is reached. */ 523 Stats::Scalar commitEligibleSamples; 524 /** Number of instructions not committed due to bandwidth limits. */ 525 Stats::Vector commitEligible; 526}; 527 528#endif // __CPU_O3_COMMIT_HH__ 529