commit.hh revision 2874:5389a28b80fb
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_COMMIT_HH__ 33#define __CPU_O3_COMMIT_HH__ 34 35#include "arch/faults.hh" 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38#include "cpu/exetrace.hh" 39#include "cpu/inst_seq.hh" 40 41template <class> 42class O3ThreadState; 43 44/** 45 * DefaultCommit handles single threaded and SMT commit. Its width is 46 * specified by the parameters; each cycle it tries to commit that 47 * many instructions. The SMT policy decides which thread it tries to 48 * commit instructions from. Non- speculative instructions must reach 49 * the head of the ROB before they are ready to execute; once they 50 * reach the head, commit will broadcast the instruction's sequence 51 * number to the previous stages so that they can issue/ execute the 52 * instruction. Only one non-speculative instruction is handled per 53 * cycle. Commit is responsible for handling all back-end initiated 54 * redirects. It receives the redirect, and then broadcasts it to all 55 * stages, indicating the sequence number they should squash until, 56 * and any necessary branch misprediction information as well. It 57 * priortizes redirects by instruction's age, only broadcasting a 58 * redirect if it corresponds to an instruction that should currently 59 * be in the ROB. This is done by tracking the sequence number of the 60 * youngest instruction in the ROB, which gets updated to any 61 * squashing instruction's sequence number, and only broadcasting a 62 * redirect if it corresponds to an older instruction. Commit also 63 * supports multiple cycle squashing, to model a ROB that can only 64 * remove a certain number of instructions per cycle. 65 */ 66template<class Impl> 67class DefaultCommit 68{ 69 public: 70 // Typedefs from the Impl. 71 typedef typename Impl::O3CPU O3CPU; 72 typedef typename Impl::DynInstPtr DynInstPtr; 73 typedef typename Impl::Params Params; 74 typedef typename Impl::CPUPol CPUPol; 75 76 typedef typename CPUPol::RenameMap RenameMap; 77 typedef typename CPUPol::ROB ROB; 78 79 typedef typename CPUPol::TimeStruct TimeStruct; 80 typedef typename CPUPol::FetchStruct FetchStruct; 81 typedef typename CPUPol::IEWStruct IEWStruct; 82 typedef typename CPUPol::RenameStruct RenameStruct; 83 84 typedef typename CPUPol::Fetch Fetch; 85 typedef typename CPUPol::IEW IEW; 86 87 typedef O3ThreadState<Impl> Thread; 88 89 /** Event class used to schedule a squash due to a trap (fault or 90 * interrupt) to happen on a specific cycle. 91 */ 92 class TrapEvent : public Event { 93 private: 94 DefaultCommit<Impl> *commit; 95 unsigned tid; 96 97 public: 98 TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid); 99 100 void process(); 101 const char *description(); 102 }; 103 104 /** Overall commit status. Used to determine if the CPU can deschedule 105 * itself due to a lack of activity. 106 */ 107 enum CommitStatus{ 108 Active, 109 Inactive 110 }; 111 112 /** Individual thread status. */ 113 enum ThreadStatus { 114 Running, 115 Idle, 116 ROBSquashing, 117 TrapPending, 118 FetchTrapPending 119 }; 120 121 /** Commit policy for SMT mode. */ 122 enum CommitPolicy { 123 Aggressive, 124 RoundRobin, 125 OldestReady 126 }; 127 128 private: 129 /** Overall commit status. */ 130 CommitStatus _status; 131 /** Next commit status, to be set at the end of the cycle. */ 132 CommitStatus _nextStatus; 133 /** Per-thread status. */ 134 ThreadStatus commitStatus[Impl::MaxThreads]; 135 /** Commit policy used in SMT mode. */ 136 CommitPolicy commitPolicy; 137 138 public: 139 /** Construct a DefaultCommit with the given parameters. */ 140 DefaultCommit(Params *params); 141 142 /** Returns the name of the DefaultCommit. */ 143 std::string name() const; 144 145 /** Registers statistics. */ 146 void regStats(); 147 148 /** Sets the CPU pointer. */ 149 void setCPU(O3CPU *cpu_ptr); 150 151 /** Sets the list of threads. */ 152 void setThreads(std::vector<Thread *> &threads); 153 154 /** Sets the main time buffer pointer, used for backwards communication. */ 155 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 156 157 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 158 159 /** Sets the pointer to the queue coming from rename. */ 160 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 161 162 /** Sets the pointer to the queue coming from IEW. */ 163 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 164 165 /** Sets the pointer to the IEW stage. */ 166 void setIEWStage(IEW *iew_stage); 167 168 /** The pointer to the IEW stage. Used solely to ensure that 169 * various events (traps, interrupts, syscalls) do not occur until 170 * all stores have written back. 171 */ 172 IEW *iewStage; 173 174 /** Sets pointer to list of active threads. */ 175 void setActiveThreads(std::list<unsigned> *at_ptr); 176 177 /** Sets pointer to the commited state rename map. */ 178 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 179 180 /** Sets pointer to the ROB. */ 181 void setROB(ROB *rob_ptr); 182 183 /** Initializes stage by sending back the number of free entries. */ 184 void initStage(); 185 186 /** Initializes the draining of commit. */ 187 bool drain(); 188 189 /** Resumes execution after draining. */ 190 void resume(); 191 192 /** Completes the switch out of commit. */ 193 void switchOut(); 194 195 /** Takes over from another CPU's thread. */ 196 void takeOverFrom(); 197 198 /** Ticks the commit stage, which tries to commit instructions. */ 199 void tick(); 200 201 /** Handles any squashes that are sent from IEW, and adds instructions 202 * to the ROB and tries to commit instructions. 203 */ 204 void commit(); 205 206 /** Returns the number of free ROB entries for a specific thread. */ 207 unsigned numROBFreeEntries(unsigned tid); 208 209 /** Generates an event to schedule a squash due to a trap. */ 210 void generateTrapEvent(unsigned tid); 211 212 /** Records that commit needs to initiate a squash due to an 213 * external state update through the TC. 214 */ 215 void generateTCEvent(unsigned tid); 216 217 private: 218 /** Updates the overall status of commit with the nextStatus, and 219 * tell the CPU if commit is active/inactive. 220 */ 221 void updateStatus(); 222 223 /** Sets the next status based on threads' statuses, which becomes the 224 * current status at the end of the cycle. 225 */ 226 void setNextStatus(); 227 228 /** Checks if the ROB is completed with squashing. This is for the case 229 * where the ROB can take multiple cycles to complete squashing. 230 */ 231 bool robDoneSquashing(); 232 233 /** Returns if any of the threads have the number of ROB entries changed 234 * on this cycle. Used to determine if the number of free ROB entries needs 235 * to be sent back to previous stages. 236 */ 237 bool changedROBEntries(); 238 239 /** Squashes all in flight instructions. */ 240 void squashAll(unsigned tid); 241 242 /** Handles squashing due to a trap. */ 243 void squashFromTrap(unsigned tid); 244 245 /** Handles squashing due to an TC write. */ 246 void squashFromTC(unsigned tid); 247 248 /** Commits as many instructions as possible. */ 249 void commitInsts(); 250 251 /** Tries to commit the head ROB instruction passed in. 252 * @param head_inst The instruction to be committed. 253 */ 254 bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 255 256 /** Gets instructions from rename and inserts them into the ROB. */ 257 void getInsts(); 258 259 /** Marks completed instructions using information sent from IEW. */ 260 void markCompletedInsts(); 261 262 /** Gets the thread to commit, based on the SMT policy. */ 263 int getCommittingThread(); 264 265 /** Returns the thread ID to use based on a round robin policy. */ 266 int roundRobin(); 267 268 /** Returns the thread ID to use based on an oldest instruction policy. */ 269 int oldestReady(); 270 271 public: 272 /** Returns the PC of the head instruction of the ROB. 273 * @todo: Probably remove this function as it returns only thread 0. 274 */ 275 uint64_t readPC() { return PC[0]; } 276 277 /** Returns the PC of a specific thread. */ 278 uint64_t readPC(unsigned tid) { return PC[tid]; } 279 280 /** Sets the PC of a specific thread. */ 281 void setPC(uint64_t val, unsigned tid) { PC[tid] = val; } 282 283 /** Reads the next PC of a specific thread. */ 284 uint64_t readNextPC(unsigned tid) { return nextPC[tid]; } 285 286 /** Sets the next PC of a specific thread. */ 287 void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; } 288 289#if THE_ISA != ALPHA_ISA 290 /** Reads the next NPC of a specific thread. */ 291 uint64_t readNextPC(unsigned tid) { return nextNPC[tid]; } 292 293 /** Sets the next NPC of a specific thread. */ 294 void setNextPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; } 295#endif 296 297 private: 298 /** Time buffer interface. */ 299 TimeBuffer<TimeStruct> *timeBuffer; 300 301 /** Wire to write information heading to previous stages. */ 302 typename TimeBuffer<TimeStruct>::wire toIEW; 303 304 /** Wire to read information from IEW (for ROB). */ 305 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 306 307 TimeBuffer<FetchStruct> *fetchQueue; 308 309 typename TimeBuffer<FetchStruct>::wire fromFetch; 310 311 /** IEW instruction queue interface. */ 312 TimeBuffer<IEWStruct> *iewQueue; 313 314 /** Wire to read information from IEW queue. */ 315 typename TimeBuffer<IEWStruct>::wire fromIEW; 316 317 /** Rename instruction queue interface, for ROB. */ 318 TimeBuffer<RenameStruct> *renameQueue; 319 320 /** Wire to read information from rename queue. */ 321 typename TimeBuffer<RenameStruct>::wire fromRename; 322 323 public: 324 /** ROB interface. */ 325 ROB *rob; 326 327 private: 328 /** Pointer to O3CPU. */ 329 O3CPU *cpu; 330 331 /** Vector of all of the threads. */ 332 std::vector<Thread *> thread; 333 334 /** Records that commit has written to the time buffer this cycle. Used for 335 * the CPU to determine if it can deschedule itself if there is no activity. 336 */ 337 bool wroteToTimeBuffer; 338 339 /** Records if the number of ROB entries has changed this cycle. If it has, 340 * then the number of free entries must be re-broadcast. 341 */ 342 bool changedROBNumEntries[Impl::MaxThreads]; 343 344 /** A counter of how many threads are currently squashing. */ 345 int squashCounter; 346 347 /** Records if a thread has to squash this cycle due to a trap. */ 348 bool trapSquash[Impl::MaxThreads]; 349 350 /** Records if a thread has to squash this cycle due to an XC write. */ 351 bool tcSquash[Impl::MaxThreads]; 352 353 /** Priority List used for Commit Policy */ 354 std::list<unsigned> priority_list; 355 356 /** IEW to Commit delay, in ticks. */ 357 unsigned iewToCommitDelay; 358 359 /** Commit to IEW delay, in ticks. */ 360 unsigned commitToIEWDelay; 361 362 /** Rename to ROB delay, in ticks. */ 363 unsigned renameToROBDelay; 364 365 unsigned fetchToCommitDelay; 366 367 /** Rename width, in instructions. Used so ROB knows how many 368 * instructions to get from the rename instruction queue. 369 */ 370 unsigned renameWidth; 371 372 /** Commit width, in instructions. */ 373 unsigned commitWidth; 374 375 /** Number of Reorder Buffers */ 376 unsigned numRobs; 377 378 /** Number of Active Threads */ 379 unsigned numThreads; 380 381 /** Is a drain pending. */ 382 bool drainPending; 383 384 /** Is commit switched out. */ 385 bool switchedOut; 386 387 /** The latency to handle a trap. Used when scheduling trap 388 * squash event. 389 */ 390 Tick trapLatency; 391 392 /** The commit PC of each thread. Refers to the instruction that 393 * is currently being processed/committed. 394 */ 395 Addr PC[Impl::MaxThreads]; 396 397 /** The next PC of each thread. */ 398 Addr nextPC[Impl::MaxThreads]; 399 400#if THE_ISA != ALPHA_ISA 401 /** The next NPC of each thread. */ 402 Addr nextNPC[Impl::MaxThreads]; 403#endif 404 405 /** The sequence number of the youngest valid instruction in the ROB. */ 406 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 407 408 /** Pointer to the list of active threads. */ 409 std::list<unsigned> *activeThreads; 410 411 /** Rename map interface. */ 412 RenameMap *renameMap[Impl::MaxThreads]; 413 414 /** Updates commit stats based on this instruction. */ 415 void updateComInstStats(DynInstPtr &inst); 416 417 /** Stat for the total number of committed instructions. */ 418 Stats::Scalar<> commitCommittedInsts; 419 /** Stat for the total number of squashed instructions discarded by commit. 420 */ 421 Stats::Scalar<> commitSquashedInsts; 422 /** Stat for the total number of times commit is told to squash. 423 * @todo: Actually increment this stat. 424 */ 425 Stats::Scalar<> commitSquashEvents; 426 /** Stat for the total number of times commit has had to stall due to a non- 427 * speculative instruction reaching the head of the ROB. 428 */ 429 Stats::Scalar<> commitNonSpecStalls; 430 /** Stat for the total number of branch mispredicts that caused a squash. */ 431 Stats::Scalar<> branchMispredicts; 432 /** Distribution of the number of committed instructions each cycle. */ 433 Stats::Distribution<> numCommittedDist; 434 435 /** Total number of instructions committed. */ 436 Stats::Vector<> statComInst; 437 /** Total number of software prefetches committed. */ 438 Stats::Vector<> statComSwp; 439 /** Stat for the total number of committed memory references. */ 440 Stats::Vector<> statComRefs; 441 /** Stat for the total number of committed loads. */ 442 Stats::Vector<> statComLoads; 443 /** Total number of committed memory barriers. */ 444 Stats::Vector<> statComMembars; 445 /** Total number of committed branches. */ 446 Stats::Vector<> statComBranches; 447 448 /** Number of cycles where the commit bandwidth limit is reached. */ 449 Stats::Scalar<> commitEligibleSamples; 450 /** Number of instructions not committed due to bandwidth limits. */ 451 Stats::Vector<> commitEligible; 452}; 453 454#endif // __CPU_O3_COMMIT_HH__ 455