commit.hh revision 10193:d717abc806aa
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#ifndef __CPU_O3_COMMIT_HH__ 45#define __CPU_O3_COMMIT_HH__ 46 47#include <queue> 48 49#include "base/statistics.hh" 50#include "cpu/exetrace.hh" 51#include "cpu/inst_seq.hh" 52#include "cpu/timebuf.hh" 53#include "sim/probe/probe.hh" 54 55struct DerivO3CPUParams; 56 57template <class> 58struct O3ThreadState; 59 60/** 61 * DefaultCommit handles single threaded and SMT commit. Its width is 62 * specified by the parameters; each cycle it tries to commit that 63 * many instructions. The SMT policy decides which thread it tries to 64 * commit instructions from. Non- speculative instructions must reach 65 * the head of the ROB before they are ready to execute; once they 66 * reach the head, commit will broadcast the instruction's sequence 67 * number to the previous stages so that they can issue/ execute the 68 * instruction. Only one non-speculative instruction is handled per 69 * cycle. Commit is responsible for handling all back-end initiated 70 * redirects. It receives the redirect, and then broadcasts it to all 71 * stages, indicating the sequence number they should squash until, 72 * and any necessary branch misprediction information as well. It 73 * priortizes redirects by instruction's age, only broadcasting a 74 * redirect if it corresponds to an instruction that should currently 75 * be in the ROB. This is done by tracking the sequence number of the 76 * youngest instruction in the ROB, which gets updated to any 77 * squashing instruction's sequence number, and only broadcasting a 78 * redirect if it corresponds to an older instruction. Commit also 79 * supports multiple cycle squashing, to model a ROB that can only 80 * remove a certain number of instructions per cycle. 81 */ 82template<class Impl> 83class DefaultCommit 84{ 85 public: 86 // Typedefs from the Impl. 87 typedef typename Impl::O3CPU O3CPU; 88 typedef typename Impl::DynInstPtr DynInstPtr; 89 typedef typename Impl::CPUPol CPUPol; 90 91 typedef typename CPUPol::RenameMap RenameMap; 92 typedef typename CPUPol::ROB ROB; 93 94 typedef typename CPUPol::TimeStruct TimeStruct; 95 typedef typename CPUPol::FetchStruct FetchStruct; 96 typedef typename CPUPol::IEWStruct IEWStruct; 97 typedef typename CPUPol::RenameStruct RenameStruct; 98 99 typedef typename CPUPol::Fetch Fetch; 100 typedef typename CPUPol::IEW IEW; 101 102 typedef O3ThreadState<Impl> Thread; 103 104 /** Event class used to schedule a squash due to a trap (fault or 105 * interrupt) to happen on a specific cycle. 106 */ 107 class TrapEvent : public Event { 108 private: 109 DefaultCommit<Impl> *commit; 110 ThreadID tid; 111 112 public: 113 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 114 115 void process(); 116 const char *description() const; 117 }; 118 119 /** Overall commit status. Used to determine if the CPU can deschedule 120 * itself due to a lack of activity. 121 */ 122 enum CommitStatus{ 123 Active, 124 Inactive 125 }; 126 127 /** Individual thread status. */ 128 enum ThreadStatus { 129 Running, 130 Idle, 131 ROBSquashing, 132 TrapPending, 133 FetchTrapPending, 134 SquashAfterPending, //< Committing instructions before a squash. 135 }; 136 137 /** Commit policy for SMT mode. */ 138 enum CommitPolicy { 139 Aggressive, 140 RoundRobin, 141 OldestReady 142 }; 143 144 private: 145 /** Overall commit status. */ 146 CommitStatus _status; 147 /** Next commit status, to be set at the end of the cycle. */ 148 CommitStatus _nextStatus; 149 /** Per-thread status. */ 150 ThreadStatus commitStatus[Impl::MaxThreads]; 151 /** Commit policy used in SMT mode. */ 152 CommitPolicy commitPolicy; 153 154 /** Probe Points. */ 155 ProbePointArg<DynInstPtr> *ppCommit; 156 ProbePointArg<DynInstPtr> *ppCommitStall; 157 158 public: 159 /** Construct a DefaultCommit with the given parameters. */ 160 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 161 162 /** Returns the name of the DefaultCommit. */ 163 std::string name() const; 164 165 /** Registers statistics. */ 166 void regStats(); 167 168 /** Registers probes. */ 169 void regProbePoints(); 170 171 /** Sets the list of threads. */ 172 void setThreads(std::vector<Thread *> &threads); 173 174 /** Sets the main time buffer pointer, used for backwards communication. */ 175 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 176 177 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 178 179 /** Sets the pointer to the queue coming from rename. */ 180 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 181 182 /** Sets the pointer to the queue coming from IEW. */ 183 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 184 185 /** Sets the pointer to the IEW stage. */ 186 void setIEWStage(IEW *iew_stage); 187 188 /** Skid buffer between rename and commit. */ 189 std::queue<DynInstPtr> skidBuffer; 190 191 /** The pointer to the IEW stage. Used solely to ensure that 192 * various events (traps, interrupts, syscalls) do not occur until 193 * all stores have written back. 194 */ 195 IEW *iewStage; 196 197 /** Sets pointer to list of active threads. */ 198 void setActiveThreads(std::list<ThreadID> *at_ptr); 199 200 /** Sets pointer to the commited state rename map. */ 201 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 202 203 /** Sets pointer to the ROB. */ 204 void setROB(ROB *rob_ptr); 205 206 /** Initializes stage by sending back the number of free entries. */ 207 void startupStage(); 208 209 /** Initializes the draining of commit. */ 210 void drain(); 211 212 /** Resumes execution after draining. */ 213 void drainResume(); 214 215 /** Perform sanity checks after a drain. */ 216 void drainSanityCheck() const; 217 218 /** Has the stage drained? */ 219 bool isDrained() const; 220 221 /** Takes over from another CPU's thread. */ 222 void takeOverFrom(); 223 224 /** Ticks the commit stage, which tries to commit instructions. */ 225 void tick(); 226 227 /** Handles any squashes that are sent from IEW, and adds instructions 228 * to the ROB and tries to commit instructions. 229 */ 230 void commit(); 231 232 /** Returns the number of free ROB entries for a specific thread. */ 233 size_t numROBFreeEntries(ThreadID tid); 234 235 /** Generates an event to schedule a squash due to a trap. */ 236 void generateTrapEvent(ThreadID tid); 237 238 /** Records that commit needs to initiate a squash due to an 239 * external state update through the TC. 240 */ 241 void generateTCEvent(ThreadID tid); 242 243 private: 244 /** Updates the overall status of commit with the nextStatus, and 245 * tell the CPU if commit is active/inactive. 246 */ 247 void updateStatus(); 248 249 /** Sets the next status based on threads' statuses, which becomes the 250 * current status at the end of the cycle. 251 */ 252 void setNextStatus(); 253 254 /** Checks if the ROB is completed with squashing. This is for the case 255 * where the ROB can take multiple cycles to complete squashing. 256 */ 257 bool robDoneSquashing(); 258 259 /** Returns if any of the threads have the number of ROB entries changed 260 * on this cycle. Used to determine if the number of free ROB entries needs 261 * to be sent back to previous stages. 262 */ 263 bool changedROBEntries(); 264 265 /** Squashes all in flight instructions. */ 266 void squashAll(ThreadID tid); 267 268 /** Handles squashing due to a trap. */ 269 void squashFromTrap(ThreadID tid); 270 271 /** Handles squashing due to an TC write. */ 272 void squashFromTC(ThreadID tid); 273 274 /** Handles a squash from a squashAfter() request. */ 275 void squashFromSquashAfter(ThreadID tid); 276 277 /** 278 * Handle squashing from instruction with SquashAfter set. 279 * 280 * This differs from the other squashes as it squashes following 281 * instructions instead of the current instruction and doesn't 282 * clean up various status bits about traps/tc writes 283 * pending. Since there might have been instructions committed by 284 * the commit stage before the squashing instruction was reached 285 * and we can't commit and squash in the same cycle, we have to 286 * squash in two steps: 287 * 288 * <ol> 289 * <li>Immediately set the commit status of the thread of 290 * SquashAfterPending. This forces the thread to stop 291 * committing instructions in this cycle. The last 292 * instruction to be committed in this cycle will be the 293 * SquashAfter instruction. 294 * <li>In the next cycle, commit() checks for the 295 * SquashAfterPending state and squashes <i>all</i> 296 * in-flight instructions. Since the SquashAfter instruction 297 * was the last instruction to be committed in the previous 298 * cycle, this causes all subsequent instructions to be 299 * squashed. 300 * </ol> 301 * 302 * @param tid ID of the thread to squash. 303 * @param head_inst Instruction that requested the squash. 304 */ 305 void squashAfter(ThreadID tid, DynInstPtr &head_inst); 306 307 /** Handles processing an interrupt. */ 308 void handleInterrupt(); 309 310 /** Get fetch redirecting so we can handle an interrupt */ 311 void propagateInterrupt(); 312 313 /** Commits as many instructions as possible. */ 314 void commitInsts(); 315 316 /** Tries to commit the head ROB instruction passed in. 317 * @param head_inst The instruction to be committed. 318 */ 319 bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 320 321 /** Gets instructions from rename and inserts them into the ROB. */ 322 void getInsts(); 323 324 /** Insert all instructions from rename into skidBuffer */ 325 void skidInsert(); 326 327 /** Marks completed instructions using information sent from IEW. */ 328 void markCompletedInsts(); 329 330 /** Gets the thread to commit, based on the SMT policy. */ 331 ThreadID getCommittingThread(); 332 333 /** Returns the thread ID to use based on a round robin policy. */ 334 ThreadID roundRobin(); 335 336 /** Returns the thread ID to use based on an oldest instruction policy. */ 337 ThreadID oldestReady(); 338 339 public: 340 /** Reads the PC of a specific thread. */ 341 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 342 343 /** Sets the PC of a specific thread. */ 344 void pcState(const TheISA::PCState &val, ThreadID tid) 345 { pc[tid] = val; } 346 347 /** Returns the PC of a specific thread. */ 348 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 349 350 /** Returns the next PC of a specific thread. */ 351 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 352 353 /** Reads the micro PC of a specific thread. */ 354 Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 355 356 private: 357 /** Time buffer interface. */ 358 TimeBuffer<TimeStruct> *timeBuffer; 359 360 /** Wire to write information heading to previous stages. */ 361 typename TimeBuffer<TimeStruct>::wire toIEW; 362 363 /** Wire to read information from IEW (for ROB). */ 364 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 365 366 TimeBuffer<FetchStruct> *fetchQueue; 367 368 typename TimeBuffer<FetchStruct>::wire fromFetch; 369 370 /** IEW instruction queue interface. */ 371 TimeBuffer<IEWStruct> *iewQueue; 372 373 /** Wire to read information from IEW queue. */ 374 typename TimeBuffer<IEWStruct>::wire fromIEW; 375 376 /** Rename instruction queue interface, for ROB. */ 377 TimeBuffer<RenameStruct> *renameQueue; 378 379 /** Wire to read information from rename queue. */ 380 typename TimeBuffer<RenameStruct>::wire fromRename; 381 382 public: 383 /** ROB interface. */ 384 ROB *rob; 385 386 private: 387 /** Pointer to O3CPU. */ 388 O3CPU *cpu; 389 390 /** Vector of all of the threads. */ 391 std::vector<Thread *> thread; 392 393 /** Records that commit has written to the time buffer this cycle. Used for 394 * the CPU to determine if it can deschedule itself if there is no activity. 395 */ 396 bool wroteToTimeBuffer; 397 398 /** Records if the number of ROB entries has changed this cycle. If it has, 399 * then the number of free entries must be re-broadcast. 400 */ 401 bool changedROBNumEntries[Impl::MaxThreads]; 402 403 /** A counter of how many threads are currently squashing. */ 404 ThreadID squashCounter; 405 406 /** Records if a thread has to squash this cycle due to a trap. */ 407 bool trapSquash[Impl::MaxThreads]; 408 409 /** Records if a thread has to squash this cycle due to an XC write. */ 410 bool tcSquash[Impl::MaxThreads]; 411 412 /** 413 * Instruction passed to squashAfter(). 414 * 415 * The squash after implementation needs to buffer the instruction 416 * that caused a squash since this needs to be passed to the fetch 417 * stage once squashing starts. 418 */ 419 DynInstPtr squashAfterInst[Impl::MaxThreads]; 420 421 /** Priority List used for Commit Policy */ 422 std::list<ThreadID> priority_list; 423 424 /** IEW to Commit delay. */ 425 Cycles iewToCommitDelay; 426 427 /** Commit to IEW delay. */ 428 Cycles commitToIEWDelay; 429 430 /** Rename to ROB delay. */ 431 Cycles renameToROBDelay; 432 433 Cycles fetchToCommitDelay; 434 435 /** Rename width, in instructions. Used so ROB knows how many 436 * instructions to get from the rename instruction queue. 437 */ 438 unsigned renameWidth; 439 440 /** Commit width, in instructions. */ 441 unsigned commitWidth; 442 443 /** Number of Reorder Buffers */ 444 unsigned numRobs; 445 446 /** Number of Active Threads */ 447 ThreadID numThreads; 448 449 /** Is a drain pending. */ 450 bool drainPending; 451 452 /** The latency to handle a trap. Used when scheduling trap 453 * squash event. 454 */ 455 Cycles trapLatency; 456 457 /** The interrupt fault. */ 458 Fault interrupt; 459 460 /** The commit PC state of each thread. Refers to the instruction that 461 * is currently being processed/committed. 462 */ 463 TheISA::PCState pc[Impl::MaxThreads]; 464 465 /** The sequence number of the youngest valid instruction in the ROB. */ 466 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 467 468 /** The sequence number of the last commited instruction. */ 469 InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 470 471 /** Records if there is a trap currently in flight. */ 472 bool trapInFlight[Impl::MaxThreads]; 473 474 /** Records if there were any stores committed this cycle. */ 475 bool committedStores[Impl::MaxThreads]; 476 477 /** Records if commit should check if the ROB is truly empty (see 478 commit_impl.hh). */ 479 bool checkEmptyROB[Impl::MaxThreads]; 480 481 /** Pointer to the list of active threads. */ 482 std::list<ThreadID> *activeThreads; 483 484 /** Rename map interface. */ 485 RenameMap *renameMap[Impl::MaxThreads]; 486 487 /** True if last committed microop can be followed by an interrupt */ 488 bool canHandleInterrupts; 489 490 /** Have we had an interrupt pending and then seen it de-asserted because 491 of a masking change? In this case the variable is set and the next time 492 interrupts are enabled and pending the pipeline will squash to avoid 493 a possible livelock senario. */ 494 bool avoidQuiesceLiveLock; 495 496 /** Updates commit stats based on this instruction. */ 497 void updateComInstStats(DynInstPtr &inst); 498 499 /** Stat for the total number of squashed instructions discarded by commit. 500 */ 501 Stats::Scalar commitSquashedInsts; 502 /** Stat for the total number of times commit is told to squash. 503 * @todo: Actually increment this stat. 504 */ 505 Stats::Scalar commitSquashEvents; 506 /** Stat for the total number of times commit has had to stall due to a non- 507 * speculative instruction reaching the head of the ROB. 508 */ 509 Stats::Scalar commitNonSpecStalls; 510 /** Stat for the total number of branch mispredicts that caused a squash. */ 511 Stats::Scalar branchMispredicts; 512 /** Distribution of the number of committed instructions each cycle. */ 513 Stats::Distribution numCommittedDist; 514 515 /** Total number of instructions committed. */ 516 Stats::Vector instsCommitted; 517 /** Total number of ops (including micro ops) committed. */ 518 Stats::Vector opsCommitted; 519 /** Total number of software prefetches committed. */ 520 Stats::Vector statComSwp; 521 /** Stat for the total number of committed memory references. */ 522 Stats::Vector statComRefs; 523 /** Stat for the total number of committed loads. */ 524 Stats::Vector statComLoads; 525 /** Total number of committed memory barriers. */ 526 Stats::Vector statComMembars; 527 /** Total number of committed branches. */ 528 Stats::Vector statComBranches; 529 /** Total number of floating point instructions */ 530 Stats::Vector statComFloating; 531 /** Total number of integer instructions */ 532 Stats::Vector statComInteger; 533 /** Total number of function calls */ 534 Stats::Vector statComFunctionCalls; 535 /** Committed instructions by instruction type (OpClass) */ 536 Stats::Vector2d statCommittedInstType; 537 538 /** Number of cycles where the commit bandwidth limit is reached. */ 539 Stats::Scalar commitEligibleSamples; 540 /** Number of instructions not committed due to bandwidth limits. */ 541 Stats::Vector commitEligible; 542}; 543 544#endif // __CPU_O3_COMMIT_HH__ 545