checker.cc revision 9384
12350SN/A/* 28733SN/A * Copyright (c) 2011 ARM Limited 38733SN/A * All rights reserved 48733SN/A * 58733SN/A * The license below extends only to copyright in the software and shall 68733SN/A * not be construed as granting a license to any other intellectual 78733SN/A * property including but not limited to intellectual property relating 88733SN/A * to a hardware implementation of the functionality of the software 98733SN/A * licensed hereunder. You may use the software subject to the license 108733SN/A * terms below provided that you ensure that this notice is replicated 118733SN/A * unmodified and in its entirety in all distributions of the software, 128733SN/A * modified or unmodified, in source code or in binary form. 138733SN/A * 142350SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152350SN/A * All rights reserved. 162350SN/A * 172350SN/A * Redistribution and use in source and binary forms, with or without 182350SN/A * modification, are permitted provided that the following conditions are 192350SN/A * met: redistributions of source code must retain the above copyright 202350SN/A * notice, this list of conditions and the following disclaimer; 212350SN/A * redistributions in binary form must reproduce the above copyright 222350SN/A * notice, this list of conditions and the following disclaimer in the 232350SN/A * documentation and/or other materials provided with the distribution; 242350SN/A * neither the name of the copyright holders nor the names of its 252350SN/A * contributors may be used to endorse or promote products derived from 262350SN/A * this software without specific prior written permission. 272350SN/A * 282350SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292350SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302350SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312350SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322350SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332350SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342350SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352350SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362350SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372350SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382350SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689SN/A * 402689SN/A * Authors: Kevin Lim 412350SN/A */ 422315SN/A 432765SN/A#include "cpu/checker/cpu_impl.hh" 449340SAndreas.Sandberg@arm.com#include "cpu/o3/checker.hh" 454762SN/A#include "params/O3Checker.hh" 462315SN/A 472669SN/Aclass MemObject; 482669SN/A 492765SN/Atemplate 508733SN/Aclass Checker<O3CPUImpl>; 512765SN/A 522315SN/A//////////////////////////////////////////////////////////////////////// 532315SN/A// 542315SN/A// CheckerCPU Simulation Object 552315SN/A// 564762SN/AO3Checker * 574762SN/AO3CheckerParams::create() 582315SN/A{ 592315SN/A O3Checker::Params *params = new O3Checker::Params(); 604762SN/A params->name = name; 618733SN/A params->numThreads = numThreads; 622315SN/A params->max_insts_any_thread = 0; 632315SN/A params->max_insts_all_threads = 0; 642315SN/A params->max_loads_any_thread = 0; 652315SN/A params->max_loads_all_threads = 0; 662315SN/A params->exitOnError = exitOnError; 672356SN/A params->updateOnError = updateOnError; 682732SN/A params->warnOnlyOnLoadError = warnOnlyOnLoadError; 692315SN/A params->clock = clock; 708733SN/A params->tracer = tracer; 712315SN/A // Hack to touch all parameters. Consider not deriving Checker 722315SN/A // from BaseCPU..it's not really a CPU in the end. 732315SN/A Counter temp; 742315SN/A temp = max_insts_any_thread; 752315SN/A temp = max_insts_all_threads; 762315SN/A temp = max_loads_any_thread; 772315SN/A temp = max_loads_all_threads; 788887SN/A temp++; 792356SN/A Tick temp2 = progress_interval; 802367SN/A params->progress_interval = 0; 812356SN/A temp2++; 822315SN/A 832315SN/A params->itb = itb; 842315SN/A params->dtb = dtb; 859384SAndreas.Sandberg@arm.com params->isa = isa; 865104SN/A params->system = system; 875110SN/A params->cpu_id = cpu_id; 882315SN/A params->profile = profile; 898733SN/A params->interrupts = NULL; 908733SN/A params->workload = workload; 912315SN/A 922315SN/A O3Checker *cpu = new O3Checker(params); 932315SN/A return cpu; 942315SN/A} 95