checker.cc revision 4762 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <string>
32
33#include "cpu/checker/cpu_impl.hh"
34#include "cpu/inst_seq.hh"
35#include "cpu/o3/alpha/dyn_inst.hh"
36#include "cpu/o3/alpha/impl.hh"
37#include "params/O3Checker.hh"
38#include "sim/process.hh"
39#include "sim/sim_object.hh"
40
41class MemObject;
42
43template
44class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
45
46/**
47 * Specific non-templated derived class used for SimObject configuration.
48 */
49class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
50{
51  public:
52    O3Checker(Params *p)
53        : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
54    { }
55};
56
57////////////////////////////////////////////////////////////////////////
58//
59//  CheckerCPU Simulation Object
60//
61O3Checker *
62O3CheckerParams::create()
63{
64    O3Checker::Params *params = new O3Checker::Params();
65    params->name = name;
66    params->numberOfThreads = 1;
67    params->max_insts_any_thread = 0;
68    params->max_insts_all_threads = 0;
69    params->max_loads_any_thread = 0;
70    params->max_loads_all_threads = 0;
71    params->exitOnError = exitOnError;
72    params->updateOnError = updateOnError;
73    params->warnOnlyOnLoadError = warnOnlyOnLoadError;
74    params->deferRegistration = defer_registration;
75    params->functionTrace = function_trace;
76    params->functionTraceStart = function_trace_start;
77    params->clock = clock;
78    // Hack to touch all parameters.  Consider not deriving Checker
79    // from BaseCPU..it's not really a CPU in the end.
80    Counter temp;
81    temp = max_insts_any_thread;
82    temp = max_insts_all_threads;
83    temp = max_loads_any_thread;
84    temp = max_loads_all_threads;
85    Tick temp2 = progress_interval;
86    params->progress_interval = 0;
87    temp2++;
88
89#if FULL_SYSTEM
90    params->itb = itb;
91    params->dtb = dtb;
92    params->system = system;
93    params->cpu_id = cpu_id;
94    params->profile = profile;
95#else
96    params->process = workload;
97#endif
98
99    O3Checker *cpu = new O3Checker(params);
100    return cpu;
101}
102