checker.cc revision 2367
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <string> 30 31#include "cpu/checker/cpu.hh" 32#include "cpu/inst_seq.hh" 33#include "cpu/o3/alpha_dyn_inst.hh" 34#include "cpu/o3/alpha_impl.hh" 35#include "mem/base_mem.hh" 36#include "sim/builder.hh" 37#include "sim/process.hh" 38#include "sim/sim_object.hh" 39 40/** 41 * Specific non-templated derived class used for SimObject configuration. 42 */ 43class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > > 44{ 45 public: 46 O3Checker(Params *p) 47 : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p) 48 { } 49}; 50 51//////////////////////////////////////////////////////////////////////// 52// 53// CheckerCPU Simulation Object 54// 55BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) 56 57 Param<Counter> max_insts_any_thread; 58 Param<Counter> max_insts_all_threads; 59 Param<Counter> max_loads_any_thread; 60 Param<Counter> max_loads_all_threads; 61 Param<Counter> stats_reset_inst; 62 Param<Tick> progress_interval; 63 64#if FULL_SYSTEM 65 SimObjectParam<AlphaITB *> itb; 66 SimObjectParam<AlphaDTB *> dtb; 67 SimObjectParam<FunctionalMemory *> mem; 68 SimObjectParam<System *> system; 69 Param<int> cpu_id; 70 Param<Tick> profile; 71#else 72 SimObjectParam<Process *> workload; 73#endif // FULL_SYSTEM 74 Param<int> clock; 75 SimObjectParam<BaseMem *> icache; 76 SimObjectParam<BaseMem *> dcache; 77 78 Param<bool> defer_registration; 79 Param<bool> exitOnError; 80 Param<bool> updateOnError; 81 Param<bool> function_trace; 82 Param<Tick> function_trace_start; 83 84END_DECLARE_SIM_OBJECT_PARAMS(O3Checker) 85 86BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) 87 88 INIT_PARAM(max_insts_any_thread, 89 "terminate when any thread reaches this inst count"), 90 INIT_PARAM(max_insts_all_threads, 91 "terminate when all threads have reached this inst count"), 92 INIT_PARAM(max_loads_any_thread, 93 "terminate when any thread reaches this load count"), 94 INIT_PARAM(max_loads_all_threads, 95 "terminate when all threads have reached this load count"), 96 INIT_PARAM(stats_reset_inst, 97 "blah"), 98 INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), 99 100#if FULL_SYSTEM 101 INIT_PARAM(itb, "Instruction TLB"), 102 INIT_PARAM(dtb, "Data TLB"), 103 INIT_PARAM(mem, "memory"), 104 INIT_PARAM(system, "system object"), 105 INIT_PARAM(cpu_id, "processor ID"), 106 INIT_PARAM(profile, ""), 107#else 108 INIT_PARAM(workload, "processes to run"), 109#endif // FULL_SYSTEM 110 111 INIT_PARAM(clock, "clock speed"), 112 INIT_PARAM(icache, "L1 instruction cache object"), 113 INIT_PARAM(dcache, "L1 data cache object"), 114 115 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 116 INIT_PARAM(exitOnError, "exit on error"), 117 INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"), 118 INIT_PARAM(function_trace, "Enable function trace"), 119 INIT_PARAM(function_trace_start, "Cycle to start function trace") 120 121END_INIT_SIM_OBJECT_PARAMS(O3Checker) 122 123 124CREATE_SIM_OBJECT(O3Checker) 125{ 126 O3Checker::Params *params = new O3Checker::Params(); 127 params->name = getInstanceName(); 128 params->numberOfThreads = 1; 129 params->max_insts_any_thread = 0; 130 params->max_insts_all_threads = 0; 131 params->max_loads_any_thread = 0; 132 params->max_loads_all_threads = 0; 133 params->stats_reset_inst = 0; 134 params->exitOnError = exitOnError; 135 params->updateOnError = updateOnError; 136 params->deferRegistration = defer_registration; 137 params->functionTrace = function_trace; 138 params->functionTraceStart = function_trace_start; 139 params->clock = clock; 140 // Hack to touch all parameters. Consider not deriving Checker 141 // from BaseCPU..it's not really a CPU in the end. 142 Counter temp; 143 temp = max_insts_any_thread; 144 temp = max_insts_all_threads; 145 temp = max_loads_any_thread; 146 temp = max_loads_all_threads; 147 temp = stats_reset_inst; 148 Tick temp2 = progress_interval; 149 params->progress_interval = 0; 150 temp2++; 151 BaseMem *cache = icache; 152 cache = dcache; 153 154#if FULL_SYSTEM 155 params->itb = itb; 156 params->dtb = dtb; 157 params->mem = mem; 158 params->system = system; 159 params->cpu_id = cpu_id; 160 params->profile = profile; 161#else 162 params->process = workload; 163#endif 164 165 O3Checker *cpu = new O3Checker(params); 166 return cpu; 167} 168 169REGISTER_SIM_OBJECT("O3Checker", O3Checker) 170