checker.cc revision 2350 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <string>
30
31#include "cpu/checker/cpu.hh"
32#include "cpu/inst_seq.hh"
33#include "cpu/o3/alpha_dyn_inst.hh"
34#include "cpu/o3/alpha_impl.hh"
35#include "mem/base_mem.hh"
36#include "sim/builder.hh"
37#include "sim/process.hh"
38#include "sim/sim_object.hh"
39
40/**
41 * Specific non-templated derived class used for SimObject configuration.
42 */
43class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
44{
45  public:
46    O3Checker(Params *p)
47        : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
48    { }
49};
50
51////////////////////////////////////////////////////////////////////////
52//
53//  CheckerCPU Simulation Object
54//
55BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
56
57    Param<Counter> max_insts_any_thread;
58    Param<Counter> max_insts_all_threads;
59    Param<Counter> max_loads_any_thread;
60    Param<Counter> max_loads_all_threads;
61
62#if FULL_SYSTEM
63    SimObjectParam<AlphaITB *> itb;
64    SimObjectParam<AlphaDTB *> dtb;
65    SimObjectParam<FunctionalMemory *> mem;
66    SimObjectParam<System *> system;
67    Param<int> cpu_id;
68    Param<Tick> profile;
69#else
70    SimObjectParam<Process *> workload;
71#endif // FULL_SYSTEM
72    Param<int> clock;
73    SimObjectParam<BaseMem *> icache;
74    SimObjectParam<BaseMem *> dcache;
75
76    Param<bool> defer_registration;
77    Param<bool> exitOnError;
78    Param<bool> function_trace;
79    Param<Tick> function_trace_start;
80
81END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
82
83BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
84
85    INIT_PARAM(max_insts_any_thread,
86               "terminate when any thread reaches this inst count"),
87    INIT_PARAM(max_insts_all_threads,
88               "terminate when all threads have reached this inst count"),
89    INIT_PARAM(max_loads_any_thread,
90               "terminate when any thread reaches this load count"),
91    INIT_PARAM(max_loads_all_threads,
92               "terminate when all threads have reached this load count"),
93
94#if FULL_SYSTEM
95    INIT_PARAM(itb, "Instruction TLB"),
96    INIT_PARAM(dtb, "Data TLB"),
97    INIT_PARAM(mem, "memory"),
98    INIT_PARAM(system, "system object"),
99    INIT_PARAM(cpu_id, "processor ID"),
100    INIT_PARAM(profile, ""),
101#else
102    INIT_PARAM(workload, "processes to run"),
103#endif // FULL_SYSTEM
104
105    INIT_PARAM(clock, "clock speed"),
106    INIT_PARAM(icache, "L1 instruction cache object"),
107    INIT_PARAM(dcache, "L1 data cache object"),
108
109    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
110    INIT_PARAM(exitOnError, "exit on error"),
111    INIT_PARAM(function_trace, "Enable function trace"),
112    INIT_PARAM(function_trace_start, "Cycle to start function trace")
113
114END_INIT_SIM_OBJECT_PARAMS(O3Checker)
115
116
117CREATE_SIM_OBJECT(O3Checker)
118{
119    O3Checker::Params *params = new O3Checker::Params();
120    params->name = getInstanceName();
121    params->numberOfThreads = 1;
122    params->max_insts_any_thread = 0;
123    params->max_insts_all_threads = 0;
124    params->max_loads_any_thread = 0;
125    params->max_loads_all_threads = 0;
126    params->exitOnError = exitOnError;
127    params->deferRegistration = defer_registration;
128    params->functionTrace = function_trace;
129    params->functionTraceStart = function_trace_start;
130    params->clock = clock;
131    // Hack to touch all parameters.  Consider not deriving Checker
132    // from BaseCPU..it's not really a CPU in the end.
133    Counter temp;
134    temp = max_insts_any_thread;
135    temp = max_insts_all_threads;
136    temp = max_loads_any_thread;
137    temp = max_loads_all_threads;
138    BaseMem *cache = icache;
139    cache = dcache;
140
141#if FULL_SYSTEM
142    params->itb = itb;
143    params->dtb = dtb;
144    params->mem = mem;
145    params->system = system;
146    params->cpu_id = cpu_id;
147    params->profile = profile;
148#else
149    params->process = workload;
150#endif
151
152    O3Checker *cpu = new O3Checker(params);
153    return cpu;
154}
155
156REGISTER_SIM_OBJECT("O3Checker", O3Checker)
157