SConscript revision 10426:cba563d00376
1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Nathan Binkert 30 31import sys 32 33Import('*') 34 35if 'O3CPU' in env['CPU_MODELS']: 36 SimObject('FUPool.py') 37 SimObject('FuncUnitConfig.py') 38 SimObject('O3CPU.py') 39 40 Source('base_dyn_inst.cc') 41 Source('commit.cc') 42 Source('cpu.cc') 43 Source('deriv.cc') 44 Source('decode.cc') 45 Source('dyn_inst.cc') 46 Source('fetch.cc') 47 Source('free_list.cc') 48 Source('fu_pool.cc') 49 Source('iew.cc') 50 Source('inst_queue.cc') 51 Source('lsq.cc') 52 Source('lsq_unit.cc') 53 Source('mem_dep_unit.cc') 54 Source('regfile.cc') 55 Source('rename.cc') 56 Source('rename_map.cc') 57 Source('rob.cc') 58 Source('scoreboard.cc') 59 Source('store_set.cc') 60 Source('thread_context.cc') 61 62 DebugFlag('CommitRate') 63 DebugFlag('IEW') 64 DebugFlag('IQ') 65 DebugFlag('LSQ') 66 DebugFlag('LSQUnit') 67 DebugFlag('MemDepUnit') 68 DebugFlag('O3CPU') 69 DebugFlag('ROB') 70 DebugFlag('Rename') 71 DebugFlag('Scoreboard') 72 DebugFlag('StoreSet') 73 DebugFlag('Writeback') 74 75 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 76 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 77 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 78 79 SimObject('O3Checker.py') 80 Source('checker.cc') 81