SConscript revision 8887
113170Sgiacomo.travaglini@arm.com# -*- mode:python -*- 213170Sgiacomo.travaglini@arm.com 313170Sgiacomo.travaglini@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 413170Sgiacomo.travaglini@arm.com# All rights reserved. 513170Sgiacomo.travaglini@arm.com# 613170Sgiacomo.travaglini@arm.com# Redistribution and use in source and binary forms, with or without 713170Sgiacomo.travaglini@arm.com# modification, are permitted provided that the following conditions are 813170Sgiacomo.travaglini@arm.com# met: redistributions of source code must retain the above copyright 913170Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer; 1013170Sgiacomo.travaglini@arm.com# redistributions in binary form must reproduce the above copyright 1113170Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer in the 1213170Sgiacomo.travaglini@arm.com# documentation and/or other materials provided with the distribution; 1313170Sgiacomo.travaglini@arm.com# neither the name of the copyright holders nor the names of its 1413170Sgiacomo.travaglini@arm.com# contributors may be used to endorse or promote products derived from 1513170Sgiacomo.travaglini@arm.com# this software without specific prior written permission. 1613170Sgiacomo.travaglini@arm.com# 1713170Sgiacomo.travaglini@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1813170Sgiacomo.travaglini@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1913170Sgiacomo.travaglini@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2013170Sgiacomo.travaglini@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2113170Sgiacomo.travaglini@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2213170Sgiacomo.travaglini@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2313170Sgiacomo.travaglini@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2413170Sgiacomo.travaglini@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2513170Sgiacomo.travaglini@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2613170Sgiacomo.travaglini@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2713170Sgiacomo.travaglini@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2813170Sgiacomo.travaglini@arm.com# 2913170Sgiacomo.travaglini@arm.com# Authors: Nathan Binkert 3013170Sgiacomo.travaglini@arm.com 3113170Sgiacomo.travaglini@arm.comimport sys 3213170Sgiacomo.travaglini@arm.com 3313170Sgiacomo.travaglini@arm.comImport('*') 3413170Sgiacomo.travaglini@arm.com 3513170Sgiacomo.travaglini@arm.comif 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: 3613170Sgiacomo.travaglini@arm.com DebugFlag('CommitRate') 3713170Sgiacomo.travaglini@arm.com DebugFlag('IEW') 3813170Sgiacomo.travaglini@arm.com DebugFlag('IQ') 3913170Sgiacomo.travaglini@arm.com 4013170Sgiacomo.travaglini@arm.comif 'O3CPU' in env['CPU_MODELS']: 4113170Sgiacomo.travaglini@arm.com SimObject('FUPool.py') 4213170Sgiacomo.travaglini@arm.com SimObject('FuncUnitConfig.py') 4313171Sgiacomo.travaglini@arm.com SimObject('O3CPU.py') 4413171Sgiacomo.travaglini@arm.com 4513171Sgiacomo.travaglini@arm.com Source('base_dyn_inst.cc') 4613170Sgiacomo.travaglini@arm.com Source('bpred_unit.cc') 4713170Sgiacomo.travaglini@arm.com Source('commit.cc') 4813170Sgiacomo.travaglini@arm.com Source('cpu.cc') 4913170Sgiacomo.travaglini@arm.com Source('cpu_builder.cc') 5013170Sgiacomo.travaglini@arm.com Source('decode.cc') 5113170Sgiacomo.travaglini@arm.com Source('dyn_inst.cc') 5213170Sgiacomo.travaglini@arm.com Source('fetch.cc') 5313170Sgiacomo.travaglini@arm.com Source('free_list.cc') 5413170Sgiacomo.travaglini@arm.com Source('fu_pool.cc') 5513171Sgiacomo.travaglini@arm.com Source('iew.cc') 5613171Sgiacomo.travaglini@arm.com Source('inst_queue.cc') 5713171Sgiacomo.travaglini@arm.com Source('lsq.cc') 5813171Sgiacomo.travaglini@arm.com Source('lsq_unit.cc') 5913171Sgiacomo.travaglini@arm.com Source('mem_dep_unit.cc') 6013171Sgiacomo.travaglini@arm.com Source('rename.cc') 6113171Sgiacomo.travaglini@arm.com Source('rename_map.cc') 6213171Sgiacomo.travaglini@arm.com Source('rob.cc') 6313171Sgiacomo.travaglini@arm.com Source('scoreboard.cc') 6413171Sgiacomo.travaglini@arm.com Source('store_set.cc') 6513171Sgiacomo.travaglini@arm.com Source('thread_context.cc') 6613171Sgiacomo.travaglini@arm.com 6713171Sgiacomo.travaglini@arm.com DebugFlag('LSQ') 6813171Sgiacomo.travaglini@arm.com DebugFlag('LSQUnit') 6913171Sgiacomo.travaglini@arm.com DebugFlag('MemDepUnit') 7013171Sgiacomo.travaglini@arm.com DebugFlag('O3CPU') 7113171Sgiacomo.travaglini@arm.com DebugFlag('ROB') 7213171Sgiacomo.travaglini@arm.com DebugFlag('Rename') 7313171Sgiacomo.travaglini@arm.com DebugFlag('Scoreboard') 7413171Sgiacomo.travaglini@arm.com DebugFlag('StoreSet') 7513171Sgiacomo.travaglini@arm.com DebugFlag('Writeback') 7613171Sgiacomo.travaglini@arm.com 7713171Sgiacomo.travaglini@arm.com CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 7813170Sgiacomo.travaglini@arm.com 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 7913170Sgiacomo.travaglini@arm.com 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 8013170Sgiacomo.travaglini@arm.com 8113170Sgiacomo.travaglini@arm.com SimObject('O3Checker.py') 8213170Sgiacomo.travaglini@arm.com Source('checker_builder.cc') 8313170Sgiacomo.travaglini@arm.com