SConscript revision 4497
12817Sksewell@umich.edu# -*- mode:python -*-
22817Sksewell@umich.edu
32817Sksewell@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
42817Sksewell@umich.edu# All rights reserved.
52817Sksewell@umich.edu#
62817Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without
72817Sksewell@umich.edu# modification, are permitted provided that the following conditions are
82817Sksewell@umich.edu# met: redistributions of source code must retain the above copyright
92817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer;
102817Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright
112817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the
122817Sksewell@umich.edu# documentation and/or other materials provided with the distribution;
132817Sksewell@umich.edu# neither the name of the copyright holders nor the names of its
142817Sksewell@umich.edu# contributors may be used to endorse or promote products derived from
152817Sksewell@umich.edu# this software without specific prior written permission.
162817Sksewell@umich.edu#
172817Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182817Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192817Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202817Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212817Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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262817Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272817Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282817Sksewell@umich.edu#
294202Sbinkertn@umich.edu# Authors: Nathan Binkert
302817Sksewell@umich.edu
312817Sksewell@umich.eduimport sys
322817Sksewell@umich.edu
334202Sbinkertn@umich.eduImport('*')
342817Sksewell@umich.edu
354202Sbinkertn@umich.eduif 'O3CPU' in env['CPU_MODELS']:
364486Sbinkertn@umich.edu    SimObject('FUPool.py')
374486Sbinkertn@umich.edu    SimObject('FuncUnitConfig.py')
384486Sbinkertn@umich.edu    SimObject('O3CPU.py')
394486Sbinkertn@umich.edu
404202Sbinkertn@umich.edu    Source('base_dyn_inst.cc')
414202Sbinkertn@umich.edu    Source('bpred_unit.cc')
424202Sbinkertn@umich.edu    Source('commit.cc')
434202Sbinkertn@umich.edu    Source('cpu.cc')
444202Sbinkertn@umich.edu    Source('decode.cc')
454202Sbinkertn@umich.edu    Source('fetch.cc')
464202Sbinkertn@umich.edu    Source('free_list.cc')
474202Sbinkertn@umich.edu    Source('fu_pool.cc')
484202Sbinkertn@umich.edu    Source('iew.cc')
494202Sbinkertn@umich.edu    Source('inst_queue.cc')
504202Sbinkertn@umich.edu    Source('lsq.cc')
514202Sbinkertn@umich.edu    Source('lsq_unit.cc')
524202Sbinkertn@umich.edu    Source('mem_dep_unit.cc')
534202Sbinkertn@umich.edu    Source('rename.cc')
544202Sbinkertn@umich.edu    Source('rename_map.cc')
554202Sbinkertn@umich.edu    Source('rob.cc')
564202Sbinkertn@umich.edu    Source('scoreboard.cc')
574202Sbinkertn@umich.edu    Source('store_set.cc')
582817Sksewell@umich.edu
594202Sbinkertn@umich.edu    if env['TARGET_ISA'] == 'alpha':
604202Sbinkertn@umich.edu        Source('alpha/cpu.cc')
614202Sbinkertn@umich.edu        Source('alpha/cpu_builder.cc')
624202Sbinkertn@umich.edu        Source('alpha/dyn_inst.cc')
634202Sbinkertn@umich.edu        Source('alpha/thread_context.cc')
644202Sbinkertn@umich.edu    elif env['TARGET_ISA'] == 'mips':
654202Sbinkertn@umich.edu        Source('mips/cpu.cc')
664202Sbinkertn@umich.edu        Source('mips/cpu_builder.cc')
674202Sbinkertn@umich.edu        Source('mips/dyn_inst.cc')
684202Sbinkertn@umich.edu        Source('mips/thread_context.cc')
694202Sbinkertn@umich.edu    elif env['TARGET_ISA'] == 'sparc':
704202Sbinkertn@umich.edu        Source('sparc/cpu.cc')
714202Sbinkertn@umich.edu        Source('sparc/cpu_builder.cc')
724202Sbinkertn@umich.edu        Source('sparc/dyn_inst.cc')
734202Sbinkertn@umich.edu        Source('sparc/thread_context.cc')
744202Sbinkertn@umich.edu    else:
754202Sbinkertn@umich.edu        sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
762817Sksewell@umich.edu
774202Sbinkertn@umich.edu    if env['USE_CHECKER']:
784497Sbinkertn@umich.edu        SimObject('O3Checker.py')
794202Sbinkertn@umich.edu        Source('checker_builder.cc')
802817Sksewell@umich.edu
814202Sbinkertn@umich.eduif 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
824202Sbinkertn@umich.edu    Source('2bit_local_pred.cc')
834202Sbinkertn@umich.edu    Source('btb.cc')
844202Sbinkertn@umich.edu    Source('ras.cc')
854202Sbinkertn@umich.edu    Source('tournament_pred.cc')
862817Sksewell@umich.edu
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