O3CPU.py revision 9518 
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.defines import buildEnv
30from m5.params import *
31from m5.proxy import *
32from BaseCPU import BaseCPU
33from FUPool import *
34from O3Checker import O3Checker
35from BranchPredictor import BranchPredictor
36
37class DerivO3CPU(BaseCPU):
38    type = 'DerivO3CPU'
39    cxx_header = 'cpu/o3/deriv.hh'
40
41    @classmethod
42    def memory_mode(cls):
43        return 'timing'
44
45    @classmethod
46    def require_caches(cls):
47        return True
48
49    @classmethod
50    def support_take_over(cls):
51        return True
52
53    activity = Param.Unsigned(0, "Initial count")
54
55    cachePorts = Param.Unsigned(200, "Cache Ports")
56
57    decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
58    renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
59    iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
60                                   "delay")
61    commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
62    fetchWidth = Param.Unsigned(8, "Fetch width")
63
64    renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
65    iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
66                                    "delay")
67    commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
68    fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
69    decodeWidth = Param.Unsigned(8, "Decode width")
70
71    iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
72                                    "delay")
73    commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
74    decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
75    renameWidth = Param.Unsigned(8, "Rename width")
76
77    commitToIEWDelay = Param.Cycles(1, "Commit to "
78               "Issue/Execute/Writeback delay")
79    renameToIEWDelay = Param.Cycles(2, "Rename to "
80               "Issue/Execute/Writeback delay")
81    issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
82              "to the IEW stage)")
83    dispatchWidth = Param.Unsigned(8, "Dispatch width")
84    issueWidth = Param.Unsigned(8, "Issue width")
85    wbWidth = Param.Unsigned(8, "Writeback width")
86    wbDepth = Param.Unsigned(1, "Writeback depth")
87    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
88
89    iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
90               "delay")
91    renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
92    commitWidth = Param.Unsigned(8, "Commit width")
93    squashWidth = Param.Unsigned(8, "Squash width")
94    trapLatency = Param.Cycles(13, "Trap latency")
95    fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
96
97    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
98    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
99
100    LQEntries = Param.Unsigned(32, "Number of load queue entries")
101    SQEntries = Param.Unsigned(32, "Number of store queue entries")
102    LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
103    LSQCheckLoads = Param.Bool(True,
104        "Should dependency violations be checked for loads & stores or just stores")
105    store_set_clear_period = Param.Unsigned(250000,
106            "Number of load/store insts before the dep predictor should be invalidated")
107    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
108    SSITSize = Param.Unsigned(1024, "Store set ID table size")
109
110    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
111
112    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
113    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
114                                      "registers")
115    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
116    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
117
118    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
119    smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
120    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
121    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
122    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
123    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
124    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
125    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
126    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
127
128    branchPred = BranchPredictor(numThreads = Parent.numThreads)
129    needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
130                          "Enable TSO Memory model")
131
132    def addCheckerCpu(self):
133        if buildEnv['TARGET_ISA'] in ['arm']:
134            from ArmTLB import ArmTLB
135
136            self.checker = O3Checker(workload=self.workload,
137                                     exitOnError=False,
138                                     updateOnError=True,
139                                     warnOnlyOnLoadError=True)
140            self.checker.itb = ArmTLB(size = self.itb.size)
141            self.checker.dtb = ArmTLB(size = self.dtb.size)
142            self.checker.cpu_id = self.cpu_id
143
144        else:
145            print "ERROR: Checker only supported under ARM ISA!"
146            exit(1)
147