O3CPU.py revision 9480:d059f8a95a42 
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
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8# redistributions in binary form must reproduce the above copyright
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.defines import buildEnv
30from m5.params import *
31from m5.proxy import *
32from BaseCPU import BaseCPU
33from FUPool import *
34from O3Checker import O3Checker
35from BranchPredictor import BranchPredictor
36
37class DerivO3CPU(BaseCPU):
38    type = 'DerivO3CPU'
39    cxx_header = 'cpu/o3/deriv.hh'
40
41    activity = Param.Unsigned(0, "Initial count")
42
43    cachePorts = Param.Unsigned(200, "Cache Ports")
44
45    decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
46    renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
47    iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
48                                   "delay")
49    commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
50    fetchWidth = Param.Unsigned(8, "Fetch width")
51
52    renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
53    iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
54                                    "delay")
55    commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
56    fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
57    decodeWidth = Param.Unsigned(8, "Decode width")
58
59    iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
60                                    "delay")
61    commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
62    decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
63    renameWidth = Param.Unsigned(8, "Rename width")
64
65    commitToIEWDelay = Param.Cycles(1, "Commit to "
66               "Issue/Execute/Writeback delay")
67    renameToIEWDelay = Param.Cycles(2, "Rename to "
68               "Issue/Execute/Writeback delay")
69    issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
70              "to the IEW stage)")
71    dispatchWidth = Param.Unsigned(8, "Dispatch width")
72    issueWidth = Param.Unsigned(8, "Issue width")
73    wbWidth = Param.Unsigned(8, "Writeback width")
74    wbDepth = Param.Unsigned(1, "Writeback depth")
75    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
76
77    iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
78               "delay")
79    renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
80    commitWidth = Param.Unsigned(8, "Commit width")
81    squashWidth = Param.Unsigned(8, "Squash width")
82    trapLatency = Param.Cycles(13, "Trap latency")
83    fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
84
85    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
86    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
87
88    LQEntries = Param.Unsigned(32, "Number of load queue entries")
89    SQEntries = Param.Unsigned(32, "Number of store queue entries")
90    LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
91    LSQCheckLoads = Param.Bool(True,
92        "Should dependency violations be checked for loads & stores or just stores")
93    store_set_clear_period = Param.Unsigned(250000,
94            "Number of load/store insts before the dep predictor should be invalidated")
95    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
96    SSITSize = Param.Unsigned(1024, "Store set ID table size")
97
98    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
99
100    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
101    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
102                                      "registers")
103    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
104    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
105
106    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
107    smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
108    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
109    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
110    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
111    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
112    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
113    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
114    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
115
116    branchPred = BranchPredictor(numThreads = Parent.numThreads)
117    needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
118                          "Enable TSO Memory model")
119
120    def addCheckerCpu(self):
121        if buildEnv['TARGET_ISA'] in ['arm']:
122            from ArmTLB import ArmTLB
123
124            self.checker = O3Checker(workload=self.workload,
125                                     exitOnError=False,
126                                     updateOnError=True,
127                                     warnOnlyOnLoadError=True)
128            self.checker.itb = ArmTLB(size = self.itb.size)
129            self.checker.dtb = ArmTLB(size = self.dtb.size)
130            self.checker.cpu_id = self.cpu_id
131
132        else:
133            print "ERROR: Checker only supported under ARM ISA!"
134            exit(1)
135