O3CPU.py revision 9341:a0eff1e9c773
113558Snikos.nikoleris@arm.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 58839Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 68839Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 78839Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 88839Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 98839Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 108839Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 118839Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 128839Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 133101Sstever@eecs.umich.edu# this software without specific prior written permission. 148579Ssteve.reinhardt@amd.com# 153101Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163101Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173101Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183101Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193101Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203101Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213101Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223101Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233101Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243101Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253101Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263101Sstever@eecs.umich.edu# 273101Sstever@eecs.umich.edu# Authors: Kevin Lim 283101Sstever@eecs.umich.edu 293101Sstever@eecs.umich.edufrom m5.defines import buildEnv 303101Sstever@eecs.umich.edufrom m5.params import * 313101Sstever@eecs.umich.edufrom m5.proxy import * 323101Sstever@eecs.umich.edufrom BaseCPU import BaseCPU 333101Sstever@eecs.umich.edufrom FUPool import * 343101Sstever@eecs.umich.edufrom O3Checker import O3Checker 353101Sstever@eecs.umich.edu 363101Sstever@eecs.umich.educlass DerivO3CPU(BaseCPU): 373101Sstever@eecs.umich.edu type = 'DerivO3CPU' 383101Sstever@eecs.umich.edu cxx_header = 'cpu/o3/deriv.hh' 393101Sstever@eecs.umich.edu 403101Sstever@eecs.umich.edu activity = Param.Unsigned(0, "Initial count") 413101Sstever@eecs.umich.edu 427778Sgblack@eecs.umich.edu cachePorts = Param.Unsigned(200, "Cache Ports") 438839Sandreas.hansson@arm.com 443101Sstever@eecs.umich.edu decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 453101Sstever@eecs.umich.edu renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 463101Sstever@eecs.umich.edu iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 473101Sstever@eecs.umich.edu "delay") 483101Sstever@eecs.umich.edu commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 493101Sstever@eecs.umich.edu fetchWidth = Param.Unsigned(8, "Fetch width") 503101Sstever@eecs.umich.edu 513101Sstever@eecs.umich.edu renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 523101Sstever@eecs.umich.edu iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 533101Sstever@eecs.umich.edu "delay") 543101Sstever@eecs.umich.edu commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 553101Sstever@eecs.umich.edu fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 563101Sstever@eecs.umich.edu decodeWidth = Param.Unsigned(8, "Decode width") 573101Sstever@eecs.umich.edu 583101Sstever@eecs.umich.edu iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 593101Sstever@eecs.umich.edu "delay") 603101Sstever@eecs.umich.edu commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 613101Sstever@eecs.umich.edu decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 6212563Sgabeblack@google.com renameWidth = Param.Unsigned(8, "Rename width") 6312563Sgabeblack@google.com 643885Sbinkertn@umich.edu commitToIEWDelay = Param.Cycles(1, "Commit to " 653885Sbinkertn@umich.edu "Issue/Execute/Writeback delay") 664762Snate@binkert.org renameToIEWDelay = Param.Cycles(2, "Rename to " 673885Sbinkertn@umich.edu "Issue/Execute/Writeback delay") 683885Sbinkertn@umich.edu issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 697528Ssteve.reinhardt@amd.com "to the IEW stage)") 703885Sbinkertn@umich.edu dispatchWidth = Param.Unsigned(8, "Dispatch width") 7113714Sandreas.sandberg@arm.com issueWidth = Param.Unsigned(8, "Issue width") 7213714Sandreas.sandberg@arm.com wbWidth = Param.Unsigned(8, "Writeback width") 7313714Sandreas.sandberg@arm.com wbDepth = Param.Unsigned(1, "Writeback depth") 743101Sstever@eecs.umich.edu fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 754762Snate@binkert.org 764762Snate@binkert.org iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 774762Snate@binkert.org "delay") 784762Snate@binkert.org renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 794762Snate@binkert.org commitWidth = Param.Unsigned(8, "Commit width") 804762Snate@binkert.org squashWidth = Param.Unsigned(8, "Squash width") 814762Snate@binkert.org trapLatency = Param.Cycles(13, "Trap latency") 824762Snate@binkert.org fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 834762Snate@binkert.org 845033Smilesck@eecs.umich.edu backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 855033Smilesck@eecs.umich.edu forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 865033Smilesck@eecs.umich.edu 875033Smilesck@eecs.umich.edu predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 885033Smilesck@eecs.umich.edu localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 895033Smilesck@eecs.umich.edu localCtrBits = Param.Unsigned(2, "Bits per counter") 905033Smilesck@eecs.umich.edu localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 915033Smilesck@eecs.umich.edu localHistoryBits = Param.Unsigned(11, "Bits for the local history") 925033Smilesck@eecs.umich.edu globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 935033Smilesck@eecs.umich.edu globalCtrBits = Param.Unsigned(2, "Bits per counter") 943101Sstever@eecs.umich.edu globalHistoryBits = Param.Unsigned(13, "Bits of history") 953101Sstever@eecs.umich.edu choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 963101Sstever@eecs.umich.edu choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 975033Smilesck@eecs.umich.edu 9810267SGeoffrey.Blake@arm.com BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 998596Ssteve.reinhardt@amd.com BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 1008596Ssteve.reinhardt@amd.com 1018596Ssteve.reinhardt@amd.com RASSize = Param.Unsigned(16, "RAS size") 1028596Ssteve.reinhardt@amd.com 1037673Snate@binkert.org LQEntries = Param.Unsigned(32, "Number of load queue entries") 1047673Snate@binkert.org SQEntries = Param.Unsigned(32, "Number of store queue entries") 1057673Snate@binkert.org LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1067673Snate@binkert.org LSQCheckLoads = Param.Bool(True, 10711988Sandreas.sandberg@arm.com "Should dependency violations be checked for loads & stores or just stores") 10811988Sandreas.sandberg@arm.com store_set_clear_period = Param.Unsigned(250000, 10911988Sandreas.sandberg@arm.com "Number of load/store insts before the dep predictor should be invalidated") 11011988Sandreas.sandberg@arm.com LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1113101Sstever@eecs.umich.edu SSITSize = Param.Unsigned(1024, "Store set ID table size") 1123101Sstever@eecs.umich.edu 1133101Sstever@eecs.umich.edu numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1143101Sstever@eecs.umich.edu 1153101Sstever@eecs.umich.edu numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 11610380SAndrew.Bardsley@arm.com numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 11710380SAndrew.Bardsley@arm.com "registers") 11810380SAndrew.Bardsley@arm.com numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 11910380SAndrew.Bardsley@arm.com numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 12010380SAndrew.Bardsley@arm.com 12110380SAndrew.Bardsley@arm.com instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 12210458Sandreas.hansson@arm.com 12310458Sandreas.hansson@arm.com smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 12410458Sandreas.hansson@arm.com smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 12510458Sandreas.hansson@arm.com smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 12610458Sandreas.hansson@arm.com smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 12710458Sandreas.hansson@arm.com smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 12810458Sandreas.hansson@arm.com smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 12910458Sandreas.hansson@arm.com smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 13010458Sandreas.hansson@arm.com smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 13110458Sandreas.hansson@arm.com smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 13210458Sandreas.hansson@arm.com 13310458Sandreas.hansson@arm.com needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 1343101Sstever@eecs.umich.edu "Enable TSO Memory model") 1353101Sstever@eecs.umich.edu 1363101Sstever@eecs.umich.edu def addCheckerCpu(self): 1373101Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['arm']: 1383101Sstever@eecs.umich.edu from ArmTLB import ArmTLB 13910267SGeoffrey.Blake@arm.com 14010267SGeoffrey.Blake@arm.com self.checker = O3Checker(workload=self.workload, 14110267SGeoffrey.Blake@arm.com exitOnError=False, 14210267SGeoffrey.Blake@arm.com updateOnError=True, 1433101Sstever@eecs.umich.edu warnOnlyOnLoadError=True) 1443101Sstever@eecs.umich.edu self.checker.itb = ArmTLB(size = self.itb.size) 1453101Sstever@eecs.umich.edu self.checker.dtb = ArmTLB(size = self.dtb.size) 1463101Sstever@eecs.umich.edu self.checker.cpu_id = self.cpu_id 1473101Sstever@eecs.umich.edu 1483101Sstever@eecs.umich.edu else: 1493101Sstever@eecs.umich.edu print "ERROR: Checker only supported under ARM ISA!" 1503101Sstever@eecs.umich.edu exit(1) 1513101Sstever@eecs.umich.edu