O3CPU.py revision 8793:5f25086326ac 
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.defines import buildEnv
30from m5.params import *
31from m5.proxy import *
32from BaseCPU import BaseCPU
33from FUPool import *
34
35if buildEnv['USE_CHECKER']:
36    from O3Checker import O3Checker
37
38class DerivO3CPU(BaseCPU):
39    type = 'DerivO3CPU'
40    activity = Param.Unsigned(0, "Initial count")
41
42    if buildEnv['USE_CHECKER']:
43        checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
44                                          exitOnError=False,
45                                          updateOnError=True,
46                                          warnOnlyOnLoadError=False),
47                                "checker")
48        checker.itb = Parent.itb
49        checker.dtb = Parent.dtb
50
51    cachePorts = Param.Unsigned(200, "Cache Ports")
52    icache_port = Port("Instruction Port")
53    dcache_port = Port("Data Port")
54    _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port']
55
56    decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
57    renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
58    iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
59                                     "delay")
60    commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
61    fetchWidth = Param.Unsigned(8, "Fetch width")
62
63    renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
64    iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
65               "delay")
66    commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
67    fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
68    decodeWidth = Param.Unsigned(8, "Decode width")
69
70    iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
71               "delay")
72    commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
73    decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
74    renameWidth = Param.Unsigned(8, "Rename width")
75
76    commitToIEWDelay = Param.Unsigned(1, "Commit to "
77               "Issue/Execute/Writeback delay")
78    renameToIEWDelay = Param.Unsigned(2, "Rename to "
79               "Issue/Execute/Writeback delay")
80    issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
81              "to the IEW stage)")
82    dispatchWidth = Param.Unsigned(8, "Dispatch width")
83    issueWidth = Param.Unsigned(8, "Issue width")
84    wbWidth = Param.Unsigned(8, "Writeback width")
85    wbDepth = Param.Unsigned(1, "Writeback depth")
86    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
87
88    iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
89               "delay")
90    renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
91    commitWidth = Param.Unsigned(8, "Commit width")
92    squashWidth = Param.Unsigned(8, "Squash width")
93    trapLatency = Param.Tick(13, "Trap latency")
94    fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
95
96    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
97    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
98
99    predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
100    localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
101    localCtrBits = Param.Unsigned(2, "Bits per counter")
102    localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
103    localHistoryBits = Param.Unsigned(11, "Bits for the local history")
104    globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
105    globalCtrBits = Param.Unsigned(2, "Bits per counter")
106    globalHistoryBits = Param.Unsigned(13, "Bits of history")
107    choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
108    choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
109
110    BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
111    BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
112
113    RASSize = Param.Unsigned(16, "RAS size")
114
115    LQEntries = Param.Unsigned(32, "Number of load queue entries")
116    SQEntries = Param.Unsigned(32, "Number of store queue entries")
117    LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
118    LSQCheckLoads = Param.Bool(True,
119        "Should dependency violations be checked for loads & stores or just stores")
120    store_set_clear_period = Param.Unsigned(250000,
121            "Number of load/store insts before the dep predictor should be invalidated")
122    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
123    SSITSize = Param.Unsigned(1024, "Store set ID table size")
124
125    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
126
127    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
128    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
129                                      "registers")
130    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
131    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
132
133    instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
134
135    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
136    smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
137    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
138    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
139    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
140    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
141    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
142    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
143    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
144
145    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
146        BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
147        self.icache.tgts_per_mshr = 20
148        self.dcache.tgts_per_mshr = 20
149