O3CPU.py revision 8707:489489c67fd9
15217Ssaidi@eecs.umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 212109SRekai.GonzalezAlberquilla@arm.com# All rights reserved. 39920Syasuko.eckert@amd.com# 49428SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 59428SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 69428SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 79428SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 89428SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 99428SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 109428SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 119428SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 129428SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 139428SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 149428SAndreas.Sandberg@ARM.com# 155217Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165217Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175217Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185217Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195217Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205217Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215217Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225217Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235217Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245217Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255217Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265217Ssaidi@eecs.umich.edu# 275217Ssaidi@eecs.umich.edu# Authors: Kevin Lim 285217Ssaidi@eecs.umich.edu 295217Ssaidi@eecs.umich.edufrom m5.defines import buildEnv 305217Ssaidi@eecs.umich.edufrom m5.params import * 315217Ssaidi@eecs.umich.edufrom m5.proxy import * 325217Ssaidi@eecs.umich.edufrom BaseCPU import BaseCPU 335217Ssaidi@eecs.umich.edufrom FUPool import * 345217Ssaidi@eecs.umich.edu 355217Ssaidi@eecs.umich.eduif buildEnv['USE_CHECKER']: 365217Ssaidi@eecs.umich.edu from O3Checker import O3Checker 375217Ssaidi@eecs.umich.edu 385217Ssaidi@eecs.umich.educlass DerivO3CPU(BaseCPU): 395217Ssaidi@eecs.umich.edu type = 'DerivO3CPU' 405217Ssaidi@eecs.umich.edu activity = Param.Unsigned(0, "Initial count") 415217Ssaidi@eecs.umich.edu 425217Ssaidi@eecs.umich.edu if buildEnv['USE_CHECKER']: 435217Ssaidi@eecs.umich.edu if not buildEnv['FULL_SYSTEM']: 4411793Sbrandon.potter@amd.com checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 4511793Sbrandon.potter@amd.com exitOnError=False, 4611627Smichael.lebeane@amd.com updateOnError=True, 4712334Sgabeblack@google.com warnOnlyOnLoadError=False), 485217Ssaidi@eecs.umich.edu "checker") 496658Snate@binkert.org else: 509441SAndreas.Sandberg@ARM.com checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, 519441SAndreas.Sandberg@ARM.com warnOnlyOnLoadError=False), "checker") 528232Snate@binkert.org checker.itb = Parent.itb 5311627Smichael.lebeane@amd.com checker.dtb = Parent.dtb 5411627Smichael.lebeane@amd.com 559441SAndreas.Sandberg@ARM.com cachePorts = Param.Unsigned(200, "Cache Ports") 565217Ssaidi@eecs.umich.edu 575217Ssaidi@eecs.umich.edu decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 585217Ssaidi@eecs.umich.edu renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 595217Ssaidi@eecs.umich.edu iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 605217Ssaidi@eecs.umich.edu "delay") 615217Ssaidi@eecs.umich.edu commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 625217Ssaidi@eecs.umich.edu fetchWidth = Param.Unsigned(8, "Fetch width") 635217Ssaidi@eecs.umich.edu 645217Ssaidi@eecs.umich.edu renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 655217Ssaidi@eecs.umich.edu iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 665217Ssaidi@eecs.umich.edu "delay") 675217Ssaidi@eecs.umich.edu commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 685217Ssaidi@eecs.umich.edu fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 695217Ssaidi@eecs.umich.edu decodeWidth = Param.Unsigned(8, "Decode width") 705217Ssaidi@eecs.umich.edu 715217Ssaidi@eecs.umich.edu iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 725217Ssaidi@eecs.umich.edu "delay") 735217Ssaidi@eecs.umich.edu commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 745217Ssaidi@eecs.umich.edu decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 755217Ssaidi@eecs.umich.edu renameWidth = Param.Unsigned(8, "Rename width") 765217Ssaidi@eecs.umich.edu 775217Ssaidi@eecs.umich.edu commitToIEWDelay = Param.Unsigned(1, "Commit to " 785217Ssaidi@eecs.umich.edu "Issue/Execute/Writeback delay") 7912109SRekai.GonzalezAlberquilla@arm.com renameToIEWDelay = Param.Unsigned(2, "Rename to " 8012109SRekai.GonzalezAlberquilla@arm.com "Issue/Execute/Writeback delay") 8112109SRekai.GonzalezAlberquilla@arm.com issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 8212109SRekai.GonzalezAlberquilla@arm.com "to the IEW stage)") 8312109SRekai.GonzalezAlberquilla@arm.com dispatchWidth = Param.Unsigned(8, "Dispatch width") 8412109SRekai.GonzalezAlberquilla@arm.com issueWidth = Param.Unsigned(8, "Issue width") 8512109SRekai.GonzalezAlberquilla@arm.com wbWidth = Param.Unsigned(8, "Writeback width") 8612109SRekai.GonzalezAlberquilla@arm.com wbDepth = Param.Unsigned(1, "Writeback depth") 8712109SRekai.GonzalezAlberquilla@arm.com fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 8812109SRekai.GonzalezAlberquilla@arm.com 895217Ssaidi@eecs.umich.edu iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 905217Ssaidi@eecs.umich.edu "delay") 915217Ssaidi@eecs.umich.edu renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 925217Ssaidi@eecs.umich.edu commitWidth = Param.Unsigned(8, "Commit width") 935217Ssaidi@eecs.umich.edu squashWidth = Param.Unsigned(8, "Squash width") 945217Ssaidi@eecs.umich.edu trapLatency = Param.Tick(13, "Trap latency") 955217Ssaidi@eecs.umich.edu fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 965217Ssaidi@eecs.umich.edu 979920Syasuko.eckert@amd.com backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 989920Syasuko.eckert@amd.com forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 999920Syasuko.eckert@amd.com 1009920Syasuko.eckert@amd.com predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 1019920Syasuko.eckert@amd.com localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 1029920Syasuko.eckert@amd.com localCtrBits = Param.Unsigned(2, "Bits per counter") 1039920Syasuko.eckert@amd.com localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 1049920Syasuko.eckert@amd.com localHistoryBits = Param.Unsigned(11, "Bits for the local history") 1057720Sgblack@eecs.umich.edu globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 1067720Sgblack@eecs.umich.edu globalCtrBits = Param.Unsigned(2, "Bits per counter") 1075712Shsul@eecs.umich.edu globalHistoryBits = Param.Unsigned(13, "Bits of history") 1085712Shsul@eecs.umich.edu choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 1095217Ssaidi@eecs.umich.edu choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 1105217Ssaidi@eecs.umich.edu 1115714Shsul@eecs.umich.edu BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 11211005Sandreas.sandberg@arm.com BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 11311005Sandreas.sandberg@arm.com 11411005Sandreas.sandberg@arm.com RASSize = Param.Unsigned(16, "RAS size") 1155714Shsul@eecs.umich.edu 1165714Shsul@eecs.umich.edu LQEntries = Param.Unsigned(32, "Number of load queue entries") 1175714Shsul@eecs.umich.edu SQEntries = Param.Unsigned(32, "Number of store queue entries") 1185217Ssaidi@eecs.umich.edu LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1199428SAndreas.Sandberg@ARM.com LSQCheckLoads = Param.Bool(True, 1209428SAndreas.Sandberg@ARM.com "Should dependency violations be checked for loads & stores or just stores") 12111627Smichael.lebeane@amd.com store_set_clear_period = Param.Unsigned(250000, 12211627Smichael.lebeane@amd.com "Number of load/store insts before the dep predictor should be invalidated") 12311627Smichael.lebeane@amd.com LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 12411627Smichael.lebeane@amd.com SSITSize = Param.Unsigned(1024, "Store set ID table size") 12511627Smichael.lebeane@amd.com 12611627Smichael.lebeane@amd.com numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 12711627Smichael.lebeane@amd.com 12811627Smichael.lebeane@amd.com numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 12911627Smichael.lebeane@amd.com numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 13011627Smichael.lebeane@amd.com "registers") 13111627Smichael.lebeane@amd.com numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 13211627Smichael.lebeane@amd.com numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 13311627Smichael.lebeane@amd.com 13411627Smichael.lebeane@amd.com instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 13511627Smichael.lebeane@amd.com 13611627Smichael.lebeane@amd.com smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 13711627Smichael.lebeane@amd.com smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 13811627Smichael.lebeane@amd.com smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 13911627Smichael.lebeane@amd.com smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 14011627Smichael.lebeane@amd.com smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 14111627Smichael.lebeane@amd.com smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 14211627Smichael.lebeane@amd.com smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 14311627Smichael.lebeane@amd.com smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 14411627Smichael.lebeane@amd.com smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 14511627Smichael.lebeane@amd.com 14611627Smichael.lebeane@amd.com