O3CPU.py revision 8519
13760SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 23760SN/A# All rights reserved. 33760SN/A# 43760SN/A# Redistribution and use in source and binary forms, with or without 53760SN/A# modification, are permitted provided that the following conditions are 63760SN/A# met: redistributions of source code must retain the above copyright 73760SN/A# notice, this list of conditions and the following disclaimer; 83760SN/A# redistributions in binary form must reproduce the above copyright 93760SN/A# notice, this list of conditions and the following disclaimer in the 103760SN/A# documentation and/or other materials provided with the distribution; 113760SN/A# neither the name of the copyright holders nor the names of its 123760SN/A# contributors may be used to endorse or promote products derived from 133760SN/A# this software without specific prior written permission. 143760SN/A# 153760SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163760SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173760SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183760SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193760SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203760SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213760SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223760SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233760SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243760SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253760SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263760SN/A# 273760SN/A# Authors: Kevin Lim 285597Sgblack@eecs.umich.edu 293760SN/Afrom m5.defines import buildEnv 303760SN/Afrom m5.params import * 318229Snate@binkert.orgfrom m5.proxy import * 323760SN/Afrom BaseCPU import BaseCPU 333760SN/Afrom FUPool import * 343760SN/A 355597Sgblack@eecs.umich.eduif buildEnv['USE_CHECKER']: 363760SN/A from O3Checker import O3Checker 37 38class DerivO3CPU(BaseCPU): 39 type = 'DerivO3CPU' 40 activity = Param.Unsigned(0, "Initial count") 41 42 if buildEnv['USE_CHECKER']: 43 if not buildEnv['FULL_SYSTEM']: 44 checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 45 exitOnError=False, 46 updateOnError=True, 47 warnOnlyOnLoadError=False), 48 "checker") 49 else: 50 checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, 51 warnOnlyOnLoadError=False), "checker") 52 checker.itb = Parent.itb 53 checker.dtb = Parent.dtb 54 55 cachePorts = Param.Unsigned(200, "Cache Ports") 56 icache_port = Port("Instruction Port") 57 dcache_port = Port("Data Port") 58 _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port'] 59 60 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 61 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 62 iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 63 "delay") 64 commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 65 fetchWidth = Param.Unsigned(8, "Fetch width") 66 67 renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 68 iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 69 "delay") 70 commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 71 fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 72 decodeWidth = Param.Unsigned(8, "Decode width") 73 74 iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 75 "delay") 76 commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 77 decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 78 renameWidth = Param.Unsigned(8, "Rename width") 79 80 commitToIEWDelay = Param.Unsigned(1, "Commit to " 81 "Issue/Execute/Writeback delay") 82 renameToIEWDelay = Param.Unsigned(2, "Rename to " 83 "Issue/Execute/Writeback delay") 84 issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 85 "to the IEW stage)") 86 dispatchWidth = Param.Unsigned(8, "Dispatch width") 87 issueWidth = Param.Unsigned(8, "Issue width") 88 wbWidth = Param.Unsigned(8, "Writeback width") 89 wbDepth = Param.Unsigned(1, "Writeback depth") 90 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 91 92 iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 93 "delay") 94 renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 95 commitWidth = Param.Unsigned(8, "Commit width") 96 squashWidth = Param.Unsigned(8, "Squash width") 97 trapLatency = Param.Tick(13, "Trap latency") 98 fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 99 100 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 101 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 102 103 predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 104 localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 105 localCtrBits = Param.Unsigned(2, "Bits per counter") 106 localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 107 localHistoryBits = Param.Unsigned(11, "Bits for the local history") 108 globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 109 globalCtrBits = Param.Unsigned(2, "Bits per counter") 110 globalHistoryBits = Param.Unsigned(13, "Bits of history") 111 choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 112 choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 113 114 BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 115 BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 116 117 RASSize = Param.Unsigned(16, "RAS size") 118 119 LQEntries = Param.Unsigned(32, "Number of load queue entries") 120 SQEntries = Param.Unsigned(32, "Number of store queue entries") 121 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 122 LSQCheckLoads = Param.Bool(True, 123 "Should dependency violations be checked for loads & stores or just stores") 124 store_set_clear_period = Param.Unsigned(250000, 125 "Number of load/store insts before the dep predictor should be invalidated") 126 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 127 SSITSize = Param.Unsigned(1024, "Store set ID table size") 128 129 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 130 131 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 132 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 133 "registers") 134 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 135 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 136 137 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 138 139 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 140 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 141 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 142 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 143 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 144 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 145 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 146 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 147 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 148 149 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 150 BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) 151 self.icache.tgts_per_mshr = 20 152 self.dcache.tgts_per_mshr = 20 153