O3CPU.py revision 4303 
1from m5.params import *
2from m5.proxy import *
3from m5 import build_env
4from BaseCPU import BaseCPU
5from Checker import O3Checker
6from FUPool import *
7
8class DerivO3CPU(BaseCPU):
9    type = 'DerivO3CPU'
10    activity = Param.Unsigned(0, "Initial count")
11    numThreads = Param.Unsigned(1, "number of HW thread contexts")
12
13    if build_env['FULL_SYSTEM']:
14        profile = Param.Latency('0ns', "trace the kernel stack")
15    if build_env['USE_CHECKER']:
16        if not build_env['FULL_SYSTEM']:
17            checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
18                                              exitOnError=False,
19                                              updateOnError=True,
20                                              warnOnlyOnLoadError=False),
21                                    "checker")
22        else:
23            checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
24                                              warnOnlyOnLoadError=False), "checker")
25            checker.itb = Parent.itb
26            checker.dtb = Parent.dtb
27
28    cachePorts = Param.Unsigned("Cache Ports")
29    icache_port = Port("Instruction Port")
30    dcache_port = Port("Data Port")
31    _mem_ports = ['icache_port', 'dcache_port']
32
33    decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
34    renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
35    iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
36                                     "delay")
37    commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
38    fetchWidth = Param.Unsigned(8, "Fetch width")
39
40    renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
41    iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
42               "delay")
43    commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
44    fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
45    decodeWidth = Param.Unsigned(8, "Decode width")
46
47    iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
48               "delay")
49    commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
50    decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
51    renameWidth = Param.Unsigned(8, "Rename width")
52
53    commitToIEWDelay = Param.Unsigned(1, "Commit to "
54               "Issue/Execute/Writeback delay")
55    renameToIEWDelay = Param.Unsigned(2, "Rename to "
56               "Issue/Execute/Writeback delay")
57    issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
58              "to the IEW stage)")
59    dispatchWidth = Param.Unsigned(8, "Dispatch width")
60    issueWidth = Param.Unsigned(8, "Issue width")
61    wbWidth = Param.Unsigned(8, "Writeback width")
62    wbDepth = Param.Unsigned(1, "Writeback depth")
63    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
64
65    iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
66               "delay")
67    renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
68    commitWidth = Param.Unsigned(8, "Commit width")
69    squashWidth = Param.Unsigned(8, "Squash width")
70    trapLatency = Param.Tick(13, "Trap latency")
71    fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
72
73    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
74    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
75
76    predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
77    localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
78    localCtrBits = Param.Unsigned(2, "Bits per counter")
79    localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
80    localHistoryBits = Param.Unsigned(11, "Bits for the local history")
81    globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
82    globalCtrBits = Param.Unsigned(2, "Bits per counter")
83    globalHistoryBits = Param.Unsigned(13, "Bits of history")
84    choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
85    choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
86
87    BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
88    BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
89
90    RASSize = Param.Unsigned(16, "RAS size")
91
92    LQEntries = Param.Unsigned(32, "Number of load queue entries")
93    SQEntries = Param.Unsigned(32, "Number of store queue entries")
94    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
95    SSITSize = Param.Unsigned(1024, "Store set ID table size")
96
97    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
98
99    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
100    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
101                                      "registers")
102    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
103    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
104
105    instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
106
107    function_trace = Param.Bool(False, "Enable function trace")
108    function_trace_start = Param.Tick(0, "Cycle to start function trace")
109
110    smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
111    smtFetchPolicy = Param.String("SMT Fetch policy")
112    smtLSQPolicy    = Param.String("SMT LSQ Sharing Policy")
113    smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
114    smtIQPolicy    = Param.String("SMT IQ Sharing Policy")
115    smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
116    smtROBPolicy   = Param.String("SMT ROB Sharing Policy")
117    smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
118    smtCommitPolicy = Param.String("SMT Commit Policy")
119
120    def addPrivateSplitL1Caches(self, ic, dc):
121        BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
122        self.icache.tgts_per_mshr = 20
123        self.dcache.tgts_per_mshr = 20
124