O3CPU.py revision 2318
16145SN/Afrom m5 import *
28683SN/Afrom BaseCPU import BaseCPU
36145SN/A
46145SN/Aclass DerivAlphaFullCPU(BaseCPU):
56145SN/A    type = 'DerivAlphaFullCPU'
66145SN/A
76145SN/A    numThreads = Param.Unsigned("number of HW thread contexts")
86145SN/A
96145SN/A    if not build_env['FULL_SYSTEM']:
106145SN/A        mem = Param.FunctionalMemory(NULL, "memory")
116145SN/A
126145SN/A    checker = Param.BaseCPU(NULL, "checker")
136145SN/A
146145SN/A    cachePorts = Param.Unsigned("Cache Ports")
156145SN/A
166145SN/A    decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
176145SN/A    renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
186145SN/A    iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
196145SN/A               "delay")
206145SN/A    commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
216145SN/A    fetchWidth = Param.Unsigned("Fetch width")
226145SN/A
236145SN/A    renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
246145SN/A    iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
256145SN/A               "delay")
266145SN/A    commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
276145SN/A    fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
286145SN/A    decodeWidth = Param.Unsigned("Decode width")
2910441Snilay@cs.wisc.edu
3010441Snilay@cs.wisc.edu    iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
316145SN/A               "delay")
327055SN/A    commitToRenameDelay = Param.Unsigned("Commit to rename delay")
336145SN/A    decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
346145SN/A    renameWidth = Param.Unsigned("Rename width")
357039SN/A
369104SN/A    commitToIEWDelay = Param.Unsigned("Commit to "
3710301Snilay@cs.wisc.edu               "Issue/Execute/Writeback delay")
389105SN/A    renameToIEWDelay = Param.Unsigned("Rename to "
398174SN/A               "Issue/Execute/Writeback delay")
407039SN/A    issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
417039SN/A              "to the IEW stage)")
427039SN/A    issueWidth = Param.Unsigned("Issue width")
4310970Sdavid.hashe@amd.com    executeWidth = Param.Unsigned("Execute width")
4410301Snilay@cs.wisc.edu    executeIntWidth = Param.Unsigned("Integer execute width")
4510301Snilay@cs.wisc.edu    executeFloatWidth = Param.Unsigned("Floating point execute width")
467039SN/A    executeBranchWidth = Param.Unsigned("Branch execute width")
477039SN/A    executeMemoryWidth = Param.Unsigned("Memory execute width")
486145SN/A    fuPool = Param.FUPool(NULL, "Functional Unit pool")
497039SN/A
507039SN/A    iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
517039SN/A               "delay")
526876SN/A    renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
537039SN/A    commitWidth = Param.Unsigned("Commit width")
547039SN/A    squashWidth = Param.Unsigned("Squash width")
556145SN/A    trapLatency = Param.Tick("Trap latency")
567039SN/A    fetchTrapLatency = Param.Tick("Fetch trap latency")
576145SN/A
587039SN/A    localPredictorSize = Param.Unsigned("Size of local predictor")
597039SN/A    localCtrBits = Param.Unsigned("Bits per counter")
608165SN/A    localHistoryTableSize = Param.Unsigned("Size of local history table")
617039SN/A    localHistoryBits = Param.Unsigned("Bits for the local history")
626145SN/A    globalPredictorSize = Param.Unsigned("Size of global predictor")
637039SN/A    globalCtrBits = Param.Unsigned("Bits per counter")
648165SN/A    globalHistoryBits = Param.Unsigned("Bits of history")
657039SN/A    choicePredictorSize = Param.Unsigned("Size of choice predictor")
666145SN/A    choiceCtrBits = Param.Unsigned("Bits of choice counters")
677039SN/A
687039SN/A    BTBEntries = Param.Unsigned("Number of BTB entries")
696145SN/A    BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
707039SN/A
717039SN/A    RASSize = Param.Unsigned("RAS size")
727039SN/A
737039SN/A    LQEntries = Param.Unsigned("Number of load queue entries")
746145SN/A    SQEntries = Param.Unsigned("Number of store queue entries")
757039SN/A    LFSTSize = Param.Unsigned("Last fetched store table size")
767839SN/A    SSITSize = Param.Unsigned("Store set ID table size")
778193SN/A
788193SN/A    numRobs = Param.Unsigned("Number of Reorder Buffers");
798193SN/A
808193SN/A    numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
816145SN/A    numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
827039SN/A               "registers")
837039SN/A    numIQEntries = Param.Unsigned("Number of instruction queue entries")
846145SN/A    numROBEntries = Param.Unsigned("Number of reorder buffer entries")
857039SN/A
867039SN/A    instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
876145SN/A
887039SN/A    function_trace = Param.Bool(False, "Enable function trace")
897839SN/A    function_trace_start = Param.Tick(0, "Cycle to start function trace")
907839SN/A
916145SN/A    smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
929499SN/A    smtFetchPolicy = Param.String("SMT Fetch policy")
9310969Sdavid.hashe@amd.com    smtLSQPolicy    = Param.String("SMT LSQ Sharing Policy")
9410969Sdavid.hashe@amd.com    smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
9510969Sdavid.hashe@amd.com    smtIQPolicy    = Param.String("SMT IQ Sharing Policy")
966285SN/A    smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
977039SN/A    smtROBPolicy   = Param.String("SMT ROB Sharing Policy")
988683SN/A    smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
996145SN/A    smtCommitPolicy = Param.String("SMT Commit Policy")
1007039SN/A