O3CPU.py revision 13562:8fe39a3fc056
14680Sgblack@eecs.umich.edu# Copyright (c) 2016, 2019 ARM Limited 25442Sgblack@eecs.umich.edu# All rights reserved. 34680Sgblack@eecs.umich.edu# 44680Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 54680Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 64680Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 74680Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 84680Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 94680Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 104680Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 114680Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 124680Sgblack@eecs.umich.edu# 134680Sgblack@eecs.umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 144680Sgblack@eecs.umich.edu# All rights reserved. 154680Sgblack@eecs.umich.edu# 164680Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 174680Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 184680Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 194680Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 204680Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 214680Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 224680Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 234680Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 244680Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 254680Sgblack@eecs.umich.edu# this software without specific prior written permission. 264680Sgblack@eecs.umich.edu# 274680Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284680Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294680Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304680Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314680Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324680Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334680Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3412450Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3512450Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3612450Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374680Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384680Sgblack@eecs.umich.edu# 395543Ssaidi@eecs.umich.edu# Authors: Kevin Lim 404680Sgblack@eecs.umich.edu 414680Sgblack@eecs.umich.edufrom __future__ import print_function 424680Sgblack@eecs.umich.edu 434680Sgblack@eecs.umich.edufrom m5.defines import buildEnv 444680Sgblack@eecs.umich.edufrom m5.params import * 454680Sgblack@eecs.umich.edufrom m5.proxy import * 464680Sgblack@eecs.umich.edufrom BaseCPU import BaseCPU 4712450Sgabeblack@google.comfrom FUPool import * 4812450Sgabeblack@google.comfrom O3Checker import O3Checker 4912450Sgabeblack@google.comfrom BranchPredictor import * 5012450Sgabeblack@google.com 5112450Sgabeblack@google.comclass FetchPolicy(ScopedEnum): 5212450Sgabeblack@google.com vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ] 5312450Sgabeblack@google.com 5412450Sgabeblack@google.comclass SMTQueuePolicy(ScopedEnum): 5512450Sgabeblack@google.com vals = [ 'Dynamic', 'Partitioned', 'Threshold' ] 5612450Sgabeblack@google.com 5712450Sgabeblack@google.comclass DerivO3CPU(BaseCPU): 5812450Sgabeblack@google.com type = 'DerivO3CPU' 5912465Sgabeblack@google.com cxx_header = 'cpu/o3/deriv.hh' 6012465Sgabeblack@google.com 6112465Sgabeblack@google.com @classmethod 6212465Sgabeblack@google.com def memory_mode(cls): 6312450Sgabeblack@google.com return 'timing' 6412465Sgabeblack@google.com 6512465Sgabeblack@google.com @classmethod 6612465Sgabeblack@google.com def require_caches(cls): 6712465Sgabeblack@google.com return True 6812465Sgabeblack@google.com 6912465Sgabeblack@google.com @classmethod 7012450Sgabeblack@google.com def support_take_over(cls): 7112465Sgabeblack@google.com return True 7212465Sgabeblack@google.com 7312465Sgabeblack@google.com activity = Param.Unsigned(0, "Initial count") 7412465Sgabeblack@google.com 7512465Sgabeblack@google.com cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 7612465Sgabeblack@google.com "Constrains stores only. Loads are constrained by load FUs.") 7712465Sgabeblack@google.com 7812450Sgabeblack@google.com decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 7912450Sgabeblack@google.com renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 8012450Sgabeblack@google.com iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 8112465Sgabeblack@google.com "delay") 8212465Sgabeblack@google.com commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 8312450Sgabeblack@google.com fetchWidth = Param.Unsigned(8, "Fetch width") 8412450Sgabeblack@google.com fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 8512450Sgabeblack@google.com fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 8612450Sgabeblack@google.com "per-thread") 8712450Sgabeblack@google.com 8812450Sgabeblack@google.com renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 8912450Sgabeblack@google.com iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 9012450Sgabeblack@google.com "delay") 9112450Sgabeblack@google.com commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 9212450Sgabeblack@google.com fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 9312450Sgabeblack@google.com decodeWidth = Param.Unsigned(8, "Decode width") 9412450Sgabeblack@google.com 9512450Sgabeblack@google.com iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 9612450Sgabeblack@google.com "delay") 9712450Sgabeblack@google.com commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 9812450Sgabeblack@google.com decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 9912450Sgabeblack@google.com renameWidth = Param.Unsigned(8, "Rename width") 10012450Sgabeblack@google.com 10112450Sgabeblack@google.com commitToIEWDelay = Param.Cycles(1, "Commit to " 10212450Sgabeblack@google.com "Issue/Execute/Writeback delay") 10312450Sgabeblack@google.com renameToIEWDelay = Param.Cycles(2, "Rename to " 10412450Sgabeblack@google.com "Issue/Execute/Writeback delay") 10512450Sgabeblack@google.com issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 10612450Sgabeblack@google.com "to the IEW stage)") 10712450Sgabeblack@google.com dispatchWidth = Param.Unsigned(8, "Dispatch width") 10812450Sgabeblack@google.com issueWidth = Param.Unsigned(8, "Issue width") 10912450Sgabeblack@google.com wbWidth = Param.Unsigned(8, "Writeback width") 11012450Sgabeblack@google.com fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 11112450Sgabeblack@google.com 11212450Sgabeblack@google.com iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 11312450Sgabeblack@google.com "delay") 11412450Sgabeblack@google.com renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 11512450Sgabeblack@google.com commitWidth = Param.Unsigned(8, "Commit width") 11612450Sgabeblack@google.com squashWidth = Param.Unsigned(8, "Squash width") 11712450Sgabeblack@google.com trapLatency = Param.Cycles(13, "Trap latency") 11812450Sgabeblack@google.com fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 11912450Sgabeblack@google.com 12012450Sgabeblack@google.com backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 12112450Sgabeblack@google.com forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 12212450Sgabeblack@google.com 12312450Sgabeblack@google.com LQEntries = Param.Unsigned(32, "Number of load queue entries") 12412450Sgabeblack@google.com SQEntries = Param.Unsigned(32, "Number of store queue entries") 12512450Sgabeblack@google.com LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 12612450Sgabeblack@google.com LSQCheckLoads = Param.Bool(True, 12712450Sgabeblack@google.com "Should dependency violations be checked for loads & stores or just stores") 12812450Sgabeblack@google.com store_set_clear_period = Param.Unsigned(250000, 12912450Sgabeblack@google.com "Number of load/store insts before the dep predictor should be invalidated") 13012450Sgabeblack@google.com LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 13112450Sgabeblack@google.com SSITSize = Param.Unsigned(1024, "Store set ID table size") 13212450Sgabeblack@google.com 13312450Sgabeblack@google.com numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 13412450Sgabeblack@google.com 13512450Sgabeblack@google.com numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 13612450Sgabeblack@google.com numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 13712450Sgabeblack@google.com "registers") 13812450Sgabeblack@google.com # most ISAs don't use condition-code regs, so default is 0 13912450Sgabeblack@google.com _defaultNumPhysCCRegs = 0 14012450Sgabeblack@google.com if buildEnv['TARGET_ISA'] in ('arm','x86'): 14112450Sgabeblack@google.com # For x86, each CC reg is used to hold only a subset of the 14212450Sgabeblack@google.com # flags, so we need 4-5 times the number of CC regs as 14312450Sgabeblack@google.com # physical integer regs to be sure we don't run out. In 14412450Sgabeblack@google.com # typical real machines, CC regs are not explicitly renamed 14512450Sgabeblack@google.com # (it's a side effect of int reg renaming), so they should 14612450Sgabeblack@google.com # never be the bottleneck here. 14712450Sgabeblack@google.com _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 14812450Sgabeblack@google.com numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 14912450Sgabeblack@google.com "registers") 15012450Sgabeblack@google.com numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 15112450Sgabeblack@google.com "Number of physical cc registers") 15212450Sgabeblack@google.com numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 15312450Sgabeblack@google.com numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 15412450Sgabeblack@google.com 1554680Sgblack@eecs.umich.edu smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 15612450Sgabeblack@google.com smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy") 1574680Sgblack@eecs.umich.edu smtLSQPolicy = Param.SMTQueuePolicy('Partitioned', 1584680Sgblack@eecs.umich.edu "SMT LSQ Sharing Policy") 15912450Sgabeblack@google.com smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 16012450Sgabeblack@google.com smtIQPolicy = Param.SMTQueuePolicy('Partitioned', 1614680Sgblack@eecs.umich.edu "SMT IQ Sharing Policy") 16212450Sgabeblack@google.com smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 16312450Sgabeblack@google.com smtROBPolicy = Param.SMTQueuePolicy('Partitioned', 16412450Sgabeblack@google.com "SMT ROB Sharing Policy") 1654680Sgblack@eecs.umich.edu smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 16612450Sgabeblack@google.com smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 16712450Sgabeblack@google.com 1684680Sgblack@eecs.umich.edu branchPred = Param.BranchPredictor(TournamentBP(numThreads = 16912450Sgabeblack@google.com Parent.numThreads), 1704680Sgblack@eecs.umich.edu "Branch Predictor") 1714680Sgblack@eecs.umich.edu needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 17212450Sgabeblack@google.com "Enable TSO Memory model") 17312450Sgabeblack@google.com 1744680Sgblack@eecs.umich.edu def addCheckerCpu(self): 17512450Sgabeblack@google.com if buildEnv['TARGET_ISA'] in ['arm']: 1764680Sgblack@eecs.umich.edu from ArmTLB import ArmTLB 1774680Sgblack@eecs.umich.edu 1784680Sgblack@eecs.umich.edu self.checker = O3Checker(workload=self.workload, 17912450Sgabeblack@google.com exitOnError=False, 18012450Sgabeblack@google.com updateOnError=True, 18112450Sgabeblack@google.com warnOnlyOnLoadError=True) 18212450Sgabeblack@google.com self.checker.itb = ArmTLB(size = self.itb.size) 18312450Sgabeblack@google.com self.checker.dtb = ArmTLB(size = self.dtb.size) 18412450Sgabeblack@google.com self.checker.cpu_id = self.cpu_id 18512450Sgabeblack@google.com 18612450Sgabeblack@google.com else: 18712450Sgabeblack@google.com print("ERROR: Checker only supported under ARM ISA!") 18812450Sgabeblack@google.com exit(1) 18912450Sgabeblack@google.com