O3CPU.py revision 13559:e9983a972327
16313Sgblack@eecs.umich.edu# Copyright (c) 2016, 2019 ARM Limited 26313Sgblack@eecs.umich.edu# All rights reserved. 36313Sgblack@eecs.umich.edu# 46313Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 56313Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 66313Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 76313Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 86313Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 96313Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 106313Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 116313Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 126313Sgblack@eecs.umich.edu# 136313Sgblack@eecs.umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 146313Sgblack@eecs.umich.edu# All rights reserved. 156313Sgblack@eecs.umich.edu# 166313Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 176313Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 186313Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 196313Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 206313Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 216313Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 226313Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 236313Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 246313Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 256313Sgblack@eecs.umich.edu# this software without specific prior written permission. 266313Sgblack@eecs.umich.edu# 276313Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 286313Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 296313Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 306313Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3111793Sbrandon.potter@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3211793Sbrandon.potter@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 337678Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 347678Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 356330Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 366313Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379384SAndreas.Sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 387680Sgblack@eecs.umich.edu# 396313Sgblack@eecs.umich.edu# Authors: Kevin Lim 406313Sgblack@eecs.umich.edu 416313Sgblack@eecs.umich.edufrom __future__ import print_function 426313Sgblack@eecs.umich.edu 439384SAndreas.Sandberg@arm.comfrom m5.defines import buildEnv 4410033SAli.Saidi@ARM.comfrom m5.params import * 459384SAndreas.Sandberg@arm.comfrom m5.proxy import * 469384SAndreas.Sandberg@arm.comfrom BaseCPU import BaseCPU 479384SAndreas.Sandberg@arm.comfrom FUPool import * 489384SAndreas.Sandberg@arm.comfrom O3Checker import O3Checker 499384SAndreas.Sandberg@arm.comfrom BranchPredictor import * 509384SAndreas.Sandberg@arm.com 519384SAndreas.Sandberg@arm.comclass FetchPolicy(ScopedEnum): 529384SAndreas.Sandberg@arm.com vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ] 539384SAndreas.Sandberg@arm.com 549384SAndreas.Sandberg@arm.comclass DerivO3CPU(BaseCPU): 559384SAndreas.Sandberg@arm.com type = 'DerivO3CPU' 566313Sgblack@eecs.umich.edu cxx_header = 'cpu/o3/deriv.hh' 5710905Sandreas.sandberg@arm.com 586313Sgblack@eecs.umich.edu @classmethod 596330Sgblack@eecs.umich.edu def memory_mode(cls): 606330Sgblack@eecs.umich.edu return 'timing' 616330Sgblack@eecs.umich.edu 626330Sgblack@eecs.umich.edu @classmethod 636330Sgblack@eecs.umich.edu def require_caches(cls): 646313Sgblack@eecs.umich.edu return True 656313Sgblack@eecs.umich.edu 666313Sgblack@eecs.umich.edu @classmethod 6710905Sandreas.sandberg@arm.com def support_take_over(cls): 686313Sgblack@eecs.umich.edu return True 696330Sgblack@eecs.umich.edu 706330Sgblack@eecs.umich.edu activity = Param.Unsigned(0, "Initial count") 716330Sgblack@eecs.umich.edu 726330Sgblack@eecs.umich.edu cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 736330Sgblack@eecs.umich.edu "Constrains stores only. Loads are constrained by load FUs.") 746330Sgblack@eecs.umich.edu 756330Sgblack@eecs.umich.edu decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 766330Sgblack@eecs.umich.edu renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 776330Sgblack@eecs.umich.edu iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 7810698Sandreas.hansson@arm.com "delay") 796330Sgblack@eecs.umich.edu commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 806330Sgblack@eecs.umich.edu fetchWidth = Param.Unsigned(8, "Fetch width") 816330Sgblack@eecs.umich.edu fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 826330Sgblack@eecs.umich.edu fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 836330Sgblack@eecs.umich.edu "per-thread") 846330Sgblack@eecs.umich.edu 856330Sgblack@eecs.umich.edu renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 866330Sgblack@eecs.umich.edu iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 876330Sgblack@eecs.umich.edu "delay") 886330Sgblack@eecs.umich.edu commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 896330Sgblack@eecs.umich.edu fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 906330Sgblack@eecs.umich.edu decodeWidth = Param.Unsigned(8, "Decode width") 916330Sgblack@eecs.umich.edu 926330Sgblack@eecs.umich.edu iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 936330Sgblack@eecs.umich.edu "delay") 946330Sgblack@eecs.umich.edu commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 956330Sgblack@eecs.umich.edu decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 966330Sgblack@eecs.umich.edu renameWidth = Param.Unsigned(8, "Rename width") 976330Sgblack@eecs.umich.edu 986330Sgblack@eecs.umich.edu commitToIEWDelay = Param.Cycles(1, "Commit to " 996330Sgblack@eecs.umich.edu "Issue/Execute/Writeback delay") 1006330Sgblack@eecs.umich.edu renameToIEWDelay = Param.Cycles(2, "Rename to " 1016330Sgblack@eecs.umich.edu "Issue/Execute/Writeback delay") 1026330Sgblack@eecs.umich.edu issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 1036330Sgblack@eecs.umich.edu "to the IEW stage)") 1046330Sgblack@eecs.umich.edu dispatchWidth = Param.Unsigned(8, "Dispatch width") 1056330Sgblack@eecs.umich.edu issueWidth = Param.Unsigned(8, "Issue width") 1066330Sgblack@eecs.umich.edu wbWidth = Param.Unsigned(8, "Writeback width") 1076330Sgblack@eecs.umich.edu fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 1086330Sgblack@eecs.umich.edu 1096330Sgblack@eecs.umich.edu iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 1106330Sgblack@eecs.umich.edu "delay") 1116330Sgblack@eecs.umich.edu renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 1126330Sgblack@eecs.umich.edu commitWidth = Param.Unsigned(8, "Commit width") 1136330Sgblack@eecs.umich.edu squashWidth = Param.Unsigned(8, "Squash width") 1146330Sgblack@eecs.umich.edu trapLatency = Param.Cycles(13, "Trap latency") 1156330Sgblack@eecs.umich.edu fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 1166330Sgblack@eecs.umich.edu 1176330Sgblack@eecs.umich.edu backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 1186330Sgblack@eecs.umich.edu forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1196330Sgblack@eecs.umich.edu 1206330Sgblack@eecs.umich.edu LQEntries = Param.Unsigned(32, "Number of load queue entries") 1216330Sgblack@eecs.umich.edu SQEntries = Param.Unsigned(32, "Number of store queue entries") 1226330Sgblack@eecs.umich.edu LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1236330Sgblack@eecs.umich.edu LSQCheckLoads = Param.Bool(True, 1246330Sgblack@eecs.umich.edu "Should dependency violations be checked for loads & stores or just stores") 1256330Sgblack@eecs.umich.edu store_set_clear_period = Param.Unsigned(250000, 1266330Sgblack@eecs.umich.edu "Number of load/store insts before the dep predictor should be invalidated") 1276330Sgblack@eecs.umich.edu LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1286330Sgblack@eecs.umich.edu SSITSize = Param.Unsigned(1024, "Store set ID table size") 1296330Sgblack@eecs.umich.edu 1306330Sgblack@eecs.umich.edu numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1316330Sgblack@eecs.umich.edu 1326330Sgblack@eecs.umich.edu numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1336330Sgblack@eecs.umich.edu numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1346330Sgblack@eecs.umich.edu "registers") 1356330Sgblack@eecs.umich.edu # most ISAs don't use condition-code regs, so default is 0 1366330Sgblack@eecs.umich.edu _defaultNumPhysCCRegs = 0 1376330Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ('arm','x86'): 1386330Sgblack@eecs.umich.edu # For x86, each CC reg is used to hold only a subset of the 1396330Sgblack@eecs.umich.edu # flags, so we need 4-5 times the number of CC regs as 1406330Sgblack@eecs.umich.edu # physical integer regs to be sure we don't run out. In 1416330Sgblack@eecs.umich.edu # typical real machines, CC regs are not explicitly renamed 1426330Sgblack@eecs.umich.edu # (it's a side effect of int reg renaming), so they should 1436330Sgblack@eecs.umich.edu # never be the bottleneck here. 1446330Sgblack@eecs.umich.edu _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 1456330Sgblack@eecs.umich.edu numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 1466330Sgblack@eecs.umich.edu "registers") 1476330Sgblack@eecs.umich.edu numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 1486330Sgblack@eecs.umich.edu "Number of physical cc registers") 1496330Sgblack@eecs.umich.edu numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 1506330Sgblack@eecs.umich.edu numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 1516330Sgblack@eecs.umich.edu 1526330Sgblack@eecs.umich.edu smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 1536330Sgblack@eecs.umich.edu smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy") 1546330Sgblack@eecs.umich.edu smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 1556330Sgblack@eecs.umich.edu smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 1566330Sgblack@eecs.umich.edu smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 1576330Sgblack@eecs.umich.edu smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 1586330Sgblack@eecs.umich.edu smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 1596330Sgblack@eecs.umich.edu smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 1606330Sgblack@eecs.umich.edu smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 1616330Sgblack@eecs.umich.edu 1626330Sgblack@eecs.umich.edu branchPred = Param.BranchPredictor(TournamentBP(numThreads = 1636330Sgblack@eecs.umich.edu Parent.numThreads), 1646330Sgblack@eecs.umich.edu "Branch Predictor") 1656330Sgblack@eecs.umich.edu needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 1666313Sgblack@eecs.umich.edu "Enable TSO Memory model") 1676313Sgblack@eecs.umich.edu 1686313Sgblack@eecs.umich.edu def addCheckerCpu(self): 1699384SAndreas.Sandberg@arm.com if buildEnv['TARGET_ISA'] in ['arm']: 1709384SAndreas.Sandberg@arm.com from ArmTLB import ArmTLB 1719384SAndreas.Sandberg@arm.com 1729384SAndreas.Sandberg@arm.com self.checker = O3Checker(workload=self.workload, 1739384SAndreas.Sandberg@arm.com exitOnError=False, 1749384SAndreas.Sandberg@arm.com updateOnError=True, 175 warnOnlyOnLoadError=True) 176 self.checker.itb = ArmTLB(size = self.itb.size) 177 self.checker.dtb = ArmTLB(size = self.dtb.size) 178 self.checker.cpu_id = self.cpu_id 179 180 else: 181 print("ERROR: Checker only supported under ARM ISA!") 182 exit(1) 183