O3CPU.py revision 13559 
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39# Authors: Kevin Lim
40
41from __future__ import print_function
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from BaseCPU import BaseCPU
47from FUPool import *
48from O3Checker import O3Checker
49from BranchPredictor import *
50
51class FetchPolicy(ScopedEnum):
52    vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
53
54class DerivO3CPU(BaseCPU):
55    type = 'DerivO3CPU'
56    cxx_header = 'cpu/o3/deriv.hh'
57
58    @classmethod
59    def memory_mode(cls):
60        return 'timing'
61
62    @classmethod
63    def require_caches(cls):
64        return True
65
66    @classmethod
67    def support_take_over(cls):
68        return True
69
70    activity = Param.Unsigned(0, "Initial count")
71
72    cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
73          "Constrains stores only. Loads are constrained by load FUs.")
74
75    decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
76    renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
77    iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
78                                   "delay")
79    commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
80    fetchWidth = Param.Unsigned(8, "Fetch width")
81    fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
82    fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
83                                    "per-thread")
84
85    renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
86    iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
87                                    "delay")
88    commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
89    fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
90    decodeWidth = Param.Unsigned(8, "Decode width")
91
92    iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
93                                    "delay")
94    commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
95    decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
96    renameWidth = Param.Unsigned(8, "Rename width")
97
98    commitToIEWDelay = Param.Cycles(1, "Commit to "
99               "Issue/Execute/Writeback delay")
100    renameToIEWDelay = Param.Cycles(2, "Rename to "
101               "Issue/Execute/Writeback delay")
102    issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
103              "to the IEW stage)")
104    dispatchWidth = Param.Unsigned(8, "Dispatch width")
105    issueWidth = Param.Unsigned(8, "Issue width")
106    wbWidth = Param.Unsigned(8, "Writeback width")
107    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
108
109    iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
110               "delay")
111    renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
112    commitWidth = Param.Unsigned(8, "Commit width")
113    squashWidth = Param.Unsigned(8, "Squash width")
114    trapLatency = Param.Cycles(13, "Trap latency")
115    fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
116
117    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
118    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
119
120    LQEntries = Param.Unsigned(32, "Number of load queue entries")
121    SQEntries = Param.Unsigned(32, "Number of store queue entries")
122    LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
123    LSQCheckLoads = Param.Bool(True,
124        "Should dependency violations be checked for loads & stores or just stores")
125    store_set_clear_period = Param.Unsigned(250000,
126            "Number of load/store insts before the dep predictor should be invalidated")
127    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
128    SSITSize = Param.Unsigned(1024, "Store set ID table size")
129
130    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
131
132    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
133    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
134                                      "registers")
135    # most ISAs don't use condition-code regs, so default is 0
136    _defaultNumPhysCCRegs = 0
137    if buildEnv['TARGET_ISA'] in ('arm','x86'):
138        # For x86, each CC reg is used to hold only a subset of the
139        # flags, so we need 4-5 times the number of CC regs as
140        # physical integer regs to be sure we don't run out.  In
141        # typical real machines, CC regs are not explicitly renamed
142        # (it's a side effect of int reg renaming), so they should
143        # never be the bottleneck here.
144        _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
145    numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
146                                      "registers")
147    numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
148                                   "Number of physical cc registers")
149    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
150    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
151
152    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
153    smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy")
154    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
155    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
156    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
157    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
158    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
159    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
160    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
161
162    branchPred = Param.BranchPredictor(TournamentBP(numThreads =
163                                                       Parent.numThreads),
164                                       "Branch Predictor")
165    needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
166                          "Enable TSO Memory model")
167
168    def addCheckerCpu(self):
169        if buildEnv['TARGET_ISA'] in ['arm']:
170            from ArmTLB import ArmTLB
171
172            self.checker = O3Checker(workload=self.workload,
173                                     exitOnError=False,
174                                     updateOnError=True,
175                                     warnOnlyOnLoadError=True)
176            self.checker.itb = ArmTLB(size = self.itb.size)
177            self.checker.dtb = ArmTLB(size = self.dtb.size)
178            self.checker.cpu_id = self.cpu_id
179
180        else:
181            print("ERROR: Checker only supported under ARM ISA!")
182            exit(1)
183