O3CPU.py revision 12563:8d59ed22ae79
112837Sgabeblack@google.com# Copyright (c) 2016 ARM Limited 212837Sgabeblack@google.com# All rights reserved. 312837Sgabeblack@google.com# 412837Sgabeblack@google.com# The license below extends only to copyright in the software and shall 512837Sgabeblack@google.com# not be construed as granting a license to any other intellectual 612837Sgabeblack@google.com# property including but not limited to intellectual property relating 712837Sgabeblack@google.com# to a hardware implementation of the functionality of the software 812837Sgabeblack@google.com# licensed hereunder. You may use the software subject to the license 912837Sgabeblack@google.com# terms below provided that you ensure that this notice is replicated 1012837Sgabeblack@google.com# unmodified and in its entirety in all distributions of the software, 1112837Sgabeblack@google.com# modified or unmodified, in source code or in binary form. 1212837Sgabeblack@google.com# 1312837Sgabeblack@google.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 1412837Sgabeblack@google.com# All rights reserved. 1512837Sgabeblack@google.com# 1612837Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 1712837Sgabeblack@google.com# modification, are permitted provided that the following conditions are 1812837Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 1912837Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 2012837Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 2112837Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 2212837Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 2312837Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 2412837Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 2512837Sgabeblack@google.com# this software without specific prior written permission. 2612837Sgabeblack@google.com# 2712837Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2812837Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2912837Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3012901Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3113135Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3212901Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3312901Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3412837Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3513280Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3612982Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3712951Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3813280Sgabeblack@google.com# 3913288Sgabeblack@google.com# Authors: Kevin Lim 4012953Sgabeblack@google.com 4113260Sgabeblack@google.comfrom __future__ import print_function 4213288Sgabeblack@google.com 4313288Sgabeblack@google.comfrom m5.defines import buildEnv 4413288Sgabeblack@google.comfrom m5.params import * 4513155Sgabeblack@google.comfrom m5.proxy import * 4612837Sgabeblack@google.comfrom BaseCPU import BaseCPU 4712951Sgabeblack@google.comfrom FUPool import * 4813155Sgabeblack@google.comfrom O3Checker import O3Checker 4913135Sgabeblack@google.comfrom BranchPredictor import * 5012837Sgabeblack@google.com 5112952Sgabeblack@google.comclass DerivO3CPU(BaseCPU): 5212952Sgabeblack@google.com type = 'DerivO3CPU' 5312952Sgabeblack@google.com cxx_header = 'cpu/o3/deriv.hh' 5412952Sgabeblack@google.com 5512952Sgabeblack@google.com @classmethod 5612952Sgabeblack@google.com def memory_mode(cls): 5713135Sgabeblack@google.com return 'timing' 5813135Sgabeblack@google.com 5913135Sgabeblack@google.com @classmethod 6013135Sgabeblack@google.com def require_caches(cls): 6113135Sgabeblack@google.com return True 6213135Sgabeblack@google.com 6313135Sgabeblack@google.com @classmethod 6413135Sgabeblack@google.com def support_take_over(cls): 6512993Sgabeblack@google.com return True 6612993Sgabeblack@google.com 6712952Sgabeblack@google.com activity = Param.Unsigned(0, "Initial count") 6812952Sgabeblack@google.com 6912952Sgabeblack@google.com cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 7012952Sgabeblack@google.com "Constrains stores only. Loads are constrained by load FUs.") 7112952Sgabeblack@google.com 7213135Sgabeblack@google.com decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 7313135Sgabeblack@google.com renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 7413135Sgabeblack@google.com iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 7513135Sgabeblack@google.com "delay") 7613135Sgabeblack@google.com commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 7713135Sgabeblack@google.com fetchWidth = Param.Unsigned(8, "Fetch width") 7813135Sgabeblack@google.com fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 7913135Sgabeblack@google.com fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 8012993Sgabeblack@google.com "per-thread") 8112993Sgabeblack@google.com 8212952Sgabeblack@google.com renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 8312952Sgabeblack@google.com iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 8412952Sgabeblack@google.com "delay") 8512952Sgabeblack@google.com commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 8612952Sgabeblack@google.com fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 8713135Sgabeblack@google.com decodeWidth = Param.Unsigned(8, "Decode width") 8813135Sgabeblack@google.com 8913135Sgabeblack@google.com iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 9013135Sgabeblack@google.com "delay") 9113135Sgabeblack@google.com commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 9213135Sgabeblack@google.com decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 9313135Sgabeblack@google.com renameWidth = Param.Unsigned(8, "Rename width") 9413135Sgabeblack@google.com 9512993Sgabeblack@google.com commitToIEWDelay = Param.Cycles(1, "Commit to " 9613194Sgabeblack@google.com "Issue/Execute/Writeback delay") 9712993Sgabeblack@google.com renameToIEWDelay = Param.Cycles(2, "Rename to " 9812952Sgabeblack@google.com "Issue/Execute/Writeback delay") 9912952Sgabeblack@google.com issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 10012952Sgabeblack@google.com "to the IEW stage)") 10112952Sgabeblack@google.com dispatchWidth = Param.Unsigned(8, "Dispatch width") 10212837Sgabeblack@google.com issueWidth = Param.Unsigned(8, "Issue width") 10312837Sgabeblack@google.com wbWidth = Param.Unsigned(8, "Writeback width") 10412837Sgabeblack@google.com fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 10513091Sgabeblack@google.com 10612951Sgabeblack@google.com iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 10712951Sgabeblack@google.com "delay") 10812837Sgabeblack@google.com renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 10913091Sgabeblack@google.com commitWidth = Param.Unsigned(8, "Commit width") 11012951Sgabeblack@google.com squashWidth = Param.Unsigned(8, "Squash width") 11112951Sgabeblack@google.com trapLatency = Param.Cycles(13, "Trap latency") 11212837Sgabeblack@google.com fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 11313091Sgabeblack@google.com 11412837Sgabeblack@google.com backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 11512982Sgabeblack@google.com forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 11612837Sgabeblack@google.com 11713091Sgabeblack@google.com LQEntries = Param.Unsigned(32, "Number of load queue entries") 11812837Sgabeblack@google.com SQEntries = Param.Unsigned(32, "Number of store queue entries") 11912837Sgabeblack@google.com LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 12012837Sgabeblack@google.com LSQCheckLoads = Param.Bool(True, 12112837Sgabeblack@google.com "Should dependency violations be checked for loads & stores or just stores") 12212837Sgabeblack@google.com store_set_clear_period = Param.Unsigned(250000, 12312837Sgabeblack@google.com "Number of load/store insts before the dep predictor should be invalidated") 12412837Sgabeblack@google.com LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 12512837Sgabeblack@google.com SSITSize = Param.Unsigned(1024, "Store set ID table size") 12612837Sgabeblack@google.com 12712837Sgabeblack@google.com numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 12812837Sgabeblack@google.com 12912837Sgabeblack@google.com numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 13012837Sgabeblack@google.com numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 13112837Sgabeblack@google.com "registers") 13212837Sgabeblack@google.com # most ISAs don't use condition-code regs, so default is 0 13312837Sgabeblack@google.com _defaultNumPhysCCRegs = 0 13412837Sgabeblack@google.com if buildEnv['TARGET_ISA'] in ('arm','x86'): 13512837Sgabeblack@google.com # For x86, each CC reg is used to hold only a subset of the 13612837Sgabeblack@google.com # flags, so we need 4-5 times the number of CC regs as 13712837Sgabeblack@google.com # physical integer regs to be sure we don't run out. In 13812837Sgabeblack@google.com # typical real machines, CC regs are not explicitly renamed 13912837Sgabeblack@google.com # (it's a side effect of int reg renaming), so they should 14012837Sgabeblack@google.com # never be the bottleneck here. 14112837Sgabeblack@google.com _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 14212837Sgabeblack@google.com numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 14312837Sgabeblack@google.com "registers") 14412837Sgabeblack@google.com numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 14512837Sgabeblack@google.com "Number of physical cc registers") 14612837Sgabeblack@google.com numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 14712837Sgabeblack@google.com numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 14812837Sgabeblack@google.com 14912837Sgabeblack@google.com smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 15012837Sgabeblack@google.com smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 15112837Sgabeblack@google.com smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 15212837Sgabeblack@google.com smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 15312837Sgabeblack@google.com smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 15412837Sgabeblack@google.com smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 15512837Sgabeblack@google.com smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 15612837Sgabeblack@google.com smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 15712837Sgabeblack@google.com smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 15812837Sgabeblack@google.com 15912837Sgabeblack@google.com branchPred = Param.BranchPredictor(TournamentBP(numThreads = 16012837Sgabeblack@google.com Parent.numThreads), 16112837Sgabeblack@google.com "Branch Predictor") 16212837Sgabeblack@google.com needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 16312837Sgabeblack@google.com "Enable TSO Memory model") 16412837Sgabeblack@google.com 16512837Sgabeblack@google.com def addCheckerCpu(self): 16612837Sgabeblack@google.com if buildEnv['TARGET_ISA'] in ['arm']: 16712837Sgabeblack@google.com from ArmTLB import ArmTLB 16812837Sgabeblack@google.com 16912837Sgabeblack@google.com self.checker = O3Checker(workload=self.workload, 17012837Sgabeblack@google.com exitOnError=False, 17112837Sgabeblack@google.com updateOnError=True, 17212837Sgabeblack@google.com warnOnlyOnLoadError=True) 17312837Sgabeblack@google.com self.checker.itb = ArmTLB(size = self.itb.size) 17412837Sgabeblack@google.com self.checker.dtb = ArmTLB(size = self.dtb.size) 17512837Sgabeblack@google.com self.checker.cpu_id = self.cpu_id 17612837Sgabeblack@google.com 17712837Sgabeblack@google.com else: 17812837Sgabeblack@google.com print("ERROR: Checker only supported under ARM ISA!") 17912837Sgabeblack@google.com exit(1) 18012837Sgabeblack@google.com