O3CPU.py revision 12563 
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39# Authors: Kevin Lim
40
41from __future__ import print_function
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from BaseCPU import BaseCPU
47from FUPool import *
48from O3Checker import O3Checker
49from BranchPredictor import *
50
51class DerivO3CPU(BaseCPU):
52    type = 'DerivO3CPU'
53    cxx_header = 'cpu/o3/deriv.hh'
54
55    @classmethod
56    def memory_mode(cls):
57        return 'timing'
58
59    @classmethod
60    def require_caches(cls):
61        return True
62
63    @classmethod
64    def support_take_over(cls):
65        return True
66
67    activity = Param.Unsigned(0, "Initial count")
68
69    cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
70          "Constrains stores only. Loads are constrained by load FUs.")
71
72    decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
73    renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
74    iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
75                                   "delay")
76    commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
77    fetchWidth = Param.Unsigned(8, "Fetch width")
78    fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
79    fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
80                                    "per-thread")
81
82    renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
83    iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
84                                    "delay")
85    commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
86    fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
87    decodeWidth = Param.Unsigned(8, "Decode width")
88
89    iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
90                                    "delay")
91    commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
92    decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
93    renameWidth = Param.Unsigned(8, "Rename width")
94
95    commitToIEWDelay = Param.Cycles(1, "Commit to "
96               "Issue/Execute/Writeback delay")
97    renameToIEWDelay = Param.Cycles(2, "Rename to "
98               "Issue/Execute/Writeback delay")
99    issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
100              "to the IEW stage)")
101    dispatchWidth = Param.Unsigned(8, "Dispatch width")
102    issueWidth = Param.Unsigned(8, "Issue width")
103    wbWidth = Param.Unsigned(8, "Writeback width")
104    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
105
106    iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
107               "delay")
108    renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
109    commitWidth = Param.Unsigned(8, "Commit width")
110    squashWidth = Param.Unsigned(8, "Squash width")
111    trapLatency = Param.Cycles(13, "Trap latency")
112    fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
113
114    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
115    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
116
117    LQEntries = Param.Unsigned(32, "Number of load queue entries")
118    SQEntries = Param.Unsigned(32, "Number of store queue entries")
119    LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
120    LSQCheckLoads = Param.Bool(True,
121        "Should dependency violations be checked for loads & stores or just stores")
122    store_set_clear_period = Param.Unsigned(250000,
123            "Number of load/store insts before the dep predictor should be invalidated")
124    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
125    SSITSize = Param.Unsigned(1024, "Store set ID table size")
126
127    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
128
129    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
130    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
131                                      "registers")
132    # most ISAs don't use condition-code regs, so default is 0
133    _defaultNumPhysCCRegs = 0
134    if buildEnv['TARGET_ISA'] in ('arm','x86'):
135        # For x86, each CC reg is used to hold only a subset of the
136        # flags, so we need 4-5 times the number of CC regs as
137        # physical integer regs to be sure we don't run out.  In
138        # typical real machines, CC regs are not explicitly renamed
139        # (it's a side effect of int reg renaming), so they should
140        # never be the bottleneck here.
141        _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
142    numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
143                                      "registers")
144    numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
145                                   "Number of physical cc registers")
146    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
147    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
148
149    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
150    smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
151    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
152    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
153    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
154    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
155    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
156    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
157    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
158
159    branchPred = Param.BranchPredictor(TournamentBP(numThreads =
160                                                       Parent.numThreads),
161                                       "Branch Predictor")
162    needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
163                          "Enable TSO Memory model")
164
165    def addCheckerCpu(self):
166        if buildEnv['TARGET_ISA'] in ['arm']:
167            from ArmTLB import ArmTLB
168
169            self.checker = O3Checker(workload=self.workload,
170                                     exitOnError=False,
171                                     updateOnError=True,
172                                     warnOnlyOnLoadError=True)
173            self.checker.itb = ArmTLB(size = self.itb.size)
174            self.checker.dtb = ArmTLB(size = self.dtb.size)
175            self.checker.cpu_id = self.cpu_id
176
177        else:
178            print("ERROR: Checker only supported under ARM ISA!")
179            exit(1)
180