O3CPU.py revision 11780
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Kevin Lim 28 29from m5.defines import buildEnv 30from m5.params import * 31from m5.proxy import * 32from BaseCPU import BaseCPU 33from FUPool import * 34from O3Checker import O3Checker 35from BranchPredictor import * 36 37class DerivO3CPU(BaseCPU): 38 type = 'DerivO3CPU' 39 cxx_header = 'cpu/o3/deriv.hh' 40 41 @classmethod 42 def memory_mode(cls): 43 return 'timing' 44 45 @classmethod 46 def require_caches(cls): 47 return True 48 49 @classmethod 50 def support_take_over(cls): 51 return True 52 53 activity = Param.Unsigned(0, "Initial count") 54 55 cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 56 "Constrains stores only. Loads are constrained by load FUs.") 57 58 decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 59 renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 60 iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 61 "delay") 62 commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 63 fetchWidth = Param.Unsigned(8, "Fetch width") 64 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 65 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 66 "per-thread") 67 68 renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 69 iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 70 "delay") 71 commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 72 fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 73 decodeWidth = Param.Unsigned(8, "Decode width") 74 75 iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 76 "delay") 77 commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 78 decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 79 renameWidth = Param.Unsigned(8, "Rename width") 80 81 commitToIEWDelay = Param.Cycles(1, "Commit to " 82 "Issue/Execute/Writeback delay") 83 renameToIEWDelay = Param.Cycles(2, "Rename to " 84 "Issue/Execute/Writeback delay") 85 issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 86 "to the IEW stage)") 87 dispatchWidth = Param.Unsigned(8, "Dispatch width") 88 issueWidth = Param.Unsigned(8, "Issue width") 89 wbWidth = Param.Unsigned(8, "Writeback width") 90 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 91 92 iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 93 "delay") 94 renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 95 commitWidth = Param.Unsigned(8, "Commit width") 96 squashWidth = Param.Unsigned(8, "Squash width") 97 trapLatency = Param.Cycles(13, "Trap latency") 98 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 99 100 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 101 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 102 103 LQEntries = Param.Unsigned(32, "Number of load queue entries") 104 SQEntries = Param.Unsigned(32, "Number of store queue entries") 105 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 106 LSQCheckLoads = Param.Bool(True, 107 "Should dependency violations be checked for loads & stores or just stores") 108 store_set_clear_period = Param.Unsigned(250000, 109 "Number of load/store insts before the dep predictor should be invalidated") 110 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 111 SSITSize = Param.Unsigned(1024, "Store set ID table size") 112 113 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 114 115 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 116 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 117 "registers") 118 # most ISAs don't use condition-code regs, so default is 0 119 _defaultNumPhysCCRegs = 0 120 if buildEnv['TARGET_ISA'] in ('arm','x86'): 121 # For x86, each CC reg is used to hold only a subset of the 122 # flags, so we need 4-5 times the number of CC regs as 123 # physical integer regs to be sure we don't run out. In 124 # typical real machines, CC regs are not explicitly renamed 125 # (it's a side effect of int reg renaming), so they should 126 # never be the bottleneck here. 127 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 128 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 129 "Number of physical cc registers") 130 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 131 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 132 133 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 134 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 135 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 136 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 137 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 138 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 139 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 140 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 141 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 142 143 branchPred = Param.BranchPredictor(TournamentBP(numThreads = 144 Parent.numThreads), 145 "Branch Predictor") 146 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 147 "Enable TSO Memory model") 148 149 def addCheckerCpu(self): 150 if buildEnv['TARGET_ISA'] in ['arm']: 151 from ArmTLB import ArmTLB 152 153 self.checker = O3Checker(workload=self.workload, 154 exitOnError=False, 155 updateOnError=True, 156 warnOnlyOnLoadError=True) 157 self.checker.itb = ArmTLB(size = self.itb.size) 158 self.checker.dtb = ArmTLB(size = self.dtb.size) 159 self.checker.cpu_id = self.cpu_id 160 161 else: 162 print "ERROR: Checker only supported under ARM ISA!" 163 exit(1) 164