O3CPU.py revision 9982
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Kevin Lim 284486Sbinkertn@umich.edu 296654Snate@binkert.orgfrom m5.defines import buildEnv 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 321681SN/Afrom BaseCPU import BaseCPU 333223SN/Afrom FUPool import * 348887Sgeoffrey.blake@arm.comfrom O3Checker import O3Checker 359480Snilay@cs.wisc.edufrom BranchPredictor import BranchPredictor 364486Sbinkertn@umich.edu 372817SN/Aclass DerivO3CPU(BaseCPU): 382817SN/A type = 'DerivO3CPU' 399341SAndreas.Sandberg@arm.com cxx_header = 'cpu/o3/deriv.hh' 409341SAndreas.Sandberg@arm.com 419518SAndreas.Sandberg@ARM.com @classmethod 429518SAndreas.Sandberg@ARM.com def memory_mode(cls): 439518SAndreas.Sandberg@ARM.com return 'timing' 449518SAndreas.Sandberg@ARM.com 459518SAndreas.Sandberg@ARM.com @classmethod 469518SAndreas.Sandberg@ARM.com def require_caches(cls): 479518SAndreas.Sandberg@ARM.com return True 489518SAndreas.Sandberg@ARM.com 499518SAndreas.Sandberg@ARM.com @classmethod 509518SAndreas.Sandberg@ARM.com def support_take_over(cls): 519518SAndreas.Sandberg@ARM.com return True 529518SAndreas.Sandberg@ARM.com 532932SN/A activity = Param.Unsigned(0, "Initial count") 541681SN/A 554597Sbinkertn@umich.edu cachePorts = Param.Unsigned(200, "Cache Ports") 561681SN/A 579184Sandreas.hansson@arm.com decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 589184Sandreas.hansson@arm.com renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 599184Sandreas.hansson@arm.com iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 609184Sandreas.hansson@arm.com "delay") 619184Sandreas.hansson@arm.com commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 622932SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 639982Satgutier@umich.edu fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 642932SN/A 659184Sandreas.hansson@arm.com renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 669184Sandreas.hansson@arm.com iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 679184Sandreas.hansson@arm.com "delay") 689184Sandreas.hansson@arm.com commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 699184Sandreas.hansson@arm.com fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 702932SN/A decodeWidth = Param.Unsigned(8, "Decode width") 711681SN/A 729184Sandreas.hansson@arm.com iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 739184Sandreas.hansson@arm.com "delay") 749184Sandreas.hansson@arm.com commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 759184Sandreas.hansson@arm.com decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 762932SN/A renameWidth = Param.Unsigned(8, "Rename width") 771681SN/A 789184Sandreas.hansson@arm.com commitToIEWDelay = Param.Cycles(1, "Commit to " 792932SN/A "Issue/Execute/Writeback delay") 809184Sandreas.hansson@arm.com renameToIEWDelay = Param.Cycles(2, "Rename to " 812932SN/A "Issue/Execute/Writeback delay") 829184Sandreas.hansson@arm.com issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 832932SN/A "to the IEW stage)") 842932SN/A dispatchWidth = Param.Unsigned(8, "Dispatch width") 852932SN/A issueWidth = Param.Unsigned(8, "Issue width") 862932SN/A wbWidth = Param.Unsigned(8, "Writeback width") 872932SN/A wbDepth = Param.Unsigned(1, "Writeback depth") 883223SN/A fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 892932SN/A 909184Sandreas.hansson@arm.com iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 911681SN/A "delay") 929184Sandreas.hansson@arm.com renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 932932SN/A commitWidth = Param.Unsigned(8, "Commit width") 942932SN/A squashWidth = Param.Unsigned(8, "Squash width") 959184Sandreas.hansson@arm.com trapLatency = Param.Cycles(13, "Trap latency") 969184Sandreas.hansson@arm.com fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 971681SN/A 982932SN/A backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 992932SN/A forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1001681SN/A 1012932SN/A LQEntries = Param.Unsigned(32, "Number of load queue entries") 1022932SN/A SQEntries = Param.Unsigned(32, "Number of store queue entries") 1038199SAli.Saidi@ARM.com LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1048199SAli.Saidi@ARM.com LSQCheckLoads = Param.Bool(True, 1058199SAli.Saidi@ARM.com "Should dependency violations be checked for loads & stores or just stores") 1068519SAli.Saidi@ARM.com store_set_clear_period = Param.Unsigned(250000, 1078519SAli.Saidi@ARM.com "Number of load/store insts before the dep predictor should be invalidated") 1082932SN/A LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1092932SN/A SSITSize = Param.Unsigned(1024, "Store set ID table size") 1101681SN/A 1112932SN/A numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1121681SN/A 1132932SN/A numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1142932SN/A numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1152932SN/A "registers") 1169921Syasuko.eckert@amd.com # most ISAs don't use condition-code regs, so default is 0 1179921Syasuko.eckert@amd.com _defaultNumPhysCCRegs = 0 1189921Syasuko.eckert@amd.com if buildEnv['TARGET_ISA'] == 'x86': 1199921Syasuko.eckert@amd.com # For x86, each CC reg is used to hold only a subset of the 1209921Syasuko.eckert@amd.com # flags, so we need 4-5 times the number of CC regs as 1219921Syasuko.eckert@amd.com # physical integer regs to be sure we don't run out. In 1229921Syasuko.eckert@amd.com # typical real machines, CC regs are not explicitly renamed 1239921Syasuko.eckert@amd.com # (it's a side effect of int reg renaming), so they should 1249921Syasuko.eckert@amd.com # never be the bottleneck here. 1259921Syasuko.eckert@amd.com _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 1269921Syasuko.eckert@amd.com numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 1279921Syasuko.eckert@amd.com "Number of physical cc registers") 1282932SN/A numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 1292932SN/A numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 1301681SN/A 1314597Sbinkertn@umich.edu smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 1324597Sbinkertn@umich.edu smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 1334597Sbinkertn@umich.edu smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 1344597Sbinkertn@umich.edu smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 1354597Sbinkertn@umich.edu smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 1364597Sbinkertn@umich.edu smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 1374597Sbinkertn@umich.edu smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 1384597Sbinkertn@umich.edu smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 1394597Sbinkertn@umich.edu smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 1404303SN/A 1419849Sandreas.hansson@arm.com branchPred = Param.BranchPredictor(BranchPredictor(numThreads = 1429849Sandreas.hansson@arm.com Parent.numThreads), 1439849Sandreas.hansson@arm.com "Branch Predictor") 1448727Snilay@cs.wisc.edu needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 1458727Snilay@cs.wisc.edu "Enable TSO Memory model") 1468887Sgeoffrey.blake@arm.com 1478887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 1488887Sgeoffrey.blake@arm.com if buildEnv['TARGET_ISA'] in ['arm']: 1498887Sgeoffrey.blake@arm.com from ArmTLB import ArmTLB 1508887Sgeoffrey.blake@arm.com 1518887Sgeoffrey.blake@arm.com self.checker = O3Checker(workload=self.workload, 1528887Sgeoffrey.blake@arm.com exitOnError=False, 1538887Sgeoffrey.blake@arm.com updateOnError=True, 1548887Sgeoffrey.blake@arm.com warnOnlyOnLoadError=True) 1558887Sgeoffrey.blake@arm.com self.checker.itb = ArmTLB(size = self.itb.size) 1568887Sgeoffrey.blake@arm.com self.checker.dtb = ArmTLB(size = self.dtb.size) 1579132Satgutier@umich.edu self.checker.cpu_id = self.cpu_id 1588887Sgeoffrey.blake@arm.com 1598887Sgeoffrey.blake@arm.com else: 1608887Sgeoffrey.blake@arm.com print "ERROR: Checker only supported under ARM ISA!" 1618887Sgeoffrey.blake@arm.com exit(1) 162