O3CPU.py revision 9341
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Kevin Lim 284486Sbinkertn@umich.edu 296654Snate@binkert.orgfrom m5.defines import buildEnv 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 321681SN/Afrom BaseCPU import BaseCPU 333223SN/Afrom FUPool import * 348887Sgeoffrey.blake@arm.comfrom O3Checker import O3Checker 354486Sbinkertn@umich.edu 362817SN/Aclass DerivO3CPU(BaseCPU): 372817SN/A type = 'DerivO3CPU' 389341SAndreas.Sandberg@arm.com cxx_header = 'cpu/o3/deriv.hh' 399341SAndreas.Sandberg@arm.com 402932SN/A activity = Param.Unsigned(0, "Initial count") 411681SN/A 424597Sbinkertn@umich.edu cachePorts = Param.Unsigned(200, "Cache Ports") 431681SN/A 449184Sandreas.hansson@arm.com decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 459184Sandreas.hansson@arm.com renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 469184Sandreas.hansson@arm.com iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 479184Sandreas.hansson@arm.com "delay") 489184Sandreas.hansson@arm.com commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 492932SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 502932SN/A 519184Sandreas.hansson@arm.com renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 529184Sandreas.hansson@arm.com iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 539184Sandreas.hansson@arm.com "delay") 549184Sandreas.hansson@arm.com commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 559184Sandreas.hansson@arm.com fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 562932SN/A decodeWidth = Param.Unsigned(8, "Decode width") 571681SN/A 589184Sandreas.hansson@arm.com iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 599184Sandreas.hansson@arm.com "delay") 609184Sandreas.hansson@arm.com commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 619184Sandreas.hansson@arm.com decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 622932SN/A renameWidth = Param.Unsigned(8, "Rename width") 631681SN/A 649184Sandreas.hansson@arm.com commitToIEWDelay = Param.Cycles(1, "Commit to " 652932SN/A "Issue/Execute/Writeback delay") 669184Sandreas.hansson@arm.com renameToIEWDelay = Param.Cycles(2, "Rename to " 672932SN/A "Issue/Execute/Writeback delay") 689184Sandreas.hansson@arm.com issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 692932SN/A "to the IEW stage)") 702932SN/A dispatchWidth = Param.Unsigned(8, "Dispatch width") 712932SN/A issueWidth = Param.Unsigned(8, "Issue width") 722932SN/A wbWidth = Param.Unsigned(8, "Writeback width") 732932SN/A wbDepth = Param.Unsigned(1, "Writeback depth") 743223SN/A fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 752932SN/A 769184Sandreas.hansson@arm.com iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 771681SN/A "delay") 789184Sandreas.hansson@arm.com renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 792932SN/A commitWidth = Param.Unsigned(8, "Commit width") 802932SN/A squashWidth = Param.Unsigned(8, "Squash width") 819184Sandreas.hansson@arm.com trapLatency = Param.Cycles(13, "Trap latency") 829184Sandreas.hansson@arm.com fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 831681SN/A 842932SN/A backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 852932SN/A forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 861681SN/A 872932SN/A predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 882932SN/A localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 892932SN/A localCtrBits = Param.Unsigned(2, "Bits per counter") 902932SN/A localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 912932SN/A localHistoryBits = Param.Unsigned(11, "Bits for the local history") 922932SN/A globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 932932SN/A globalCtrBits = Param.Unsigned(2, "Bits per counter") 943223SN/A globalHistoryBits = Param.Unsigned(13, "Bits of history") 952932SN/A choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 962932SN/A choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 971681SN/A 982932SN/A BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 992932SN/A BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 1002873SN/A 1012932SN/A RASSize = Param.Unsigned(16, "RAS size") 1021681SN/A 1032932SN/A LQEntries = Param.Unsigned(32, "Number of load queue entries") 1042932SN/A SQEntries = Param.Unsigned(32, "Number of store queue entries") 1058199SAli.Saidi@ARM.com LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1068199SAli.Saidi@ARM.com LSQCheckLoads = Param.Bool(True, 1078199SAli.Saidi@ARM.com "Should dependency violations be checked for loads & stores or just stores") 1088519SAli.Saidi@ARM.com store_set_clear_period = Param.Unsigned(250000, 1098519SAli.Saidi@ARM.com "Number of load/store insts before the dep predictor should be invalidated") 1102932SN/A LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1112932SN/A SSITSize = Param.Unsigned(1024, "Store set ID table size") 1121681SN/A 1132932SN/A numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1141681SN/A 1152932SN/A numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1162932SN/A numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1172932SN/A "registers") 1182932SN/A numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 1192932SN/A numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 1201681SN/A 1212932SN/A instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 1221681SN/A 1234597Sbinkertn@umich.edu smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 1244597Sbinkertn@umich.edu smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 1254597Sbinkertn@umich.edu smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 1264597Sbinkertn@umich.edu smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 1274597Sbinkertn@umich.edu smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 1284597Sbinkertn@umich.edu smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 1294597Sbinkertn@umich.edu smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 1304597Sbinkertn@umich.edu smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 1314597Sbinkertn@umich.edu smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 1324303SN/A 1338727Snilay@cs.wisc.edu needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 1348727Snilay@cs.wisc.edu "Enable TSO Memory model") 1358887Sgeoffrey.blake@arm.com 1368887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 1378887Sgeoffrey.blake@arm.com if buildEnv['TARGET_ISA'] in ['arm']: 1388887Sgeoffrey.blake@arm.com from ArmTLB import ArmTLB 1398887Sgeoffrey.blake@arm.com 1408887Sgeoffrey.blake@arm.com self.checker = O3Checker(workload=self.workload, 1418887Sgeoffrey.blake@arm.com exitOnError=False, 1428887Sgeoffrey.blake@arm.com updateOnError=True, 1438887Sgeoffrey.blake@arm.com warnOnlyOnLoadError=True) 1448887Sgeoffrey.blake@arm.com self.checker.itb = ArmTLB(size = self.itb.size) 1458887Sgeoffrey.blake@arm.com self.checker.dtb = ArmTLB(size = self.dtb.size) 1469132Satgutier@umich.edu self.checker.cpu_id = self.cpu_id 1478887Sgeoffrey.blake@arm.com 1488887Sgeoffrey.blake@arm.com else: 1498887Sgeoffrey.blake@arm.com print "ERROR: Checker only supported under ARM ISA!" 1508887Sgeoffrey.blake@arm.com exit(1) 151