O3CPU.py revision 8199
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Kevin Lim 284486Sbinkertn@umich.edu 296654Snate@binkert.orgfrom m5.defines import buildEnv 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 321681SN/Afrom BaseCPU import BaseCPU 333223SN/Afrom FUPool import * 348887Sgeoffrey.blake@arm.com 354486Sbinkertn@umich.eduif buildEnv['USE_CHECKER']: 362817SN/A from O3Checker import O3Checker 372817SN/A 382932SN/Aclass DerivO3CPU(BaseCPU): 391681SN/A type = 'DerivO3CPU' 404597Sbinkertn@umich.edu activity = Param.Unsigned(0, "Initial count") 411681SN/A 422932SN/A if buildEnv['USE_CHECKER']: 432932SN/A if not buildEnv['FULL_SYSTEM']: 442932SN/A checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 452932SN/A exitOnError=False, 462932SN/A updateOnError=True, 472932SN/A warnOnlyOnLoadError=False), 482932SN/A "checker") 492932SN/A else: 502932SN/A checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, 511681SN/A warnOnlyOnLoadError=False), "checker") 522932SN/A checker.itb = Parent.itb 532932SN/A checker.dtb = Parent.dtb 542932SN/A 551681SN/A cachePorts = Param.Unsigned(200, "Cache Ports") 562932SN/A icache_port = Port("Instruction Port") 571681SN/A dcache_port = Port("Data Port") 582932SN/A _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port'] 592932SN/A 602932SN/A decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 611681SN/A renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 622932SN/A iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 632932SN/A "delay") 642932SN/A commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 652932SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 662932SN/A 672932SN/A renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 682932SN/A iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 692932SN/A "delay") 702932SN/A commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 712932SN/A fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 723223SN/A decodeWidth = Param.Unsigned(8, "Decode width") 732932SN/A 742932SN/A iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 751681SN/A "delay") 762932SN/A commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 772932SN/A decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 782932SN/A renameWidth = Param.Unsigned(8, "Rename width") 792932SN/A 802932SN/A commitToIEWDelay = Param.Unsigned(1, "Commit to " 811681SN/A "Issue/Execute/Writeback delay") 822932SN/A renameToIEWDelay = Param.Unsigned(2, "Rename to " 832932SN/A "Issue/Execute/Writeback delay") 841681SN/A issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 852932SN/A "to the IEW stage)") 862932SN/A dispatchWidth = Param.Unsigned(8, "Dispatch width") 872932SN/A issueWidth = Param.Unsigned(8, "Issue width") 882932SN/A wbWidth = Param.Unsigned(8, "Writeback width") 892932SN/A wbDepth = Param.Unsigned(1, "Writeback depth") 902932SN/A fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 912932SN/A 923223SN/A iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 932932SN/A "delay") 942932SN/A renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 951681SN/A commitWidth = Param.Unsigned(8, "Commit width") 962932SN/A squashWidth = Param.Unsigned(8, "Squash width") 972932SN/A trapLatency = Param.Tick(13, "Trap latency") 982873SN/A fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 992932SN/A 1001681SN/A backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 1012932SN/A forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1022932SN/A 1038199SAli.Saidi@ARM.com predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 1048199SAli.Saidi@ARM.com localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 1058199SAli.Saidi@ARM.com localCtrBits = Param.Unsigned(2, "Bits per counter") 1068519SAli.Saidi@ARM.com localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 1078519SAli.Saidi@ARM.com localHistoryBits = Param.Unsigned(11, "Bits for the local history") 1082932SN/A globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 1092932SN/A globalCtrBits = Param.Unsigned(2, "Bits per counter") 1101681SN/A globalHistoryBits = Param.Unsigned(13, "Bits of history") 1112932SN/A choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 1121681SN/A choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 1132932SN/A 1142932SN/A BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 1152932SN/A BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 1162932SN/A 1172932SN/A RASSize = Param.Unsigned(16, "RAS size") 1181681SN/A 1192932SN/A LQEntries = Param.Unsigned(32, "Number of load queue entries") 1201681SN/A SQEntries = Param.Unsigned(32, "Number of store queue entries") 1214597Sbinkertn@umich.edu LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1224597Sbinkertn@umich.edu LSQCheckLoads = Param.Bool(True, 1234597Sbinkertn@umich.edu "Should dependency violations be checked for loads & stores or just stores") 1244597Sbinkertn@umich.edu LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1254597Sbinkertn@umich.edu SSITSize = Param.Unsigned(1024, "Store set ID table size") 1264597Sbinkertn@umich.edu 1274597Sbinkertn@umich.edu numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1284597Sbinkertn@umich.edu 1294597Sbinkertn@umich.edu numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1304303SN/A numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1318727Snilay@cs.wisc.edu "registers") 1328727Snilay@cs.wisc.edu numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 1338887Sgeoffrey.blake@arm.com numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 1348887Sgeoffrey.blake@arm.com 1358887Sgeoffrey.blake@arm.com instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 1368887Sgeoffrey.blake@arm.com 1378887Sgeoffrey.blake@arm.com smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 1388887Sgeoffrey.blake@arm.com smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 1398887Sgeoffrey.blake@arm.com smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 1408887Sgeoffrey.blake@arm.com smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 1418887Sgeoffrey.blake@arm.com smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 1428887Sgeoffrey.blake@arm.com smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 1438887Sgeoffrey.blake@arm.com smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 1449132Satgutier@umich.edu smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 1458887Sgeoffrey.blake@arm.com smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 1468887Sgeoffrey.blake@arm.com 1478887Sgeoffrey.blake@arm.com def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 1488887Sgeoffrey.blake@arm.com BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) 149 self.icache.tgts_per_mshr = 20 150 self.dcache.tgts_per_mshr = 20 151