O3CPU.py revision 4997
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Kevin Lim 284486Sbinkertn@umich.edu 293102SN/Afrom m5.params import * 303102SN/Afrom m5.proxy import * 312667SN/Afrom m5 import build_env 321681SN/Afrom BaseCPU import BaseCPU 333223SN/Afrom FUPool import * 341681SN/A 354486Sbinkertn@umich.eduif build_env['USE_CHECKER']: 364486Sbinkertn@umich.edu from O3Checker import O3Checker 374486Sbinkertn@umich.edu 382817SN/Aclass DerivO3CPU(BaseCPU): 392817SN/A type = 'DerivO3CPU' 402932SN/A activity = Param.Unsigned(0, "Initial count") 412932SN/A numThreads = Param.Unsigned(1, "number of HW thread contexts") 421681SN/A 432362SN/A if build_env['FULL_SYSTEM']: 442362SN/A profile = Param.Latency('0ns', "trace the kernel stack") 452932SN/A if build_env['USE_CHECKER']: 462932SN/A if not build_env['FULL_SYSTEM']: 472932SN/A checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 483223SN/A exitOnError=False, 493223SN/A updateOnError=True, 502932SN/A warnOnlyOnLoadError=False), 512932SN/A "checker") 522932SN/A else: 533223SN/A checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, 543223SN/A warnOnlyOnLoadError=False), "checker") 554997Sgblack@eecs.umich.edu checker.itb = Parent.itb 564997Sgblack@eecs.umich.edu checker.dtb = Parent.dtb 572318SN/A 584597Sbinkertn@umich.edu cachePorts = Param.Unsigned(200, "Cache Ports") 592871SN/A icache_port = Port("Instruction Port") 602871SN/A dcache_port = Port("Data Port") 612998SN/A _mem_ports = ['icache_port', 'dcache_port'] 621681SN/A 632932SN/A decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 642932SN/A renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 652932SN/A iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 662932SN/A "delay") 672932SN/A commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 682932SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 692932SN/A 702932SN/A renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 712932SN/A iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 721681SN/A "delay") 732932SN/A commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 742932SN/A fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 752932SN/A decodeWidth = Param.Unsigned(8, "Decode width") 761681SN/A 772932SN/A iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 781681SN/A "delay") 792932SN/A commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 802932SN/A decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 812932SN/A renameWidth = Param.Unsigned(8, "Rename width") 821681SN/A 832932SN/A commitToIEWDelay = Param.Unsigned(1, "Commit to " 842932SN/A "Issue/Execute/Writeback delay") 852932SN/A renameToIEWDelay = Param.Unsigned(2, "Rename to " 862932SN/A "Issue/Execute/Writeback delay") 872932SN/A issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 882932SN/A "to the IEW stage)") 892932SN/A dispatchWidth = Param.Unsigned(8, "Dispatch width") 902932SN/A issueWidth = Param.Unsigned(8, "Issue width") 912932SN/A wbWidth = Param.Unsigned(8, "Writeback width") 922932SN/A wbDepth = Param.Unsigned(1, "Writeback depth") 933223SN/A fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 942932SN/A 952932SN/A iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 961681SN/A "delay") 972932SN/A renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 982932SN/A commitWidth = Param.Unsigned(8, "Commit width") 992932SN/A squashWidth = Param.Unsigned(8, "Squash width") 1002932SN/A trapLatency = Param.Tick(13, "Trap latency") 1012932SN/A fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 1021681SN/A 1032932SN/A backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 1042932SN/A forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1051681SN/A 1062932SN/A predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 1072932SN/A localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 1082932SN/A localCtrBits = Param.Unsigned(2, "Bits per counter") 1092932SN/A localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 1102932SN/A localHistoryBits = Param.Unsigned(11, "Bits for the local history") 1112932SN/A globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 1122932SN/A globalCtrBits = Param.Unsigned(2, "Bits per counter") 1133223SN/A globalHistoryBits = Param.Unsigned(13, "Bits of history") 1142932SN/A choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 1152932SN/A choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 1161681SN/A 1172932SN/A BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 1182932SN/A BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 1192873SN/A 1202932SN/A RASSize = Param.Unsigned(16, "RAS size") 1211681SN/A 1222932SN/A LQEntries = Param.Unsigned(32, "Number of load queue entries") 1232932SN/A SQEntries = Param.Unsigned(32, "Number of store queue entries") 1242932SN/A LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1252932SN/A SSITSize = Param.Unsigned(1024, "Store set ID table size") 1261681SN/A 1272932SN/A numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1281681SN/A 1292932SN/A numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1302932SN/A numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1312932SN/A "registers") 1322932SN/A numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 1332932SN/A numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 1341681SN/A 1352932SN/A instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 1361681SN/A 1371681SN/A function_trace = Param.Bool(False, "Enable function trace") 1381681SN/A function_trace_start = Param.Tick(0, "Cycle to start function trace") 1392294SN/A 1404597Sbinkertn@umich.edu smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 1414597Sbinkertn@umich.edu smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 1424597Sbinkertn@umich.edu smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 1434597Sbinkertn@umich.edu smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 1444597Sbinkertn@umich.edu smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 1454597Sbinkertn@umich.edu smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 1464597Sbinkertn@umich.edu smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 1474597Sbinkertn@umich.edu smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 1484597Sbinkertn@umich.edu smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 1494303SN/A 1504303SN/A def addPrivateSplitL1Caches(self, ic, dc): 1514303SN/A BaseCPU.addPrivateSplitL1Caches(self, ic, dc) 1524303SN/A self.icache.tgts_per_mshr = 20 1534303SN/A self.dcache.tgts_per_mshr = 20 154