O3CPU.py revision 4597
15390SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 25446SN/A# All rights reserved. 35390SN/A# 45390SN/A# Redistribution and use in source and binary forms, with or without 55390SN/A# modification, are permitted provided that the following conditions are 65390SN/A# met: redistributions of source code must retain the above copyright 75390SN/A# notice, this list of conditions and the following disclaimer; 85390SN/A# redistributions in binary form must reproduce the above copyright 95390SN/A# notice, this list of conditions and the following disclaimer in the 105390SN/A# documentation and/or other materials provided with the distribution; 115390SN/A# neither the name of the copyright holders nor the names of its 125390SN/A# contributors may be used to endorse or promote products derived from 135390SN/A# this software without specific prior written permission. 145390SN/A# 155390SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165390SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175390SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185390SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195390SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205390SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215390SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225390SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235390SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245390SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255390SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265390SN/A# 275390SN/A# Authors: Kevin Lim 285390SN/A 295390SN/Afrom m5.params import * 305390SN/Afrom m5.proxy import * 315637Sgblack@eecs.umich.edufrom m5 import build_env 325637Sgblack@eecs.umich.edufrom BaseCPU import BaseCPU 335390SN/Afrom FUPool import * 345636SN/A 355390SN/Aif build_env['USE_CHECKER']: 365390SN/A from O3Checker import O3Checker 375636SN/A 385636SN/Aclass DerivO3CPU(BaseCPU): 395636SN/A type = 'DerivO3CPU' 405636SN/A activity = Param.Unsigned(0, "Initial count") 415636SN/A numThreads = Param.Unsigned(1, "number of HW thread contexts") 425636SN/A 435643Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 445636SN/A profile = Param.Latency('0ns', "trace the kernel stack") 455636SN/A if build_env['USE_CHECKER']: 465636SN/A if not build_env['FULL_SYSTEM']: 475390SN/A checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 485390SN/A exitOnError=False, 495636SN/A updateOnError=True, 505446SN/A warnOnlyOnLoadError=False), 515446SN/A "checker") 525636SN/A else: 535636SN/A checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, 545636SN/A warnOnlyOnLoadError=False), "checker") 555636SN/A checker.itb = Parent.itb 565636SN/A checker.dtb = Parent.dtb 575643Sgblack@eecs.umich.edu 585390SN/A cachePorts = Param.Unsigned(200, "Cache Ports") 595446SN/A icache_port = Port("Instruction Port") 605390SN/A dcache_port = Port("Data Port") 615390SN/A _mem_ports = ['icache_port', 'dcache_port'] 625390SN/A 635390SN/A decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 645390SN/A renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 655390SN/A iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 665390SN/A "delay") 675390SN/A commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 685390SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 695390SN/A 705637Sgblack@eecs.umich.edu renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 71 iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 72 "delay") 73 commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 74 fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 75 decodeWidth = Param.Unsigned(8, "Decode width") 76 77 iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 78 "delay") 79 commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 80 decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 81 renameWidth = Param.Unsigned(8, "Rename width") 82 83 commitToIEWDelay = Param.Unsigned(1, "Commit to " 84 "Issue/Execute/Writeback delay") 85 renameToIEWDelay = Param.Unsigned(2, "Rename to " 86 "Issue/Execute/Writeback delay") 87 issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 88 "to the IEW stage)") 89 dispatchWidth = Param.Unsigned(8, "Dispatch width") 90 issueWidth = Param.Unsigned(8, "Issue width") 91 wbWidth = Param.Unsigned(8, "Writeback width") 92 wbDepth = Param.Unsigned(1, "Writeback depth") 93 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 94 95 iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 96 "delay") 97 renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 98 commitWidth = Param.Unsigned(8, "Commit width") 99 squashWidth = Param.Unsigned(8, "Squash width") 100 trapLatency = Param.Tick(13, "Trap latency") 101 fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 102 103 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 104 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 105 106 predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 107 localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 108 localCtrBits = Param.Unsigned(2, "Bits per counter") 109 localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 110 localHistoryBits = Param.Unsigned(11, "Bits for the local history") 111 globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 112 globalCtrBits = Param.Unsigned(2, "Bits per counter") 113 globalHistoryBits = Param.Unsigned(13, "Bits of history") 114 choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 115 choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 116 117 BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 118 BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 119 120 RASSize = Param.Unsigned(16, "RAS size") 121 122 LQEntries = Param.Unsigned(32, "Number of load queue entries") 123 SQEntries = Param.Unsigned(32, "Number of store queue entries") 124 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 125 SSITSize = Param.Unsigned(1024, "Store set ID table size") 126 127 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 128 129 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 130 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 131 "registers") 132 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 133 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 134 135 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 136 137 function_trace = Param.Bool(False, "Enable function trace") 138 function_trace_start = Param.Tick(0, "Cycle to start function trace") 139 140 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 141 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 142 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 143 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 144 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 145 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 146 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 147 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 148 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 149 150 def addPrivateSplitL1Caches(self, ic, dc): 151 BaseCPU.addPrivateSplitL1Caches(self, ic, dc) 152 self.icache.tgts_per_mshr = 20 153 self.dcache.tgts_per_mshr = 20 154