O3CPU.py revision 13665
12SN/A# Copyright (c) 2016, 2019 ARM Limited 21762SN/A# All rights reserved. 32SN/A# 42SN/A# The license below extends only to copyright in the software and shall 52SN/A# not be construed as granting a license to any other intellectual 62SN/A# property including but not limited to intellectual property relating 72SN/A# to a hardware implementation of the functionality of the software 82SN/A# licensed hereunder. You may use the software subject to the license 92SN/A# terms below provided that you ensure that this notice is replicated 102SN/A# unmodified and in its entirety in all distributions of the software, 112SN/A# modified or unmodified, in source code or in binary form. 122SN/A# 132SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 142SN/A# All rights reserved. 152SN/A# 162SN/A# Redistribution and use in source and binary forms, with or without 172SN/A# modification, are permitted provided that the following conditions are 182SN/A# met: redistributions of source code must retain the above copyright 192SN/A# notice, this list of conditions and the following disclaimer; 202SN/A# redistributions in binary form must reproduce the above copyright 212SN/A# notice, this list of conditions and the following disclaimer in the 222SN/A# documentation and/or other materials provided with the distribution; 232SN/A# neither the name of the copyright holders nor the names of its 242SN/A# contributors may be used to endorse or promote products derived from 252SN/A# this software without specific prior written permission. 262SN/A# 272665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292665Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382SN/A# 392SN/A# Authors: Kevin Lim 402SN/A 412SN/Afrom __future__ import print_function 422SN/A 432SN/Afrom m5.defines import buildEnv 444762Snate@binkert.orgfrom m5.params import * 4556SN/Afrom m5.proxy import * 461127SN/A 472SN/Afrom m5.objects.BaseCPU import BaseCPU 482797Sktlim@umich.edufrom m5.objects.FUPool import * 492797Sktlim@umich.edufrom m5.objects.O3Checker import O3Checker 502609SN/Afrom m5.objects.BranchPredictor import * 512SN/A 522SN/Aclass FetchPolicy(ScopedEnum): 532SN/A vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ] 542SN/A 552SN/Aclass SMTQueuePolicy(ScopedEnum): 561127SN/A vals = [ 'Dynamic', 'Partitioned', 'Threshold' ] 572SN/A 581553SN/Aclass CommitPolicy(ScopedEnum): 592797Sktlim@umich.edu vals = [ 'Aggressive', 'RoundRobin', 'OldestReady' ] 602901Ssaidi@eecs.umich.edu 612839Sktlim@umich.educlass DerivO3CPU(BaseCPU): 622901Ssaidi@eecs.umich.edu type = 'DerivO3CPU' 632797Sktlim@umich.edu cxx_header = 'cpu/o3/deriv.hh' 643202Shsul@eecs.umich.edu 652901Ssaidi@eecs.umich.edu @classmethod 662901Ssaidi@eecs.umich.edu def memory_mode(cls): 672797Sktlim@umich.edu return 'timing' 68265SN/A 692797Sktlim@umich.edu @classmethod 701553SN/A def require_caches(cls): 711553SN/A return True 722797Sktlim@umich.edu 732797Sktlim@umich.edu @classmethod 742SN/A def support_take_over(cls): 752SN/A return True 762SN/A 772SN/A activity = Param.Unsigned(0, "Initial count") 782SN/A 792SN/A cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 804762Snate@binkert.org "Constrains stores only. Loads are constrained by load FUs.") 814762Snate@binkert.org 824762Snate@binkert.org decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 832SN/A renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 844762Snate@binkert.org iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 854762Snate@binkert.org "delay") 864762Snate@binkert.org commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 872SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 882SN/A fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 895034Smilesck@eecs.umich.edu fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 905034Smilesck@eecs.umich.edu "per-thread") 915034Smilesck@eecs.umich.edu 925034Smilesck@eecs.umich.edu renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 935034Smilesck@eecs.umich.edu iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 945034Smilesck@eecs.umich.edu "delay") 951553SN/A commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 96265SN/A fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 971127SN/A decodeWidth = Param.Unsigned(8, "Decode width") 981127SN/A 99465SN/A iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 100465SN/A "delay") 101465SN/A commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 1022SN/A decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 1032SN/A renameWidth = Param.Unsigned(8, "Rename width") 1042SN/A 105330SN/A commitToIEWDelay = Param.Cycles(1, "Commit to " 1062SN/A "Issue/Execute/Writeback delay") 1072SN/A renameToIEWDelay = Param.Cycles(2, "Rename to " 1082SN/A "Issue/Execute/Writeback delay") 1092SN/A issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 110330SN/A "to the IEW stage)") 111330SN/A dispatchWidth = Param.Unsigned(8, "Dispatch width") 112330SN/A issueWidth = Param.Unsigned(8, "Issue width") 113395SN/A wbWidth = Param.Unsigned(8, "Writeback width") 114395SN/A fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 1152797Sktlim@umich.edu 116938SN/A iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 1172609SN/A "delay") 1182609SN/A renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 1192901Ssaidi@eecs.umich.edu commitWidth = Param.Unsigned(8, "Commit width") 1202901Ssaidi@eecs.umich.edu squashWidth = Param.Unsigned(8, "Squash width") 1212901Ssaidi@eecs.umich.edu trapLatency = Param.Cycles(13, "Trap latency") 1222901Ssaidi@eecs.umich.edu fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 1232797Sktlim@umich.edu 1242797Sktlim@umich.edu backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 1252797Sktlim@umich.edu forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1262797Sktlim@umich.edu 1272609SN/A LQEntries = Param.Unsigned(32, "Number of load queue entries") 1281031SN/A SQEntries = Param.Unsigned(32, "Number of store queue entries") 1291031SN/A LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1301031SN/A LSQCheckLoads = Param.Bool(True, 1311031SN/A "Should dependency violations be checked for loads & stores or just stores") 1321031SN/A store_set_clear_period = Param.Unsigned(250000, 1331031SN/A "Number of load/store insts before the dep predictor should be invalidated") 1345314Sstever@gmail.com LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1355314Sstever@gmail.com SSITSize = Param.Unsigned(1024, "Store set ID table size") 1365314Sstever@gmail.com 1375314Sstever@gmail.com numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1385314Sstever@gmail.com 1395314Sstever@gmail.com numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1405314Sstever@gmail.com numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 141938SN/A "registers") 142938SN/A # most ISAs don't use condition-code regs, so default is 0 1432SN/A _defaultNumPhysCCRegs = 0 1442SN/A if buildEnv['TARGET_ISA'] in ('arm','x86'): 1452SN/A # For x86, each CC reg is used to hold only a subset of the 146 # flags, so we need 4-5 times the number of CC regs as 147 # physical integer regs to be sure we don't run out. In 148 # typical real machines, CC regs are not explicitly renamed 149 # (it's a side effect of int reg renaming), so they should 150 # never be the bottleneck here. 151 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 152 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 153 "registers") 154 numPhysVecPredRegs = Param.Unsigned(32, "Number of physical predicate " 155 "registers") 156 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 157 "Number of physical cc registers") 158 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 159 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 160 161 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 162 smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy") 163 smtLSQPolicy = Param.SMTQueuePolicy('Partitioned', 164 "SMT LSQ Sharing Policy") 165 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 166 smtIQPolicy = Param.SMTQueuePolicy('Partitioned', 167 "SMT IQ Sharing Policy") 168 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 169 smtROBPolicy = Param.SMTQueuePolicy('Partitioned', 170 "SMT ROB Sharing Policy") 171 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 172 smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy") 173 174 branchPred = Param.BranchPredictor(TournamentBP(numThreads = 175 Parent.numThreads), 176 "Branch Predictor") 177 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 178 "Enable TSO Memory model") 179 180 def addCheckerCpu(self): 181 if buildEnv['TARGET_ISA'] in ['arm']: 182 from m5.objects.ArmTLB import ArmTLB 183 184 self.checker = O3Checker(workload=self.workload, 185 exitOnError=False, 186 updateOnError=True, 187 warnOnlyOnLoadError=True) 188 self.checker.itb = ArmTLB(size = self.itb.size) 189 self.checker.dtb = ArmTLB(size = self.dtb.size) 190 self.checker.cpu_id = self.cpu_id 191 192 else: 193 print("ERROR: Checker only supported under ARM ISA!") 194 exit(1) 195