O3CPU.py revision 13610
110259SAndrew.Bardsley@arm.com# Copyright (c) 2016, 2019 ARM Limited 210259SAndrew.Bardsley@arm.com# All rights reserved. 310259SAndrew.Bardsley@arm.com# 410259SAndrew.Bardsley@arm.com# The license below extends only to copyright in the software and shall 510259SAndrew.Bardsley@arm.com# not be construed as granting a license to any other intellectual 610259SAndrew.Bardsley@arm.com# property including but not limited to intellectual property relating 710259SAndrew.Bardsley@arm.com# to a hardware implementation of the functionality of the software 810259SAndrew.Bardsley@arm.com# licensed hereunder. You may use the software subject to the license 910259SAndrew.Bardsley@arm.com# terms below provided that you ensure that this notice is replicated 1010259SAndrew.Bardsley@arm.com# unmodified and in its entirety in all distributions of the software, 1110259SAndrew.Bardsley@arm.com# modified or unmodified, in source code or in binary form. 1210259SAndrew.Bardsley@arm.com# 1310259SAndrew.Bardsley@arm.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 1410259SAndrew.Bardsley@arm.com# All rights reserved. 1510259SAndrew.Bardsley@arm.com# 1610259SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 1710259SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 1810259SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 1910259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 2010259SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 2110259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 2210259SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 2310259SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 2410259SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 2510259SAndrew.Bardsley@arm.com# this software without specific prior written permission. 2610259SAndrew.Bardsley@arm.com# 2710259SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2810259SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2910259SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3010259SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3110259SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3210259SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3310259SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3410259SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3510259SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3610259SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3710259SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3810259SAndrew.Bardsley@arm.com# 3910259SAndrew.Bardsley@arm.com# Authors: Kevin Lim 4010259SAndrew.Bardsley@arm.com 4110259SAndrew.Bardsley@arm.comfrom __future__ import print_function 4210259SAndrew.Bardsley@arm.com 4310259SAndrew.Bardsley@arm.comfrom m5.defines import buildEnv 4410259SAndrew.Bardsley@arm.comfrom m5.params import * 4510259SAndrew.Bardsley@arm.comfrom m5.proxy import * 4610259SAndrew.Bardsley@arm.comfrom BaseCPU import BaseCPU 4710259SAndrew.Bardsley@arm.comfrom FUPool import * 4810259SAndrew.Bardsley@arm.comfrom O3Checker import O3Checker 4910785Sgope@wisc.edufrom BranchPredictor import * 5010259SAndrew.Bardsley@arm.com 5110259SAndrew.Bardsley@arm.comclass FetchPolicy(ScopedEnum): 5210259SAndrew.Bardsley@arm.com vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ] 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.comclass SMTQueuePolicy(ScopedEnum): 5510259SAndrew.Bardsley@arm.com vals = [ 'Dynamic', 'Partitioned', 'Threshold' ] 5610259SAndrew.Bardsley@arm.com 5710259SAndrew.Bardsley@arm.comclass CommitPolicy(ScopedEnum): 5810259SAndrew.Bardsley@arm.com vals = [ 'Aggressive', 'RoundRobin', 'OldestReady' ] 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.comclass DerivO3CPU(BaseCPU): 6110259SAndrew.Bardsley@arm.com type = 'DerivO3CPU' 6210259SAndrew.Bardsley@arm.com cxx_header = 'cpu/o3/deriv.hh' 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.com @classmethod 6510259SAndrew.Bardsley@arm.com def memory_mode(cls): 6610259SAndrew.Bardsley@arm.com return 'timing' 6710259SAndrew.Bardsley@arm.com 6810259SAndrew.Bardsley@arm.com @classmethod 6910259SAndrew.Bardsley@arm.com def require_caches(cls): 7010259SAndrew.Bardsley@arm.com return True 7110259SAndrew.Bardsley@arm.com 7210259SAndrew.Bardsley@arm.com @classmethod 7310259SAndrew.Bardsley@arm.com def support_take_over(cls): 7410259SAndrew.Bardsley@arm.com return True 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.com activity = Param.Unsigned(0, "Initial count") 7710259SAndrew.Bardsley@arm.com 7810259SAndrew.Bardsley@arm.com cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 7910259SAndrew.Bardsley@arm.com "Constrains stores only. Loads are constrained by load FUs.") 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.com decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 8210259SAndrew.Bardsley@arm.com renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 8310259SAndrew.Bardsley@arm.com iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 8410259SAndrew.Bardsley@arm.com "delay") 8510259SAndrew.Bardsley@arm.com commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 8610259SAndrew.Bardsley@arm.com fetchWidth = Param.Unsigned(8, "Fetch width") 8710259SAndrew.Bardsley@arm.com fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 8810259SAndrew.Bardsley@arm.com fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 8910259SAndrew.Bardsley@arm.com "per-thread") 9010259SAndrew.Bardsley@arm.com 9110259SAndrew.Bardsley@arm.com renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 9210259SAndrew.Bardsley@arm.com iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 9310259SAndrew.Bardsley@arm.com "delay") 9410259SAndrew.Bardsley@arm.com commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 9510259SAndrew.Bardsley@arm.com fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 9610259SAndrew.Bardsley@arm.com decodeWidth = Param.Unsigned(8, "Decode width") 9710259SAndrew.Bardsley@arm.com 9810259SAndrew.Bardsley@arm.com iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 9910259SAndrew.Bardsley@arm.com "delay") 10010259SAndrew.Bardsley@arm.com commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 10110259SAndrew.Bardsley@arm.com decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 10210259SAndrew.Bardsley@arm.com renameWidth = Param.Unsigned(8, "Rename width") 10310259SAndrew.Bardsley@arm.com 10410259SAndrew.Bardsley@arm.com commitToIEWDelay = Param.Cycles(1, "Commit to " 10510259SAndrew.Bardsley@arm.com "Issue/Execute/Writeback delay") 10610259SAndrew.Bardsley@arm.com renameToIEWDelay = Param.Cycles(2, "Rename to " 10710259SAndrew.Bardsley@arm.com "Issue/Execute/Writeback delay") 10810259SAndrew.Bardsley@arm.com issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 10910259SAndrew.Bardsley@arm.com "to the IEW stage)") 11010259SAndrew.Bardsley@arm.com dispatchWidth = Param.Unsigned(8, "Dispatch width") 11110259SAndrew.Bardsley@arm.com issueWidth = Param.Unsigned(8, "Issue width") 11210259SAndrew.Bardsley@arm.com wbWidth = Param.Unsigned(8, "Writeback width") 11310259SAndrew.Bardsley@arm.com fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 11610259SAndrew.Bardsley@arm.com "delay") 11710259SAndrew.Bardsley@arm.com renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 11810259SAndrew.Bardsley@arm.com commitWidth = Param.Unsigned(8, "Commit width") 11910259SAndrew.Bardsley@arm.com squashWidth = Param.Unsigned(8, "Squash width") 12010259SAndrew.Bardsley@arm.com trapLatency = Param.Cycles(13, "Trap latency") 12110259SAndrew.Bardsley@arm.com fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 12210259SAndrew.Bardsley@arm.com 12310259SAndrew.Bardsley@arm.com backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 12410259SAndrew.Bardsley@arm.com forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 12510259SAndrew.Bardsley@arm.com 12610259SAndrew.Bardsley@arm.com LQEntries = Param.Unsigned(32, "Number of load queue entries") 12710259SAndrew.Bardsley@arm.com SQEntries = Param.Unsigned(32, "Number of store queue entries") 12810259SAndrew.Bardsley@arm.com LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 12910259SAndrew.Bardsley@arm.com LSQCheckLoads = Param.Bool(True, 13010259SAndrew.Bardsley@arm.com "Should dependency violations be checked for loads & stores or just stores") 13110259SAndrew.Bardsley@arm.com store_set_clear_period = Param.Unsigned(250000, 13210259SAndrew.Bardsley@arm.com "Number of load/store insts before the dep predictor should be invalidated") 13310259SAndrew.Bardsley@arm.com LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 13410259SAndrew.Bardsley@arm.com SSITSize = Param.Unsigned(1024, "Store set ID table size") 13510259SAndrew.Bardsley@arm.com 13610259SAndrew.Bardsley@arm.com numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 13710259SAndrew.Bardsley@arm.com 13810259SAndrew.Bardsley@arm.com numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 13910259SAndrew.Bardsley@arm.com numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 14010259SAndrew.Bardsley@arm.com "registers") 14110259SAndrew.Bardsley@arm.com # most ISAs don't use condition-code regs, so default is 0 14210259SAndrew.Bardsley@arm.com _defaultNumPhysCCRegs = 0 14310259SAndrew.Bardsley@arm.com if buildEnv['TARGET_ISA'] in ('arm','x86'): 14410259SAndrew.Bardsley@arm.com # For x86, each CC reg is used to hold only a subset of the 14510259SAndrew.Bardsley@arm.com # flags, so we need 4-5 times the number of CC regs as 14610259SAndrew.Bardsley@arm.com # physical integer regs to be sure we don't run out. In 14710259SAndrew.Bardsley@arm.com # typical real machines, CC regs are not explicitly renamed 14810259SAndrew.Bardsley@arm.com # (it's a side effect of int reg renaming), so they should 14910259SAndrew.Bardsley@arm.com # never be the bottleneck here. 15010259SAndrew.Bardsley@arm.com _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 15110259SAndrew.Bardsley@arm.com numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 15210259SAndrew.Bardsley@arm.com "registers") 15310259SAndrew.Bardsley@arm.com numPhysVecPredRegs = Param.Unsigned(32, "Number of physical predicate " 15410259SAndrew.Bardsley@arm.com "registers") 15510259SAndrew.Bardsley@arm.com numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 15610259SAndrew.Bardsley@arm.com "Number of physical cc registers") 15710259SAndrew.Bardsley@arm.com numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 15810259SAndrew.Bardsley@arm.com numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 15910259SAndrew.Bardsley@arm.com 16010259SAndrew.Bardsley@arm.com smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 16110259SAndrew.Bardsley@arm.com smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy") 16210259SAndrew.Bardsley@arm.com smtLSQPolicy = Param.SMTQueuePolicy('Partitioned', 16310259SAndrew.Bardsley@arm.com "SMT LSQ Sharing Policy") 16410259SAndrew.Bardsley@arm.com smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 16510259SAndrew.Bardsley@arm.com smtIQPolicy = Param.SMTQueuePolicy('Partitioned', 16610259SAndrew.Bardsley@arm.com "SMT IQ Sharing Policy") 16710259SAndrew.Bardsley@arm.com smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 16810259SAndrew.Bardsley@arm.com smtROBPolicy = Param.SMTQueuePolicy('Partitioned', 16910259SAndrew.Bardsley@arm.com "SMT ROB Sharing Policy") 17010259SAndrew.Bardsley@arm.com smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 17110259SAndrew.Bardsley@arm.com smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy") 17210259SAndrew.Bardsley@arm.com 17310259SAndrew.Bardsley@arm.com branchPred = Param.BranchPredictor(TournamentBP(numThreads = 17410259SAndrew.Bardsley@arm.com Parent.numThreads), 17510259SAndrew.Bardsley@arm.com "Branch Predictor") 17610259SAndrew.Bardsley@arm.com needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 17710259SAndrew.Bardsley@arm.com "Enable TSO Memory model") 17810259SAndrew.Bardsley@arm.com 17910259SAndrew.Bardsley@arm.com def addCheckerCpu(self): 18010259SAndrew.Bardsley@arm.com if buildEnv['TARGET_ISA'] in ['arm']: 18110259SAndrew.Bardsley@arm.com from ArmTLB import ArmTLB 18210259SAndrew.Bardsley@arm.com 18310259SAndrew.Bardsley@arm.com self.checker = O3Checker(workload=self.workload, 18410259SAndrew.Bardsley@arm.com exitOnError=False, 18510259SAndrew.Bardsley@arm.com updateOnError=True, 18610259SAndrew.Bardsley@arm.com warnOnlyOnLoadError=True) 18710259SAndrew.Bardsley@arm.com self.checker.itb = ArmTLB(size = self.itb.size) 18810259SAndrew.Bardsley@arm.com self.checker.dtb = ArmTLB(size = self.dtb.size) 18910259SAndrew.Bardsley@arm.com self.checker.cpu_id = self.cpu_id 19010259SAndrew.Bardsley@arm.com 19110259SAndrew.Bardsley@arm.com else: 19210259SAndrew.Bardsley@arm.com print("ERROR: Checker only supported under ARM ISA!") 19310259SAndrew.Bardsley@arm.com exit(1) 19410259SAndrew.Bardsley@arm.com